TWI475415B - Architectural physical synthesis - Google Patents

Description

Entity synthesis of architecture

The present invention relates generally to the field of integrated circuit design, and more particularly to integrated circuit design through a synthesis program in accordance with high order descriptions.

This application claims the benefit of U.S. Provisional Application Serial No. 60/951,436, filed on Jul. 23, 2007, which is incorporated herein by reference. This application is also related to the application ___ of the ___ application, entitled "Entity Synthesis of the Framework" (Archive No. 02986.P058) and applied for it on the same day.

Regarding the design of digital circuits on the scale of VLSI (very large scale integration) technology, designers often use computer-aided technology. Standard languages such as Hardware Description Language (HDL) have been developed to illustrate digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved into industry standards. VHDL and Verilog are general-purpose hardware description languages that allow abstract data types to be used to define a hardware model at the wafer prototype level, scratchpad transfer level (RTL), or behavior level. As device technology continues to advance, various product design tools have been developed to make HDL suitable for newer devices and design styles.

In designing an integrated circuit using an HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code specifies the circuit components at a level, and then the compiler generates an RTL circuit plan list (netlist) based on the compilation. An RTL circuit planning list consists of a plurality of RTL objects or components and a plurality of networks between the components Signal connection. The RTL circuit planning list can be a technically independent circuit planning list because it is independent of the technology or architecture of a particular vendor's integrated circuit, such as a field programmable gate array (FPGA) or a specific application integrated circuit (ASIC). ). The RTL circuit plan list corresponds to a schematic representation of one of the circuit elements (relative to a behavioral representation). A mapping operation is then performed to transition from the technology independent RTL circuit planning list to a particular technology circuit planning list that can be used to build circuits in the vendor's technology or architecture, including placing the instances and arranging the interconnect paths So that the circuit meets the given timing, space and power constraints.

Early Electronic Design Automation (EDA) generally separated HDL synthesis from the placement/scheduling path procedure shown in Figure 1. In operation 11, an HDL code is prepared. In operation 13, the HDL prepared in operation 11 is compiled and synthesized to produce a circuit plan list that is generally optimized by performing logic optimization. Thereafter, a mapping program maps the circuit planning list to a specific target technology/architecture. At the end of operation 13, the synthesis is completed and a circuit plan list is provided that is specific to the technology/architecture used in the vendor's IC. This circuit planning list is effectively at a gate level, and timing analysis is estimated based on statistical models such as fan-out counts or pre-amplification information for the type and size of connected components using these interconnect characteristics. After synthesis, a conventional placement operation is performed on the logic circuit in operation 15 where the circuit planning list (only on a wafer prototype or cell or gate level) is locally changed to meet timing performance. A conventional scheduling path operation is then performed in operation 19 to establish a circuit design in each IC of the ICs. If any of the unconstrained constraints exist, the program uses the loopback to return to repair

change.

In the past, when the case delays dominated the early synthesis tools, the timing estimates based on the statistical models were sufficiently accurate, so that the separation synthesis and placement requirements were relatively small and returned to the HDL and synthesis stages.

However, as technology nodes continue to shrink, these interconnect delays become significant, exceeding the gate delay. This results in less and less delay estimates in the synthesis operation associated with the actual delays after placement and scheduling of the path operations, resulting in insufficient timing predictability between post-synthesis and post-layout results. Thus, in many cases, after such placement and routing procedures, the circuit entity layout cannot meet the circuit design criteria, so designers often have to start from the synthesis step and repeat the synthesis/placement/arrange path procedures.

In order to improve the synthesis, it is important to account for the physical characteristics associated with the design (eg, placement) during the synthesis procedure. A range of techniques have been employed to bring placement information into the synthesis process, such as floorplans, on-site optimization (IPO), and physical synthesis.

In the floorplanning technique, the design is divided into multiple regions on the wafer and interconnected with the placement is estimated for inter-regional interconnection, while statistical models are used to estimate the interconnections within an area. The floor plan can be used either in the early RTL phase or later after running an initial synthesis. The floor plan can be extended to divide, copy, and slice the RTL components into multiple regions and combine the RTL hierarchical timing and area models. The improved timing from inter-region timing can then be used to drive RTL level optimization more precisely. Manually producing a better quality floor plan is challenging and demanding User. An automatic floor plan similar to that from Tera Systems (US Patents 6, 145, 117 and 6, 360, 356) establishes an area and assigns an RTL component to it. Because the synthesis system is decoupled and follows the automatic floor plan, the accuracy of the timing and area information during the floor plan is poor.

A technique called on-site optimization (IPO) provides for the placement and scheduling of inverse interpretation of path delays into the synthesis domain. The critical path is re-optimized, but because the detailed placement is not updated, the interconnect delay for the modified network is returned to the statistical model. If many changes are made, the following legalization of the resulting circuit plan list may require that the instance be moved away from its initial position, resulting in a larger delay estimation error. For this reason, IPO is unstable when significant changes are required to obtain timing closure.

Another technique is entity synthesis, which is an improvement over one of the IPO techniques in which a small amount of optimization and incremental re-legalization interleaving on a mapping circuit planning list maintains the fidelity of delay and resource metrics. One limitation of this technique is that individual changes are limited to the most appropriate resource increase or the instability of the IPO technology resurface treatment. Currently, there are several different algorithms for entity synthesis. Figure 2 shows an algorithm that provides a physical synthesis engine using timing estimates based on the proximity of the placement items. After the mapping circuit plan list is initially placed in operation 23, portions of the entity synthesis operation selection circuit are used for incremental optimization and relocation in operation 24 that is only performed at the wafer prototype level.

From the foregoing, it can be seen that there is a need for an algorithmic improvement for electronic design automation.

The prior patent also relates to or describes wafer synthesis, and the patents include: U.S. Patents 6,519,754, 6,711,729, 7,010,769, 6,145,117 and 6,360,356. The placement algorithm was recently written in: Bo Hu, Timing-Driven Placement for Heterogeneous Field Programmable Gate Array (Time Series Driven Placement for Heterogeneous Field Programmable Gate Arrays), IEEE/ACM International Computer Aided Design Workshop, 2006 11 Month (ICCAD '06), pp. 383-388 (ISSN: 1092-3152, ISBN 1-59593-389-1).

The present invention discloses a method and apparatus for designing an integrated circuit. In an exemplary embodiment, the circuit design of the present invention reveals a repetitive process of synthesis and placement that begins at an RTL or behavioral level, where each of the inverses provides an incremental change through the transformation of the integrated circuit design. In a particular aspect, the transformation can be a composite or placement transformation. A synthetic transformation modifies the objects within the circuit planning list and/or the network forming a connection between the objects. A placement transformation modifies the location of one or more objects in the circuit planning list. The incremental reversal scheme of at least some embodiments of the present invention provides a continuous progression using appropriate synthesis and placement transformations as determined by current circuit circuit planning manifests, placement, timing, resource availability, and power design metrics. In a particular aspect, after each transformation, the affected design metrics are updated such that future transformation decisions are based on an accurate design statistic. The program is incrementally repeated towards the final timing resources and power closure of the design.

A key aspect of at least one particular embodiment of the present invention is that placement occurs before a particular resource type has been identified for a higher order component. For example, the classification is used for alternative implementations of components with the required weights and the total number of associated resources The scheme and the placer evolve the placement to move the components close to the type of resource used for the desired implementation.

In a preferred embodiment, the invention begins with a diagram representing one of the wafer resources RTL or behavioral design (circuitry) and a physical map. A reverse transformation is performed in which one of the circuits or objects in each of the transformation generation circuits is optimized or refined.

In a specific embodiment, a transform consists of a high order optimization. This transformation optimizes a component or a plurality of components into a set of functionally equivalent alternative components through a regular or mathematical transformation that has excellent characteristics such as timing, power, or resource consumption. An example of this transformation is to reorganize the arithmetic expression to reduce the height of the tree to improve the delay. Another example is resource sharing or not sharing.

In another embodiment, the high order optimization transform refines the circuit object(s) of the group(s) from a more abstract form to a more specific form. An example of a refined transformation maps an arithmetic expression to a DSP resource on the wafer. When refining an abstract form, there are often many implementation options. For example, an arithmetic expression can be performed by a special purpose arithmetic function on the wafer (a DSP block), by a table lookup (LUT or gate and flip-flop) in a memory or on a wafer. The hierarchical logic components are implemented externally. Components from a behavioral composite stream may have multiple implementations based on alternative scheduling and resource sharing registrations. Such alternatives for behavioral components can also be dynamically generated based on currently available resources and interconnect delays.

In another embodiment, the refinement transformations are also based on alternative realities. The quality of the program has an urgent metric and is selected in urgent order. The quality of an embodiment is measured according to design goals such as area consumption, power consumption, or timing. Other more esoteric targets such as single event flip hardness can also be included. For example, if a design includes a large memory and a plurality of small memories, and the large memory has a relatively poor implementation quality when implemented by a logical fabric, the large memory and the wafer are scarce in the design. Special-purpose memory resources are much more important than medium-sized memory. The emergency metric for this large memory will be much higher than the metric for these small memories. Once the components are mapped to a particular implementation and associated with particular resources on the wafer, the connections to the components serve as anchors for the remainder of the placement circuitry, thereby improving the quality of timing and available resource estimates.

In one embodiment, the placement transformation may be refined by one of the locations of one or more configurable items to improve placement metrics such as example congestion, arrangability, and circuit performance. A configurable object can be comprised of a behavioral composition component, an unmapped logic RTL chunk, mapping logic, or any combination of these.

In a specific embodiment, the placement transformation can modify objects of different levels of abstraction. For example, some of the configurable items may be RTL chunks, while others may map gates.

In another embodiment, a refinement transform is triggered when the placement is fully evolved such that the available resources can be determined and the scheduled path delay is estimated.

In accordance with another aspect of the present invention, an exemplary method for designing an integrated circuit provides an incremental transform repeat, wherein the composite and placement transforms are not In any order, but only for its functionality. The circuit design automation is based on a selection function to select the next transformation, ie synthesis or placement. At each iteration, the cost for a predetermined list of changes is calculated. This cost may include predictions of changes in costs of other transformations. For example, if an arithmetic operation is mapped to a ROM, the ROM option can be removed to perform another operation, thereby increasing its cost. The optimal transformation is selected based on cost convergence criteria such as current placement, circuit planning inventory, resources, timing, or power.

The next transformation may be a placement update, a resource assignment, a synthesis optimization, a placement optimization, or an arrangement of path updates. As a result, the state of the IC design is moving toward the final circuit specification and layout.

In another embodiment, the placement transformations are performed repeatedly until the critical path begins to form or until resources are fully dispersed in accordance with a predetermined congestion threshold. The criteria for repetitive performance are timing, congestion per resource layer, area utilization, and power.

Congestion per resource layer can be determined by using the resource layer. There is a resource layer for each of the different prototype type resources on the wafer. For example, today's FPGAs and structured ASICs have introduced irregular layouts of prototype wafer resources. These prototype types include logic (LUT), flip-flops, special I/O units for high-speed serial interconnects (such as SERDES), various memory components with different capacities and high-speed arithmetic chunks to accelerate DSP algorithms. In addition to logic and flip-flops, in general, these resources are included in a sparse and possibly irregular manner. Many FPGAs have a limited amount of RAM, DSP, and other dedicated logic blocks that are sparsely arranged on the wafer. For example, DSP arithmetic chunks may be available in only 2 rows within the wafer layout. One The resource layer is a distribution map established for each prototype type and records the placement of available resource locations for that type and the placement of prototypes of that type. A layer is considered to be congested when there is a localized physical area that is used more than supplied.

In one typical example of this method, an initial state of the integrated circuit design is produced from a high-order representation with timing constraints and placement constraints, such as an IO pin, an existing floor plan, or an existing placement. The higher order representation can be a hardware description language (HDL) code or a technically independent RTL circuit planning list compiled after a hardware description language (HDL) code.

In one embodiment, the circuit planning list of the initial state of the integrated circuit design is optimized based on a series of neutral optimizations based on timing. The neutral optimization may be one of any areas that may be easily revoked (such as resource sharing or non-common); adder tree decomposition, preferably based on fan-out table timing; a resource assignment, circuit planning One of the lists flattens to promote optimization across the hierarchy; the multiplexer captures or reconstructs.

In one embodiment, the general flow of the design state of the integrated circuit progresses from an RTL circuit planning list to a decomposition and factorization, and then to a mapping and scheduling path circuit planning list. Placement modifications, resource assignments, and area or timing optimization are implemented through the entire flow.

In one embodiment, the refinement placement and circuit architecture procedures are repeated until all of the higher order components have been assigned a particular implementation and resource assignment and the placement has been spread across the wafer such that each component has sufficient nearby resources for implementation. A more conventional physical synthesis stream can be used to complete this embodiment from now on.

In another embodiment, the applied transform and its potential replacement are recorded example. This stream can be repeated and these alternative transformations can be applied to achieve better results.

The present invention also discloses apparatus including software media that can be used to design integrated circuits. For example, the present invention includes a digital processing system capable of designing an integrated circuit in accordance with the present invention, and the present invention also provides a machine readable medium that causes the digital processing system to be executed on a digital processing system, such as a computer system A method for designing an integrated circuit is implemented.

Other features of the invention will be apparent from the description and drawings.

Methods and apparatus for designing an integrated circuit or a plurality of integrated circuits are described herein. In the following description, for the purposes of illustration However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In other instances, well-known structures, <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

The present invention discloses a method and apparatus for designing an integrated circuit. In a specific embodiment, it is placed and combined in a single pass. One embodiment of the present invention discloses a physical compositing procedure, referred to as architectural entity compositing, in which interaction between compositing and placement occurs at an architectural level. This allows the synthesis to occur with the actual physical placement on one of the substrates of the integrated circuit, thereby providing a usable local resource that is closely related to the delay estimate to the synthesis from the actual circuit timing of the placement, and thus can simultaneously consider the synthesis and The interaction between placements. In addition, this provides an automated way to make high-level architectural decisions that map high-level components in one way. Or performing high-order circuit transformations to account for placement, congestion estimation, and characteristics of the target wafer architecture, including but not limited to physical distribution of different resources, component delays, and interconnect delays. In accordance with one aspect of the present invention, it is recognized that given a circuit design or an HDL code representation, there are a number of alternative implementations of inter-chain synthesis and placement, particularly for an existing floor plan having one of a given distribution resource. . In order to achieve an optimal design implementation, it is more important to be able to return to an earlier synthesis decision based on the currently available circuit data (such as timing or power) collected through the placement.

Thus, in one aspect of the invention, in high-order designs or behavioral representations, placement is performed in an early synthesis cycle, such as at a circuit architecture level, to allow for an accurate assessment of the applicability of various design implementations. This is especially important for pre-diffused wafers such as FPGAs and structured ASICs where resources are unevenly distributed across the wafer. In pre-diffused wafers, resource locations and resource types are predetermined and distributed in a sparse manner. For example, today's FPGAs and structured ASICs have introduced irregular layouts of wafer resources. These components may include logic, flip-flops, special I/O units for high-speed serial interconnects (such as SERDES), various memory components with different capacities and high-speed arithmetic chunks to accelerate DSP algorithms. Many FPGAs have a limited amount of RAM, DSP, and other dedicated logic blocks that are sparsely arranged on the wafer. For example, DSP arithmetic chunks may be available in only 2 rows within the wafer layout.

In one aspect, the present invention addresses this change in wafer architecture evolution to integrate entity placement and architecture selection at the beginning of the composite stream. This requirement can be at the RTL level or at the behavioral synthesis level, where different types of requirements are determined The number of sources.

The current awareness of resource layout information and the integration of placement and synthesis in an early synthesis process (e.g., when an assembly has not been selected for many components) provides an optimal resource utilization. For example, an RTL synthesis program that is unaware of resource layout information may result in an intermediate circuit planning list that overuses some resource material while other resource types are underutilized. In addition, these resource type decisions may not be compatible with the physical location of the resources. For example, multiple DSP resources beyond the available ones may be required within one of the localized portions of the wafer. The synthesis method can provide an efficient use of the resources by knowing the distribution of the resources on the wafer and not only knowing that there is enough specific resources, but also knowing that there are sufficient resources nearby. Thus, large interconnect delays due to the delivery of signals to different placement resources can be avoided.

In accordance with one aspect of the present invention, various placement decisions are made while the synthesis is still in a higher order circuit representation (e.g., many components in a design may still not have a selected implementation) or a gate level specification is yet to be determined. These placement decisions may enable accurate evaluation of circuit parameters, such as timing delay or power consumption, thereby permitting an incremental path toward an optimal design implementation. In one embodiment, as shown in FIG. 3, in operation 30, the program begins with an initial state of the IC design, which may include an ESL or HDL language, a behavioral abstraction, or a compiled HDL code to the RTL circuit planning list. One of the high-level abstractions, plus timing, floor plans, power, and placement constraints. In operation 31, a synthetic transformation is performed which will be a higher order transformation at an early stage of the procedure. This composite transformation may only be part of this design. in In operation 32, the placement transformation is performed on the existing circuit representation and, at an early stage, will be placed at an architectural level. This placement transformation may only be part of the design. Such placement decisions at this time may require various assumptions and estimates as detailed information may be missed at this early stage. The IC state is then ready for operation at operation 34, and if it meets the design and legal goals, then move to the traditional entity synthesis in operation 48. As may be possible at this early stage, if these goals are not met, the loop will be returned to another round of synthesis.

The next synthetic iteration (current operation 31) will improve the design representation, especially after having physical placement information (previous operation 32). And similarly, the next placement override (current operation 32) will improve its circuit parameter estimates after having a synthesis improvement. Using such close loops, the synthesis and placement can work together to provide a path to an optimal design representation without significant redoing.

In one embodiment, the synthesizing operation provides various implementations for a circuit design representation, and the placement operation can perform circuit parameter analysis to help narrow down the options. For example, if implementation #1 is significantly better, it will be selected and the number of potential implementations will be reduced to one. Alternatively, if implementation #2 clearly falls outside the scope of such design constraints, it will be excluded, thereby reducing the number of potential implementations by one.

In accordance with one aspect of the present invention, an exemplary method for designing a plurality of integrated circuits proposes an integration, interaction, and recombination and placement from an abstract machine specification. In one embodiment, the exemplary method of designing an integrated circuit incrementally changes the state of the IC design. Start with an initial state of IC design that includes ESL or HDL language, a behavioral abstraction, or a compilation A high-level abstraction of the HDL code to RTL circuit planning list, plus timing, floor plan, power, and placement constraints, the incremental method incrementally and repeatedly changes the IC design state until an optimized design state is reached. The optimized state is preferably a wafer prototype hierarchical circuit planning list that satisfies the timing and placement constraints, which can then be passed to a conventional placement and routing procedure without any extensive redoing.

According to one aspect, the present invention discloses a repetitive process of synthesis and placement in which each of the inverses provides incremental changes in the design of the integrated circuit. A general example of a particular embodiment of the invention will be provided with reference to FIG. The method of Figure 4 begins at operation 40 where an initial state of an IC design is generated. The initial state of the IC design includes a behavioral representation or high-order RTL circuit planning list that can be compiled by an HDL source code that describes the circuit and logic.

The technical independent RTL circuit planning list is generally a higher order behavior representation of the design. This saves the abstract information for use by the program before the final mapping step. This is different from traditional synthesis tools, which segment the design into a fine, low-level (gate) representation immediately after language compilation. By preserving a higher order behavioral representation, a synthesis tool can perform optimizations, partitioning and planarizing the map at a far more global level and generally delivering better results. By working on abstract data, the compositing tool can also operate and process larger designs faster. The high-order RTL circuit planning list contains high-order abstractions that are independent of any particular vendor technology or architecture, such as circuit block representations.

The initial state of the IC design further includes timing constraints, power constraints, and placement constraints, such as IO header locations, existing floor plans, or existing placements (eg, size and shape of the IC die, IP chunks). In operation 42, increment Change the state of the IC design. The state of the integrated circuit design generally includes a circuit planning list, timing information, resource information, placement information, routing information, and power data. Incremental changes in the design state can be combined or modified, and will be further described below. In one aspect of the invention, the variations are incremental, meaning that the design optimizations generally continue with minor modifications to all current information such as timing estimates and placement constraints. These incremental changes allow the design to progress with confidence and progress steadily. In one aspect, the incremental changes involve an incremental global placement algorithm, such as a force steering method. In another aspect, the incremental changes involve a global optimization algorithm, such as simulated annealing. In operation 44, the state of the IC design is evaluated, and in operation 46 it is determined whether to continue to repeat by return operation 42, or to complete the design flow at operation 48 to make a decision.

This circuit design method provides a highly integrated and interactive procedure between two basic steps in the design of an integrated circuit, namely, synthesis and physical design (eg, placement and routing). Conceptually, the synthesis and placement are strongly interdependent. Since there is no resettlement, the design constraints cannot be accurately estimated in the synthesis, and there is no synthesis, and the resettlement cannot be implemented. Therefore, the design method of the present invention uses the incremental and repeated scheme to effectively combine the synthesis and the placement into a one-step procedure.

In a specific embodiment, the present invention provides a reversal of one of the synthesis/placement transformations. The body of the repeated procedure may be a combination of a placement transformation, a synthetic transformation, or a synthesis and placement transformation. In either case, the state of the integrated circuit design changes incrementally and repeatedly toward the synthesis or placement of the wafer prototype hierarchy circuit planning list that satisfies one of the design goals. Figures 5A and 5B show two examples for designing a portion of an IC stream; the square shown in Figure 5A In the case of the method, a placement transformation occurs first, followed by a synthetic transformation, and in Fig. 5B, a reverse situation occurs. The incremental and repeated transformations of synthesis, placement, or synthesis/placement provide a continuous reversal between synthesis and placement at either state of the design. The incremental and repetitive progress of the synthesis and placement ensures that the synthetic transformation always has the most up-to-date and accurate design state information, including delay information from the placement transformation and local resource availability, and wherein the placement transformations are always based on the most recent synthetic circuit planning list. To provide the best estimate for entity placement and scheduling path information. The placement and synthesis transformations continue until the circuit planning list consists of only wafer level prototypes that meet these design goals and then reduces placement congestion to a level where a detailed placer can easily legalize any smaller local area independently. This stream can be followed by a conventional entity synthesis stream to complete the implementation.

Figure 6 shows a specific embodiment of the invention for incrementally changing the design state of an IC. The present invention can place all levels of abstraction simultaneously. During the early iterations, objects at a higher level of abstraction are more prevalent than later in the design where the design consists primarily of wafer prototypes. These wafer prototypes are generally the lowest order representations. Synthetic transformations gradually modify the circuit plan list to turn those objects at a higher level of abstraction into more specific objects. These specific items have more specific resource requirements and are then considered in the following synthesis and placement transformations. The placement transformation determines the location of the circuit planning list item, ie, the RTL instance, the unmapped instance item, the mapping example item, or the wafer prototype level item, thereby determining the length and delay of the network in the circuit along with the router. The placement transformation can be placed over a legally placed gradual repeating circuit, where legal placement means that the rules governing the use of resources of the leading IC chip are met. Generally In this early reversal, the placement will be illegal. Since the placement change is incrementally changed at the location of the object, a single iteration of the placement transformation will not be established in a legal placement. The placement will become legal through repeated placement changes. In this particular embodiment, the placement transformation is the center of the electronic design automation.

In each iteration, the criteria for a repeat may be time series data, congestion per resource layer, area utilization, power level, or any combination thereof. The method can further include a possible internal loop reversal to optimize the design to shape the critical path, or to spread the resources to a predetermined threshold.

In one embodiment of the method of the present invention, which uses an incrementally repeated synthesis and placement transformation, the entity design information can always be used in the synthesis transformation at all stages of the design. Thus, such optimizations and transformations in the synthesis are always up-to-date in terms of timing and region and also in arranging pathological effects. The decision-making and placement of the circuit structure is fully coordinated in the synthesis.

The inventive method of incrementally recombining and arranging transformations effectively combines the synthesis and placement transformations to simultaneously optimize the logical structure and spatial placement of a circuit. In a typical example of this approach, the state of the integrated circuit design progresses toward the final circuit specification and layout.

The progress of the reversal placement transformation may be one of a circuit planning list or a placement configuration to increase the maturity level. The maturity of a design is made up of only the wafer level prototypes by the circuit planning list, satisfying the design goals and reducing the placement congestion to a certain level. One detail placer can easily legalize any smaller part independently. The extent of the area is measured.

The progress of the inverse synthetic transformation can be optimized for a synthesis, such as an object Or entity reconstruction or replication to meet timing constraints. Synthesis optimization includes, but is not limited to, a circuit optimization, an abstract component decomposition, an arithmetic mapping, an undo/restore resource sharing, an adder tree decomposition, a placement based and/or gate decomposition, path replication, and a Path detour removal, an assignment to discrete resources such as RAM or DSP, a logic factorization, multiplexer reconstruction, or a circuit planning list is flattened to promote optimization across the hierarchy.

A specific embodiment of this method is shown in Figure 6, beginning with an operation 61 in which an initial state of an IC design is generated. The state of the IC design can be an RTL network with associated status information such as timing information, resource information, placement information, routing information, and/or power data. In general, the state of the IC design contains enough information to specify such circuit requirements, such as functionality, timing, power, and floor plan.

The high-order RTL circuit planning list contains a circuit planning list in which most objects are abstractions of these low-order wafer prototypes. Associated prototypes for multiple groups may be represented as objects using a higher order representation that represents the functionality encoded by the RTL. The higher order or abstract representation of the integrated circuit design can be a logical object that represents an RTL code or portion thereof. Each object generally represents a plurality of wafer prototypes, such as more complex functions such as adders, multipliers, multiplexers and sequential logic, as well as AND functions, OR functions. Objects represented by higher order may also include memory chunks or private (intellectual property chunks or IP) chunks. Other logical objects may be part of the RTL code to provide support functions such as glue logic (providing buffer or interface functions), timing logic, control logic or memory logic. Some high-order RTL objects may also be wafer level prototypes. The object circuit planning list also includes information related to each item for routing and placement. The objects may include information to map back to the corresponding RTL code.

In addition, the RTL code can include a hierarchy in which the functions are grouped together. In some cases, components may be regrouped from one level to another to optimize timing, routing, area, or power requirements. In other cases, the merged functional RTL hierarchy may be flattened, in whole or in part, during the incremental repeat procedure.

Initially, the initial state of the design may include constraints such as timing constraints, power constraints, and/or placement constraints. For example, the placement constraints may include the location of the IO pin, the existing floor plan, or existing placement information.

In an exemplary embodiment, the initial state of the design is first optimized by a series of timing-based neutral optimizations. Such neutral optimizations include any regional replies that can be easily revoked, such as undo/restore resource sharing; adder tree decomposition based on fan-out table timing; significant resource refinement, for example, if there is a huge in design RAM and only one RAM chunk resource is available, then the RAM has to go there; flatten the merged circuit plan list to promote optimization across the hierarchy; and capture and reconstruct the multiplexer structure.

Based on the current design state (current placement, circuit planning list, timing, power, and scheduling path), a change is selected in operation 62 to incrementally change the state of the IC design. Operations 63 through 70 are typical transformations in accordance with an embodiment of the present invention, including placement or update placement (63), assignment of resources (64), factorization (65), mapping (66), optimization logic (67) , establish/refine the implementation plan (68), update the route (69) and other synthesis (70). Such Transformations are generally small, incremental operations to permit seamless integration of placement and synthesis, such that placement knowledge is used to perform the synthesis, and synthetic knowledge is used to perform the placement.

These repeated and incremental transforms 63 through 70 thus include placement and synthesis operations, including optimization transformations such as undo/restore resource sharing, adder tree decomposition, AND/OR gate decomposition, logical replication, bit splicing. ), round-trip removal, factorization, and placement transformations (such as assignments to discrete resources (RAM, DSP, etc.) and scheduling paths.

In an exemplary embodiment, various potential transformations are evaluated based on a cost function at each iteration, operation 62. The cost function is designed to operate with the choice of the best transform, and thus includes design status information such as timing, placement congestion, scheduled path congestion, area utilization, and power. After the evaluation, the best transformation is implemented and the continuation continues until the design constraints are met. In one aspect, the design can then continue to the conventional gate placement and routing.

In each iteration, the method browses a selection list and then selects the best transformation based on a cost function. For example, the choice between a placement transformation and a composite transformation is based on a timing closure criterion. On a critical path, if possible, placement can try to shorten critical networks. If the critical network cannot be shortened, then those networks can be used for physical synthesis optimization.

In accordance with another aspect of the present invention, an exemplary method for designing an integrated circuit provides a transform reversal wherein the synthesizing and placement transforms are not in any order, but are selected only for their functionality. This method provides a better integration between synthesis and placement, where within the inverse, based on integrated circuit design The state is selected to select the next transformation to progress toward the final configuration with timing and placement constraints. In a specific embodiment, the method provides a transform selection algorithm in which the next transform is selected based on specific criteria such as timing, per-resource layer congestion, area utilization, and power. The next transformation can be one of the placement updates, where the circuit will undergo a repetitive to place changes to the current circuit planning list with less resource congestion or better meet the design goals. The next transformation can be a synthetic optimization, such as a factorization, an optimization, or a decomposition. The next transformation can be a synthetic optimization, such as segmentation, reconstruction, or replication to meet timing or critical path requirements. The next transformation can be synthesized, where the current circuit planning list can be mapped to a lower level of abstraction toward the wafer prototype hierarchical circuit planning list to finalize the circuit specifications and layout or update routing paths.

The next transformation may be a placement optimization, such as floor plan partitioning, resource assignment, logical reconstruction or replication to meet timing or critical path requirements, or a path for an item placement update schedule. The next transformation can be a compositing operation in which the current circuit planning list can be mapped to a lower level of abstraction toward the wafer prototype hierarchical circuit planning list to finalize the circuit specifications and layout.

Using incremental transforms, design state information such as timing and power is up to date, and optimization can be performed because of the ability to accurately view the impact on the target.

In an alternative embodiment, several transforms are selected. Each selected transform is then applied to measure the effect on the design state and return or revoke. Then select and apply the best transformation.

In a specific embodiment, one of the key steps of the present invention is operation 68, which establishes or refines the possible implementation of each RTL object in the circuit planning list. plan selection. An associated function implements an estimate of the shape and resources required for alternative embodiments of the alternatives to the embodiments. In another embodiment, operation 68 may also assign weights to various embodiments, indicating a preferred embodiment. One of the key advantages of the present invention that incorporates synthesis and placement at an architectural level is that it allows for the evaluation of different architectural implementations. Without the use of this architecture entity synthesis, once an implementation plan is selected during the RTL synthesis phase, it will be impossible to recover high-level information during the quasi-relocation phase of the gate. This can lead to suboptimality if other embodiments are preferred. Therefore, if you use entity information to make implementation decisions at the RTL level, you can get better timing results. This transformation is extremely difficult to implement once the circuit has been mapped for placement and scheduling.

As it proceeds over and the design state is refined, operation 68 excludes implementation options with inferior properties. An example of function F will be used to interpret operation 68, which implements F = S & (A * C) ∥ ~ S & (B * C). If the selection signal S is 1, the F system is multiplied by C, and if S is 0, the F system B is multiplied by C. Operation 68 determines a possible implementation alternative to this function. 10A and 10B illustrate two possible implementation alternatives that the setup/refinishment implementation operation can establish for this function. FIG. 10A shows an embodiment utilizing two multipliers and a multiplexer, which may be desirable when the output F system timing is critical and the selection signal S has the most recent arrival time. Figure 10B shows an embodiment utilizing a single multiplier and multiplexer that would be more desirable when the input C-system arrives at the most recent signal or when the output F is non-timing critical and requires area reduction. The two alternatives illustrate resource sharing/non-sharing. Do not use information about the timing and placement of this feature, a typical high-level synthesis The algorithm will generally not evaluate an alternative such as Figure 10A because it uses resources for two very expensive multipliers. This is the case even in the case where the placement of the legacy stream is placed near the dedicated unused multiplier resource, its output is critical and the selection signal S arrives after A, B and C. In this invention, operation 68 will establish both of these embodiments, and possibly others, to exclude alternatives when they are clearly below standard. For example, as it goes on, it may be obvious that the output F is not critical. In this case, operation 68 will refine the implementation selection to only Figure 10B, since this alternative uses less resources. Alternatively, operation 68 may exclude the embodiment of FIG. 10B when F is more critical than selection line S and there are nearby resources available to implement the multipliers.

FPGA chips typically have a plurality of pre-diffused memory resources, such as flip-flops, and blocks of variable bit sizes (such as 512, 4K) and MRAM. The memory components required by a design also vary in size. In general, it is not clear how these memory components will be implemented. For example, a modest size RAM between two and 512 bits can be implemented using a flip flop, a 512 resource, or even a 4K resource. Moreover, resource locations for larger memory sizes are generally only sparsely available on the wafer. In previous EDA tools, placement information was not available during the memory implementation phase. Therefore, implementation decisions are made without local use and precise timing information. This limitation can result in severe performance degradation. If a modest amount of RAM is implemented as a 512 resource and the only available 512 location is located away from the logic to which the RAM is connected, then forcing the RAM to be a 512 will result in a longer interconnect and on a chirp implementation. The delay benefit of using a 512 place is invalid. even if The delay of using one of the embodiments of the flip-flop may be longer, but if this embodiment allows for a shorter interconnection between the flip-flop of the RAM and the logic to which the RAM is connected, it may result in a faster design. Alternatively, if there is a 4K resource available in the vicinity of the connection logic of the RAM, it may be advantageous to implement it as 4K. Memory implementation decisions should therefore be made within the consideration of the various available memory resources and the location of the components connected to the memory.

Figure 9A illustrates an example of a memory implementation decision. The figure shows an exemplary wafer with memory resources at the top and bottom of the wafer. A 4-bit RAM is connected to a contact on the right side of the wafer and an AND gate. If the RAM is implemented as a memory and placed on top of the wafer, it can result in an extremely long interconnection to its contact input and to the AND gate it drives. Figure 9B shows an alternative mapping of the same logic. This RAM is implemented using nearby logic and thus shorter interconnects and delays.

A system-function that is closely related to operation 68, which estimates the shape and resources required for an embodiment. In a specific embodiment, this function implements a mapping for the purpose of estimating resources for the RTL component. In another embodiment, this mapping is specific to the target wafer architecture. The resource estimates are based on a synthesis designed to estimate the logic requirements and input/output requirements of a particular component to implement the module in the target architecture. Moreover, in a specific embodiment, the function also estimates the timing transitions for the component.

Figure 7 illustrates an example of an adder that adds two busbars A[31:0] and B[31:0] to produce a third busbar O[31:0]. A transformation is used to estimate the logical region required to implement the adder, and the implementation is estimated to determine the required resource and the internal transition delay from its input to its output. in In a particular aspect, for example, two adder arrays (LABs) can be used to implement the adder, each consisting of 16 lookup tables (LUTs).

Operations 65 through 67 and operation 70 are exemplary synthetic transformations, such as logic factorization (operation 65), logic mapping (operation 66), logic optimization (operation 67), and abstraction (operation 70), where modification is performed by the RTL The components and connections represented by the circuit planning list result in a functional equivalent circuit that improves the design state, such as timing, power. These transformations can add or remove components and their interconnections. The transformation paradigm includes performing one of the components to copy, or splitting an overall RTL component.

This exemplary embodiment represents one of the extremely simple cases of a very large class of implementation choices for I/O, different sized memory, CPU, and DSP. Different designs may want to use these resources in different ways. The abstract transformation of the present invention (i.e., operation 70) can change implementations depending on timing information, location of connection components, utilization of various resource types, and scheduling path utilization. This abstract transformation is similar to the build/render transform (ie, operation 68). While operation 68 establishes a plurality of alternative implementations that are maintained and evaluated in future reversals, the abstract operations are instead abstracted from a more detailed implementation to an abstract component. Various embodiments of the abstract component are considered and the best implementation is chosen to replace the original implementation. This ability avoids an alternative that enumerates all possible architectural mapping choices and runs all of them from top to bottom from mapping, placement, and scheduling paths.

An example of this abstract transformation is given in Figure 11, which shows an adder tree decomposition operation. The adder tree decomposition splits an n-input adder into an m-input adder tree. No delay information is exported from the placement, this optimization will not There is information about where the inputs to the adder are located and the tree can only be roughly estimated based on one of the input arrival times. In this example, if all inputs come from the scratchpad, they have roughly the same arrival time. This decomposition will pick up the combinations of (a, b), (c, d) and (e, f) for the leaf nodes. However, the inputs b and d, a and c can be placed close together. Using the placement information, it is preferable to pick up (a, c), (b, d), (e, f) combinations for the leaf nodes. This will produce better timing at the output.

Another abstract example of gate tree decomposition is shown in Figure 12. A key step in a composite stream is to decompose a large gate (such as a 32 input AND gate) with one of many inputs into a tree representation. The decision that this phase is usually performed early in the flow and on the tree decomposition does not include any information about the location of the drives for the large gate. The present invention includes damper decomposition and re-decomposition as a transformation with placement and timing awareness. The least critical earliest arrival input is placed at the leaf level of the tree and grouped with fewer key inputs near it. When the timing is not a factor, the input signals are grouped by the position of the signal driver.

The optimized logic transformation (ie, operation 67) changes the circuit planning list to optimize design goals, such as timing or power. An example of this optimization transformation is the slicing operation as shown in Figure 13A. If the inputs or outputs of a wider prototype are separated far apart, it may be advantageous to split the prototype. This optimization can only be implemented based on placement information. The following example shows one of the points for a 2-bit memory a[1:0] whose output is very far apart. This memory can be split into two flip-flops, which can then be placed very close to its output.

In another example, a segment is based on the position of its fan-out or fan-in signal. Component. For example, the example shown in Figure 13B shows a memory that has been split into three clusters based on the location of the fanout of the memory. Thus, the original component, which is shown as a single block, has been divided to create three new components that are split according to their corresponding loads. Similar partitioning can be applied based on the input signals of a component. This optimization is more general and not limited to memory.

Another exemplary operation is the logical copy shown in FIG. These conditions for copying are very similar to segmentation. For a component with farther separate inputs or outputs, it may be advantageous to duplicate the component and place it close to a critical load. This optimization can only be implemented based on placement information. The following example shows one of the points for a component a, whose output is very far apart. It can be split into two instance items a_1 and a_2, which can then be placed very close to its output. This is very common when the fanout of the drive is high. Save only one copy of the instance within a given entity.

Another exemplary operation is shown in Figure 15 for Shannon. For logic at the input cone of an RTL component with a large delay, such as an adder or a multiplier, the critical input network can be "pushed" to improve timing. Copy the logic and replace the critical network with constant inputs 0 and 1, then use a multiplexer to select the output of the two operators, and the critical network choose which operator copy is the output. The two logical copies can be further simplified based on the constant inputs. Again, this is an optimization that is best performed under the knowledge of the logical location and the drivers of the critical networks that drive the logic.

Another exemplary operation is Mux/PMux (a PMux is defined as a multiplexer with a one-bit effective coding option) collapse and timing drive. Decomposed as shown in Figures 16A and 16B. Large multiplexers are very common in commercial circuits. Decomposing a multiplexer is similar to the adder tree and/or tree decomposition mentioned earlier, but the selection logic makes the Mux decomposition more difficult, because moving in the tree a little later to reach the input will not only affect the tree structure, but also affect the selection. logic. As with other decompositions, the present invention includes timing information based on placement and scheduling paths to determine appropriate decomposition.

Operation 69 is updating the path of the arrangement. This incrementally repeating method provides better configurable routing for integrated circuits to improve design performance, noise sensitivity, yield, area, and power. This incremental repeat procedure can gradually improve the wiring congestion on the wafer, that is, the density of wiring resources required per unit area.

Many of the transformations mentioned have affected the power consumed by the FPGA. For example, the way in which a memory is decomposed (row form versus column) affects the power it consumes. A column of decomposition uses less power, but requires extra multiplexes, introducing additional delays. A list of row decompositions can be implemented in the present invention to optimize power consumption because accurate delay information can be used using this close connection between synthesis and placement.

Operation 63 is a placement transformation or an update placement transformation. The placement transform modifies the location of the circuit plan list items, such as RTL objects, unmapped instances, or wafer prototype level items, and thereby determines the length and latency of the networks in the circuits along with the router operation.

This placement transformation can use various placement methods depending on the circuit planning list and the maturity of the placement. In an exemplary embodiment, the presentplacer utilizes an incremental algorithm. An incremental algorithm is generated in response to a small input change An algorithm that increments the output of the algorithm. For example, global placement such as force guided placement can be used to place less mature circuit planning lists and placements. The Force Directed Placement (FDP) method is one of the preferred choices for global placement in the present invention because it is an incremental method in which one of the FDPs repeatedly produces incremental placement changes. In general, FDP uses a secondary stylization technique to model the networks and determine how overlapping instances should be spread.

In a specific embodiment, the first step FDP addresses an unconstrained secondary stylization problem that only models the networks interconnecting the instances. This initial answer usually has very high congestion. The FDP then repeatedly constructs the spreading force to move the instance from the area of over-congestion (higher use) to the under-congested area (higher resource availability). The nature of these repeated steps makes the FDP an incremental algorithm. Circuit planning lists or other design status data can be changed between these reversals. As these state changes increase, the resulting changes in the FDP should also increase in the original appearance without a change in design state.

There are various FDP algorithms, but all share the basic concept of calculating the direction in which an item should be moved to resolve an over-congested area. In a particular arrangement, it is assumed that the instances connected by a network are proportional to the quadratic distance between the instances and impose an attraction on each other. In this previous work, all of the items were excluded from each other and attracted to all placements, even if the site was not suitable for the case. The instance is then removed until the system is equalized in a minimum energy state. Thus the FDP method moves the instances based on the direction of the total force imposed thereon.

In one aspect, the present invention provides novel heterogeneous resource placement from a number of The machine can reprogram the wafer and some ASIC design streams to solve these heterogeneous resources. For example, most FPGAs have a variety of predefined wafer resources, such as IO, DSP, RAM, LUT, FF, etc., which are only available at specific locations. These predefined resources are one of the results of the pre-diffusion properties of the FPGA chip. Each resource location has a limit on the number of entities that can be placed in the location. For example, for Altera Stratix-II wafers, 16 or fewer LUTs and FFs can be placed in one LAB location, and there are 3 different RAM locations holding 512 bytes, 4K bytes, and 64K bytes.

In an exemplary embodiment, the incremental placement addresses a heterogeneous resource issue. In an FPGA, structured ASICs and some ASIC chips and resources can be placed only in specific locations that are often unevenly distributed over the placement area. Most global placers (including all previous FDPs) have employed homogeneous resources, regardless of their type, and any of the items can be placed at any effective area within the wafer boundary. This prior approach simplifies this placement problem, since all ranges can be considered as simple linear objects, and as long as the objects do not overlap and are placed within the wafer boundaries, placement will be legal. This simple rectangular model allows adjacent inappropriate resources to place a particular type of instance. This assumption is ignored, for each of these heterogeneous resources, each resource has a specific set of places in which the instance must be placed. Although this "combination" placement may not have any overlap, the placement may not be legal when considering the actual resource type. Some prior work in the simulated annealing placer has taken into account the resource information, but only the placers have been placing the static mapping circuit planning list, not the RTL object. In addition, the use of simulated annealing for far smaller designs has become difficult to use for large designs due to runtime.

In one aspect, the present invention separately models different resource locations such that in all placement transformations, the placer optimizes the resource requirements. In one aspect, the present invention models any number of venue types to become "layers." These layers are used to determine the spreading force on each item. In a specific embodiment, the layers are established in the initialization stages. A layer is created for each resource type that exists on the wafer. The resource locations of a layer are recorded in the supply distribution of the layer at their location. A distribution is a matrix-like, two-dimensional data structure at which a value at the location gives the value of the supply.

Each item is assigned to the (etc.) layer for which it consumes resources. These items that consume a single resource type are called prototype items, while those that consume multiple resources become non-prototypes. An example of a non-prototype would be a state machine that consumes both LUT and FF site types. The resources utilized by the various instances assigned to one layer are recorded in the layer usage profiles. The present invention provides a non-prototype that is processed by recording its area on all layers for which it has resources. These usage contributions will in turn affect the force calculations for the various layers of the non-prototype layers.

For a layer, the difference between its usage and supply distribution is used for the congestion distribution of that layer. As with the previous FDP method, this congestion distribution is used to calculate the force for each instance on the layer.

The force for a non-prototype case is calculated by weighting the forces of the resource layers from its resource layers or based on local congestion of the resources. The weight applied to each layer may be a uniform weighting or a weighting that depends on the relative dispersion of the resources of the layer. Resource dispersion can be characterized Positioning for how far apart the resources are, how sparse the resources are, or distributing the resources evenly or unevenly.

In a specific embodiment, similar to the case of a non-prototype example, a force for a component having one of a plurality of possible implementations is calculated. The force is calculated by weighted averaging the forces from the layers of the resource layer of its implementation. The weighting of the resources applied to the various embodiments may be a uniform weighting or a weighting depending on the probability that a given implementation will be selected.

One advantage of the present invention is that the force of an item depends only on other instances that use the same resource type and the resource supply for that type. For example, if each of items A and B has a portion that uses a resource C, then the force on item A (or on the portion of item A using resource C) depends on the portion of instance B that uses resource C. And also depends on the resources C available for placement. Cases on different layers do not affect each other's spread.

In one aspect, when the global placer terminates, each item will be in or near an effective location suitable for its type, so the placement can be legalized with little improvement. This scheme compares the previous FDP with a novelty. Previous FDP requirements modeled all the instances into a single type and combined all resource regions and then spread the instances on the combined region.

In an exemplary embodiment, the architectural entity synthesis of the present invention may provide improvements to data utilization issues. The situation is often that the wafer resources exceed the requirements of the circuit. For example, in an FPGA design, the circuit to be implemented may require 150 LUTs when the chip or portion of its internal implementation has 256 LUTs. This issue is known as a resource utilization issue. When ignoring the resource utilization problem, the placer will generally spread the circuit instances evenly over the available resources, even if Better results can be achieved by placing one of the different densities on the resources. The previous placer has ignored this issue or imposed an additional "filler" instance. The filler instance is an additional instance that does not add any connectivity to the circuit. Using the "filler" example is also problematic because the position must be determined for these items.

In an exemplary embodiment, the present invention utilizes a region removal method to address the resource utilization problem. As with force generation, consider each resource layer separately. In the region removal method, the resources are utilized based on their quality while removing low quality resources. A quality metric is determined first, and then the resource supply is analyzed to determine one of the resources based on its quality. These low quality parts are then removed from the consideration by the placer as a place of placement. Since the placement changes affect the quality of the resources, the rating and removal can be performed multiple times during the placement process. The program is thus well suited to the repeated and incremental improvements of the present invention in the design state.

In a specific embodiment, the quality metric used to form the rating is based on the distance between the resource and the usage. A method of calculating the force is a convolution of the density distribution of the byproduct layer with a Green function. The result of this convolution can be viewed as a topological map where a higher point indicates a demand for resources and a lower point indicates a lack of demand. Since the distribution is composed of discrete squares, the squares can be selected based on the convolution result. The desire to remove the resource can then be determined by traversing the supply and starting the removal of the resource with the lowest value resource in the convolution pick order until the required requirement is removed. In one aspect, the method can leave sufficient resources such that there are sufficient resources to satisfy the physical requirements on the layer and cause the wafer to be routed.

Alternatively, in other exemplary embodiments, the present invention utilizes a range approach to address this resource utilization problem. In the force range method, the force acting on each of the instances is a weighted average of one of the forces from the plurality of force ranges. In one aspect, the short-range weighting factor is proportional to the density of the instances in the short-range region, with a higher local density resulting in a higher force. This proportionality thus increases the dispersion of instances to reduce overlap.

Using this force range method, the force applied to an item depends on the density of the items of adjacent items. The general idea is that the spread of an item should depend on the area required to legalize the items in its adjacent area. In the most extreme case of congestion, where all of the instances overlap within a small adjacent area, the forces on each instance are calculated based on the location of all instances and all resources. In the case of least congestion, where an item does not have any other items in its vicinity and is directly located on a resource, the item will have no force. For the case between these two extremes, the force depends on the items and resources within the area required to legalize the item.

In a specific embodiment, the range of forces can be cut into local, medium and long range forces. In other embodiments, more or less force ranges may be used. In general, it is a compromise between computational and memory resources to determine the legalized area for an adjacent region and the forces for each legalization range. In one aspect, the forces are calculated by varying the magnitude of the Green's function. The long-range Green's function covers the entire placement area, and the smaller Green's function covers a circular area having, for example, five times the radius of one of the average case areas; and the medium-range Green's function has, for example, 10 times the average case area a radius. The force on one case is the sum of the local, medium and long range of the case. Right and. The weight applied is determined by the density within the neighborhood of the example. If the neighborhood is extremely dense, the long range force will have a very high weight and the local weight will be zero. An item in a low density region will have a zero long range weight and a higher local weight.

Another aspect of the method is the ability to determine important architectural decisions that determine the resources that should be used in implementing an architectural construct. At the architectural level, there are many decisions, such as whether a small RAM should be mapped to a 512-bit RAM resource or a 4k-bit RAM resource on an FPGA. Other examples include the decision of the multiplier implementation and previously stated conditions, such as adder tree decomposition. However, the invention is not limited to these specific examples. Because of the availability of placement information, the present invention refines important architectural implementation decisions that meet these design goals. An exemplary example is where a 1k bit of memory can be assigned to two 512 bit resources or a single 4k bit resource. This embodiment may be critical to a successful implementation when the logic connected to the 1k-bit memory is located close to a 512-bit or 4k-bit location. In the case where the connection logic of the 1k memory is very close to 512 bit resources and the 4k bit resources are further away, a non-optimal mapping to 4k resources will result in a substantially lower performance circuit. It is important to use placement information to make this and other architectural decisions.

In an exemplary embodiment, this embodiment refinement is handled by including a portion of the area of the elastic layer instance in use for each layer that the item may map. In the case of the 1k-bit example, the area of the entity will be partially included in both the 512-layer and the 4k-layer. The force on the example is determined by taking its potential layer to weight one of the forces or to obtain the force with the least amount. The reason behind the ability to get the least amount of value is Thus, the layer associated with this force should have a lower adjacent region density.

In other exemplary embodiments, the resource implementation begins by including instances of multiple possible resource implementations that are not included in the use of any of the layers. These elastic implementation examples are considered after the region removal operations have been performed for all layers. For a flexible implementation example, consider the potential supply of the layers of its possible layers. The potential supply is the area that the removal operation removes from the entire supply by the area. The potential supply on each of the layers of the implementation layer is examined to determine which layer has removed the area that will be least cleavable when the instance is placed within this removal area. The instance is then assigned to the least mitotic layer.

The assigned resource transformation (operation 64) is responsible for deciding to assign an instance of an item to its particular wafer resource. Various placement algorithms can be used for this operation, including force guided placement, simulated annealing, Mongrel, minimum slice placement, numerical optimization placement, evolution-based placement, and other detail placement algorithms.

While most of the specific embodiments of the present invention are intended for use in an HDL design synthesis software program, the invention is not limited to such use. Although other languages and computer programs may be used (eg, a computer program can be written to illustrate the hardware and thus be considered as an expression within an HDL and can be compiled or in some embodiments, the invention can be assigned or re-allocated Allocating a logical representation, such as a circuit planning list, which is not built using an HDL, but will be used in an HDL synthesis system and in particular for such integrated circuits with specific vendor technologies/architectures Specific embodiments of the invention are described in the context of a user. As is well known, the target architecture is generally determined by one of the providers of programmable ICs. An example of a target architecture is a programmatic lookup The associated logic of the table (LUT) and the integrated circuits (which are field programmable gate arrays from Xilinx, Inc., San Jose, CA). Other examples of target architectures/technologies include such well-known architectures in field programmable gate arrays and complex programmable logic devices from vendors such as Altera, Lucent Technology, Advanced Micro Devices, and Lattice Semiconductor. For a particular embodiment, the invention may also be utilized with a particular application integrated circuit (ASIC).

One embodiment of the present invention may be a circuit design and a synthetic computer-aided design software implemented as a computer program stored in a machine readable medium such as a CD ROM or a magnetic hard disk. Or on a compact disc or a variety of other alternative storage devices. Moreover, many of the methods of the present invention can be implemented using a digital processing system, such as a conventional general purpose computer system. Special purpose computers can also be used, which are designed or programmed to perform only one function.

Figure 17 shows an example of a typical computer system that can be used with the present invention. The computer system is used to implement a logical synthesis of one of the designs described in an HDL code. It should be noted that while Figure 17 illustrates various components of a computer system, it is not intended to represent any particular architecture or manner of interconnecting such components, such details are not germane to the present invention. It should be noted that the architecture of Figure 17 is provided for illustrative purposes only and that a computer system or other digital processing system used in connection with the present invention is not limited to this feature architecture. It should also be appreciated that a networked computer and other data processing systems having fewer components or possibly more components may also be used with the present invention. The computer system of Figure 17 may be, for example, an Apple Macintosh computer.

As shown in FIG. 17, a computer system 101 in the form of a data processing system includes a busbar 102 coupled to a microprocessor 103 and a ROM 107 and a volatile RAM 105 and a non-volatile memory 106. . Microprocessor 103 (which may be from one of Intel or Motorola, Inc. or one of IBM's microprocessors) is coupled to cache memory 104. The busbars 102 interconnect the various components together and also interconnect the components 103, 107, 105, and 106 to a display controller and display device 108 and to peripheral devices, such as input/output (I/O) devices, It may be a mouse, keyboard, modem, network interface, printer, scanner, video camera, and other devices well known in the art. In general, input/output device 110 is coupled to the system via input/output controller 109. Non-volatile RAM 105 is typically implemented as a dynamic RAM (DRAM) that continuously requires power to renew or maintain data in the memory. The non-volatile memory 106 is typically a magnetic hard disk drive or a magneto-optical drive or an optical drive or a DVD RAM or other type of memory system that still maintains data after power is removed from the system. In general, the non-volatile memory will also be a random access memory, but this is not required. Although FIG. 17 shows that the non-volatile memory system is directly coupled to a native device of the remainder of the components of the data processing system, it will be appreciated that the present invention may utilize a non-volatile memory remote from the system, such as a A network storage device coupled to the data processing system via a network interface, such as a data modem or an Ethernet interface. Busbar 102 may include one or more busbars connected to each other through various bridges, controllers, and/or adapters, as is well known in the art. In a specific embodiment, the I/O controller 109 includes a USB (Universal Serial Bus) adapter. The USB peripheral device and/or an IEEE-1394 bus adapter are used to control the IEEE-1394 peripheral device.

It will be apparent from this description that the aspects of the invention may be at least partially embodied in a software. That is, the techniques can be implemented in a computer system or other data processing system in response to a processor (such as a microprocessor) executing in a memory (such as ROM 107, non-volatile RAM 105). The instruction sequence of the non-volatile memory 106, the cache memory 104, or a remote storage device. In various embodiments, software instructions can be combined to implement hardwired circuits to implement the present invention. Thus, the techniques are not limited to any particular combination of hardware circuitry and software, and are not limited to any particular source of such instructions for execution by the data processing system. In addition, throughout this specification, various functions and operating systems are described as being implemented or caused by a software code to simplify the description. However, those skilled in the art will recognize that such expression means that the functions are generated from a processor (such as microprocessor 103) executing the code.

A machine readable medium can be used to store software and materials that, when executed by a data processing system, cause the system to perform the various methods of the present invention. The executable software and materials can be stored in a variety of locations including, for example, exemplary ROM 107, non-volatile RAM 105, non-volatile memory 106, and/or cache memory 104. Portions of the software and/or data may be stored in any of the storage devices.

Thus, a machine readable medium includes any mechanism that can be a machine (eg, a computer, a network device, a personal digital assistant, a manufacturing tool, any device having a set of one or more processors, etc.) The form of access provides (ie, stores and/or transmits) information. For example, a machine readable media package Recordable/non-recordable media (eg, read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory devices, etc.) and electrical, optical, acoustic Or other forms of propagation signals (such as carrier waves, infrared signals, digital signals).

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It is apparent that various modifications may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative and not limiting.

101‧‧‧ computer system

102‧‧‧ busbar

103‧‧‧Microprocessor

105‧‧‧Volatile RAM

106‧‧‧Non-volatile memory

107‧‧‧ROM

108‧‧‧Display device

109‧‧‧Input/Output Controller

110‧‧‧Input/Output Devices

The invention is illustrated by way of example and not limitation,

Figure 1 shows a prior art method for designing an integrated circuit.

Figure 2 shows one prior art exemplary method of entity synthesis.

3 shows a flow chart of one method for designing an integrated circuit in accordance with an embodiment of the present invention.

4 shows a flow chart of another method for designing an integrated circuit in accordance with an embodiment of the present invention.

5A and 5B show details of a method for designing an integrated circuit in accordance with a particular embodiment of the present invention.

6 shows a flow chart of one method for designing an integrated circuit in accordance with an embodiment of the present invention.

Figure 7 shows an exemplary estimate of one of the shapes and resources.

Figure 8 shows an exemplary mapping for one of the resource types.

9A and 9B are exemplary mappings of a memory resource.

10A and 10B are exemplary resource sharing implementations.

Figure 11 shows an example of an adder tree decomposition.

Figure 12 shows an example of a brake tree decomposition.

Figures 13A and 13B show an example of a slice optimization.

Figure 14 shows an example of a replication optimization.

Figure 15 shows an example of a one-way agricultural expansion.

16A and 16B show examples of mux/pmux folding and timing driven decomposition.

Figure 17 shows an example of a block diagram of one of the data processing systems that can be used with the present invention.

(no component symbol description)

Claims (70)

A method of designing an integrated circuit, the method comprising: dividing a wafer resource into a plurality of segments; calculating a rank of the segments based on a quality metric; and having the lowest level by a placement transformation The section was removed from consideration. The method of claim 1, wherein the wafer resource exceeds a requirement of the integrated circuit. The method of claim 1, wherein the segments are removed such that the wafer resource satisfies the circuit requirements. The method of claim 1, further comprising the step of repeating the rating and removing until a predetermined criterion is achieved. The method of claim 1, wherein some sections of the removed sections are reconsidered in a next repeated removal procedure. The method of claim 1, wherein some of the sections of the removed section are permanently removed and are not reconsidered in a next repeated removal procedure. The method of claim 1, wherein the quality metric comprises a distance from use of the resource. The method of claim 1, wherein calculating the level comprises calculating a convolution of one of the instances of the resource with a Green's function. A machine readable medium comprising a plurality of executable instructions that, when executed on a digital processing system, cause the digital processing system to perform a method of designing an integrated circuit (IC), the method comprising: placing a wafer The resources are divided into a plurality of sections; The ranks of the segments are calculated based on a quality metric; and the segments having the lowest rank are removed from the consideration by a placement transformation. The medium of claim 9, wherein the wafer resource exceeds a requirement of the integrated circuit. The medium of claim 9, wherein the segments are removed such that the wafer resource satisfies the circuit requirements. As with the media of claim 9, it further includes the steps of repeating the rating and removing until a predetermined criterion is achieved. The media of claim 9, wherein some segments of the removed segments are reconsidered in a next repeated removal procedure. The media of claim 9, wherein some of the sections of the removed section are permanently removed and are not reconsidered in a next repeated removal procedure. The media of claim 9, wherein the quality metric comprises a distance from the use of the resource. The media of claim 9, wherein calculating the level comprises convolving a density of one of the instances in the resource with a Green's function. A method for calculating a total force on an item in an item arrangement for an integrated circuit on a wafer, comprising: calculating a force between the item and an element, the element is Another example of an integrated circuit and at least one of a wafer resource on the wafer, the force being a function of a distance between the instance and the component; the term being based on the distance to the example One adjacent area is divided into a plurality of adjacent areas; Calculating a plurality of adjacent forces on the item as a function of the force between the item and each of the adjacent regions; and calculating by weighting one of the adjacent forces A total force on the item. The method of claim 17, wherein the adjacent region for an item is divided into three adjacent regions, that is, a partial adjacent region, a medium adjacent region, and a long-range adjacent region. The method of claim 18, wherein a partially adjacent region covers an area having a radius of about five times one of the average instance regions. The method of claim 18, wherein a medium adjacent region covers an area having a radius of about 10 times one of the average case regions. The method of claim 18, wherein a long-range adjacent area covers the total area. The method of claim 17, wherein the adjacent regions comprise a short range adjacent region and wherein a weight for a short range neighboring force is proportional to an item density in a short range adjacent region. The method of claim 17, wherein the adjacent regions comprise a long range adjacent region and wherein the weight for a long range adjacent force is inversely proportional to the density of the instances in a short range adjacent region. The method of claim 17, wherein the adjacent regions are further determined by legalizing the area required to surround the use of an item. The method of claim 17, wherein the component is another item within the integrated circuit and wherein the force between the instance and the other instance is a repulsive force. The method of claim 17, wherein the one of the plurality of adjacent forces is adjacent to the force system Calculated by weighting one of the resource type forces, each resource type force is included in the case and the other part of the other item having the same data type in the integrated circuit and in the example Such forces between the wafer resources of the same resource type. The method of claim 26, wherein the another instance item has a prototype item of a resource type, and wherein the force between the item item and the other item item comprises a resource type force component. The method of claim 26, wherein the another instance item has a non-prototype item of a plurality of resource types, and wherein the force between the item item and the other item item comprises a plurality of resource type force components. The method of claim 26, wherein the weight of the resource type is a function of one of the dispersions of the resource type. The method of claim 17, wherein the component is a wafer resource of the same type as the instance and wherein the force between the instance and the wafer resource is attractive. A machine readable medium comprising a plurality of executable instructions which, when executed on a digital processing system, cause the digital processing system to perform an integrated circuit on a wafer for calculation in an example of placement A method of total force, the method comprising: calculating a force between the instance and another instance in the integrated circuit, the force being a function of a distance between the two instances; Dividing the adjacent region of the instance into a plurality of adjacent regions based on the distance to the example; by adding the forces between the instance and the elements of the adjacent regions To calculate a plurality of adjacent forces on the item; and to calculate a total force on the item by weighting one of the adjacent forces. The medium of claim 31, wherein the adjacent area for an item is divided into three adjacent areas, that is, a partial adjacent area, a medium adjacent area, and a long-range adjacent area. In the medium of claim 32, wherein a portion of the local area covers an area having a radius of about five times one of the average item areas. As in the medium of claim 32, a mediumly adjacent region covers an area having a radius of about 10 times one of the average case regions. As in the medium of claim 32, a long-range adjacent area covers the total area. The medium of claim 31, wherein the adjacent regions comprise a short range adjacent region and wherein the weight for a short range neighboring force is proportional to the density of the instances in a short range adjacent region. The medium of claim 31, wherein the adjacent regions comprise a long range adjacent region and wherein the weight for a long range adjacent force is inversely proportional to the density of the instances in a short range adjacent region. The media of claim 31, wherein the adjacent regions are further determined by legalizing the area required to surround the use of an item. The medium of claim 31, wherein the component is another instance within the integrated circuit and wherein the force between the instance and the other instance is a repulsive force. The media of claim 31, wherein one of the plurality of adjacent forces is calculated by weighting one of resource type forces, each resource type force The force is included between the item and the portion of the other item having the same data type in the integrated circuit and the force between the item and the wafer resource of the same resource type. The media of claim 40, wherein the other instance has a prototype instance of a resource type, and wherein the force between the instance and the other instance comprises a resource type force component. The medium of claim 40, wherein the another instance has a non-prototype item of a plurality of resource types, and wherein the force between the item and the other item comprises a plurality of resource type force components. The medium of claim 40, wherein the weight of the resource type is a function of one of the dispersions of the resource type. The medium of claim 31, wherein the component is a wafer resource of the same type as the instance and wherein the force between the instance and the wafer resource is attractive. A method for calculating a total force on a non-prototype item in an item placement in an item placement, the non-prototype item consuming more than one type of resource, the method comprising: assigning the non-prototype item Within each layer to a different resource type layer, the resource type layer is represented by one of the resource types; as a function of the force between the instance item and other instances and resources in the resource type layer The resource type layer calculates a resource type layer force; and calculates a total force on the item by weighting one of the resource type layer forces. The method of claim 45, wherein the weight is a uniform weight. The method of claim 45, wherein the weight is a function of one of the dispersions of resources of the layer. A machine readable medium comprising a plurality of executable instructions that, when executed on a digital processing system, cause the digital processing system to perform a calculation on a non-prototype item in an item placement for an integrated circuit In a method of total force, the non-prototype item consumes more than one type of resource, and the method includes: assigning each type of the non-prototype item to a layer of another resource type, the resource type layer is the resource type a representation; calculating a resource type layer force for the resource type layer as a function of the force between the instance item and other instances and resources within the resource type layer; and by using the resource type layer One of the weighted sums is used to calculate a total force on the item. The media of claim 48, wherein the weight is a uniform weight. The medium of claim 48, wherein the weight is a function of one of the dispersions of resources of the layer. A method for calculating a total force on an item in an item placement in an item arrangement, the method comprising: determining a plurality of resource types for one part of the item; placing the item in each resource type layer In the portion, the resource type layer is represented by one of the resource types; as a function of the forces from the resource type layers, A total force on this item. The method of claim 51, wherein the total force is a weighted sum of the forces from the resource type layers. The method of claim 51, wherein the force from the resource type layers is included in the instance and the other items in the resource type layer. The method of claim 51, wherein the force from the resource type layers is included in the instance and the resources between the resources in the resource type layer. The method of claim 51, wherein the weight is a uniform weight. The method of claim 51, wherein the weight is a function of one of the dispersions of resources of the layer. The method of claim 51, wherein the total force is a force having a minimum amount of the forces from the resource type layers. A machine readable medium comprising a plurality of executable instructions that, when executed on a digital processing system, cause the digital processing system to perform a calculation of one of the items in an item placement for an integrated circuit a method for force, the method comprising: determining a plurality of resource types for one of the items; placing the portion of the item in each resource type layer, the resource type layer being represented by one of the resource types; One of these forces of the resource type layer calculates a total force on the instance. The medium of claim 58, wherein the total force is from the resource type layer One of these forces is weighted. The medium of claim 58, wherein the force from the resource type layers is included in the instance and the other items in the resource type layer. The medium of claim 58, wherein the force from the resource type layers is included in the instance and the resources between the resources in the resource type layer. The media of claim 58, wherein the weight is a uniform weight. The medium of claim 58, wherein the weight is a function of one of the dispersions of resources of the layer. The medium of claim 58, wherein the total force is a force having a minimum amount of the forces from the resource type layers. A method for calculating a total force on an item in an item placement in an item arrangement, the method comprising: determining a single resource part of the item that can be assigned only to a resource type layer, the resource type layer Representing one of the resource types; placing the single resource portion of the instance in the corresponding resource type layer; calculating a total force on the instance as a function of the force from the corresponding resource type layer Determining a multi-resource portion of the instance that can be assigned to a plurality of potential resource type layers; calculating a splitting metric that is caused by placing a plurality of resource portions of the instance within each potential resource type layer; The multi-resource portion of the instance is placed within a potential resource type layer that exhibits the least splitting metric. The method of claim 65, wherein the splitting metric is represented by a higher force on an item. The method of claim 65, wherein the force on the one of the items is included in the instance and the other items in the same resource type layer and the same in the same resource type layer Such attraction between these resources. A machine readable medium comprising a plurality of executable instructions that, when executed on a digital processing system, cause the digital processing system to perform a calculation of one of the items in an item placement for an integrated circuit a method for determining a single resource portion of the instance that can be assigned only to a resource type layer, the resource type layer being represented by one of the resource types; placing the instance in the corresponding resource type layer The single resource portion; a total force on the instance as a function of the force from the corresponding resource type layer; determining one of the plurality of resources of the instance that can be assigned to the plurality of potential resource type layers Part of calculating a splitting metric caused by placing a plurality of resource portions of the instance within each potential resource type layer; placing the multi-resource portion of the instance within a potential resource type layer that exhibits a minimum splitting metric. The media of claim 68, wherein the splitting metric is represented by a higher force on an item. The medium of claim 68, wherein the force on an item is included in the instance and the other items in the same resource type layer and the same in the same resource type layer Such attraction between these resources.