TWI473420B - Structure of output stage - Google Patents

Description

Output stage structure

The present invention relates to the structure of an output stage, and more particularly to a structure of an output stage that can improve drive capability.

In recent years, operational amplifiers have been widely used in a wide variety of applications because of their high input impedance, high loop gain, low output impedance, low common-mode gain, and high gain bandwidth. On the circuit, for example, an amplifier circuit for processing large signal amplification, or a driving circuit for driving a capacitive load. In addition, in some high current applications (such as those used in drive circuits that drive display panels), op amps must have high drive capability (ie, output high current).

In a high-drive op amplifier, the layout of the output stage of the op amp determines the magnitude of the current output from the op amp, so the importance of the output stage of the op amp is second only to the circuit design, and the operation The design of the amplifier's output stage requires special attention. Moreover, if the electrode arrangement of the current terminal, the ground terminal, and the output terminal is not good, electron migration, burn-out, or equivalent resistance between the electrodes may occur. Reduce the maximum current that the output stage can deliver in an instant. When the operational amplifier is packaged as a chip and verified, the output of the operational amplifier is short-circuited to the power supply or ground. In this case, over current protection (OCP) and over temperature protection (OTP) are available. The protection op amp is working properly, but it is still possible to pass verification at some point.

The invention provides a structure of an output stage, which can improve the driving capability of the output stage (ie, the current outputted by the output stage).

The present invention provides a structure of an output stage, including a first electrode, a second electrode, a third electrode, a plurality of first auxiliary electrodes, a plurality of second auxiliary electrodes, a plurality of third auxiliary electrodes, and a plurality of fourth auxiliary electrodes, a plurality of first transistors and a plurality of second transistors. The first auxiliary electrodes are disposed between the first electrode and the second electrode and are connected to the first electrode, wherein a width of each of the first auxiliary electrodes is inversely proportional to a distance from the first electrode. The second auxiliary electrodes are disposed between the first electrode and the second electrode, and are connected to the second electrode, wherein a width of each of the second auxiliary electrodes is inversely proportional to a distance from the second electrode. The third auxiliary electrodes are disposed between the second electrode and the third electrode, and are connected to the second electrode, wherein a width of each of the third auxiliary electrodes is inversely proportional to a distance from the second electrode. The fourth auxiliary electrodes are disposed between the second electrode and the third electrode, and are connected to the third electrode, wherein the width of each of the fourth auxiliary electrodes is inversely proportional to the distance from the third electrode. The first auxiliary electrodes and the second auxiliary electrodes are electrically connected to each other through the first transistors that are turned on. The third auxiliary electrodes and the fourth auxiliary electrodes are electrically connected to each other through the second transistors that are turned on.

In an embodiment of the invention, the shapes of the first auxiliary electrode, the second auxiliary electrode, the third auxiliary electrode, and the fourth auxiliary electrode are respectively a trapezoid.

In an embodiment of the invention, the first electrode, the second electrode, and the third electrode are sequentially disposed between the power terminal and the ground.

In an embodiment of the invention, the first electrode is electrically connected to the power terminal, the second electrode is electrically connected to an output terminal, and the third electrode is electrically connected to the ground terminal.

In an embodiment of the invention, each of the first auxiliary electrodes is electrically connected to one of the adjacent two second auxiliary electrodes through at least one of the first transistors that are turned on.

In an embodiment of the invention, each of the first auxiliary electrodes is electrically connected to the adjacent two second auxiliary electrodes through at least one of the first transistors that are turned on.

In an embodiment of the invention, each of the second auxiliary electrodes is electrically connected to the adjacent two first auxiliary electrodes through at least one of the first transistors that are turned on.

In an embodiment of the invention, each of the third auxiliary electrodes is electrically connected to one of the adjacent two fourth auxiliary electrodes through at least one of the second transistors that are turned on.

In an embodiment of the invention, each of the third auxiliary electrodes is electrically connected to the adjacent two fourth auxiliary electrodes through at least one of the second transistors that are turned on.

In an embodiment of the invention, each of the fourth auxiliary electrodes is electrically connected to the adjacent two third auxiliary electrodes through at least one of the second transistors that are turned on.

In an embodiment of the invention, the first transistors are respectively PMOS transistors, and the second transistors are respectively NMOS transistors.

Based on the above, in the output stage structure of the embodiment of the present invention, the first auxiliary electrode of the output stage is connected to the first electrode, and the width of the first auxiliary electrode is inversely proportional to the distance from the first electrode; the second auxiliary electrode of the output stage is connected. a second electrode, and a width of the second auxiliary electrode is inversely proportional to a distance from the second electrode; a third auxiliary electrode is connected to the second electrode, and a width of the third auxiliary electrode is inversely proportional to a distance from the second electrode; The electrode is connected to the third electrode, and the width of the fourth auxiliary electrode is inversely proportional to its distance from the third electrode. Thereby, the magnitude of the current flowing through the first auxiliary electrode, the second auxiliary electrode, the third auxiliary electrode, and the fourth auxiliary electrode can be increased.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1A is a schematic structural diagram of an output stage according to an embodiment of the invention. Referring to FIG. 1A, in the embodiment, the output stage 100 includes a first electrode 110, a second electrode 120, a third electrode 130, a plurality of first auxiliary electrodes 140, a plurality of second auxiliary electrodes 150, and a plurality of third portions. The auxiliary electrode 160, the plurality of fourth auxiliary electrodes 170, the plurality of first transistors T1, and the plurality of second transistors T2. The first electrode 110, the second electrode 120, and the third electrode 130 are sequentially disposed in parallel between the power terminal TP and the ground terminal TG, and the first electrode 110 is electrically connected to the power terminal TP, and the second electrode 120 is electrically connected. The output terminal TO is connected, and the third electrode 130 is electrically connected to the ground terminal TG. The power terminal TP, the output terminal TO, and the ground terminal TG may be a power terminal, an output terminal, and a ground terminal of the chip. In addition, in this embodiment, the first transistor T1 may be a PMOS transistor, and the second transistor T2 may be an NMOS transistor, but the invention is not limited thereto.

The first auxiliary electrode 140 and the second auxiliary electrode 150 are disposed between the first electrode 110 and the second electrode 120, and the first auxiliary electrode 140 is connected to the first electrode 110, and the second auxiliary electrode 150 is connected to the second electrode 120. An auxiliary electrode 140 is not directly connected to the second auxiliary electrode 150. The width W1 of each of the first auxiliary electrodes 140 is inversely proportional to the distance from the first electrode 110, that is, the closer to the first electrode 110, the wider the width W1 of the first auxiliary electrode 140, and the further away from the first electrode 110 The width W1 of the first auxiliary electrode 140 is narrower; the width W2 of each second auxiliary electrode 150 is inversely proportional to the distance from the second electrode 120, that is, the closer to the width W2 of the second auxiliary electrode 150 from the second electrode 120 The width is wider from the second electrode 120, and the width W2 of the second auxiliary electrode 150 is narrower. In the present embodiment, the shapes of the first auxiliary electrode 140 and the second auxiliary electrode 150 are represented by trapezoids, but other embodiments of the present invention are not limited thereto.

The third auxiliary electrode 160 and the fourth auxiliary electrode 170 are disposed between the second electrode 120 and the third electrode 130, and the third auxiliary electrode 160 is connected to the second electrode 120, and the fourth auxiliary electrode 170 is connected to the third electrode 130. The three auxiliary electrodes 160 are not directly connected to the fourth auxiliary electrode 170. The width W3 of each of the third auxiliary electrodes 160 is inversely proportional to the distance from the second electrode 120, that is, the closer to the second electrode 120, the wider the width W3 of the third auxiliary electrode 160, and the further away from the second electrode 120 The width W3 of the third auxiliary electrode 160 is narrower. Moreover, the width W4 of each fourth auxiliary electrode 170 is inversely proportional to the distance from the third electrode 130, that is, the closer to the third electrode 130, the wider the width W4 of the fourth auxiliary electrode 170, and the further away from the third electrode 130 The width W4 of the fourth auxiliary electrode 170 is narrower. In the present embodiment, the shapes of the third auxiliary electrode 160 and the fourth auxiliary electrode 170 are represented by trapezoids, but other embodiments of the present invention are not limited thereto.

In this embodiment, the first transistors T1 are shown in two columns, and the first auxiliary electrodes 140 and the second auxiliary 150 electrodes are electrically connected to each other through the first transistors T1 that are turned on, that is, Each of the first auxiliary electrodes 140 is electrically connected to the second auxiliary electrode 150 corresponding to one adjacent side through the two conductive first transistors T1, and is electrically connected to the other through the other two conductive first transistors T1. The second auxiliary electrode 150 corresponding to the adjacent side. In other embodiments, the first transistors T1 can be illustrated as one or more columns, depending on the design of the circuit structure. Moreover, when the first transistors T1 are in a row, each of the first auxiliary electrodes 140 is electrically connected to the second auxiliary electrode 150 corresponding to an adjacent side through one of the first transistors T1 that is turned on, and is turned on by another one. The first transistor T1 is electrically connected to the second auxiliary electrode 150 corresponding to the other adjacent side.

In this embodiment, the second transistors T3 are also shown in two rows, and the third auxiliary electrodes 160 and the fourth auxiliary 170 electrodes are electrically connected to each other through the second transistors T2 that are turned on. That is, each of the third auxiliary electrodes 160 is electrically connected to the fourth auxiliary electrode 170 corresponding to the left adjacent side through the two conductive second transistors T3, and is electrically connected to the right through the other two conductive second transistors T2. The fourth auxiliary electrode 170 corresponding to the adjacent side. In other embodiments, the second transistor T2 can be illustrated as one or more columns, depending on the design of the circuit structure. Moreover, when the second transistor T2 is in a row, each of the third auxiliary electrodes 160 is electrically connected to the fourth auxiliary electrode 170 corresponding to an adjacent side through a second transistor T2 that is turned on, and passes through another conductive portion. The two transistors T2 are electrically connected to the fourth auxiliary electrode 170 corresponding to the other adjacent side.

According to the above, when the first transistor T1 is turned on, the first transistor T1 transfers the current flowing into the first auxiliary electrode 140 to the second auxiliary electrode 150, and the current density of the first auxiliary electrode 140 is close to the first. The electrode 110 is higher in place and gradually decreases away from the first electrode 110. Therefore, the closer the width W1 is, the closer the width W1 is, and the narrower the width W1 is, the farther away from the first electrode 110 is, the larger the equivalent resistance of the first auxiliary electrode 140 is avoided, and the first auxiliary is improved. The maximum current of the electrode 140. Moreover, the current density of the second auxiliary electrode 150 is higher near the second electrode 120 and gradually decreases away from the second electrode 120. Therefore, the width W2 is wider as the second electrode 120 is closer, and the width W2 is narrower as the distance from the second electrode 120 is farther, so as to avoid excessive resistance of the second auxiliary electrode 150 and increase the flow through the second auxiliary. The maximum current of the electrode 150.

In this embodiment, similarly, the width W3 is wider as the second electrode 120 is closer, the width W3 is narrower as the distance from the second electrode 120 is larger, and the width W4 is closer as the third electrode 130 is closer. The width is wider, and the width W4 is narrower as the distance from the second electrode 120 is farther. The design principle is similar to that of the first auxiliary electrode 140 and the second auxiliary electrode 150, and will not be described herein. Thereby, the equivalent resistance of the third auxiliary electrode 160 and the fourth auxiliary electrode 170 can be prevented from being excessively increased, and the maximum current flowing through the third auxiliary electrode 160 and the fourth auxiliary electrode 170 can be increased.

Further, in this embodiment, each of the first transistors T1 includes a source S1, an S2, a drain D1, a D2, a channel layer P1 to P3, and a gate G1, wherein the source S1, S2, and the drain D1 The D2 and the channel layers P1 to P3 are exemplarily shown as strips, but other embodiments of the present invention are not limited thereto. The channel layers P1 to P3 are respectively disposed between the source electrodes S1 and S2 and the drain electrodes D1 and D2, and it is assumed here that the source electrodes S1 and S2 are electrically connected to the corresponding first auxiliary electrode 140, and the drain electrodes D1 and D2 are electrically connected. Corresponding second auxiliary electrode 150. When the channel layers P1 to P3 are affected by the voltage of the gate G1 to form a channel, the drain D1 is electrically connected to the source electrodes S1 and S2 through the channel layers P1 and P2, and the drain D2 is electrically connected to the source through the channel layer P3. S2.

Moreover, in this embodiment, each of the second transistors T2 includes a source S3, S4, a drain D3, D4, a channel layer P4~P6, and a gate G2, wherein the source S3, S4, the drain D3, D4 The channel layers P4 to P6 are exemplarily shown as strips, but other embodiments of the present invention are not limited thereto. The channel layers P4 to P6 are respectively disposed between the source electrodes S3 and S4 and the drain electrodes D3 and D4, and it is assumed here that the source electrodes S3 and S4 are electrically connected to the corresponding fourth auxiliary electrode 170, and the drain electrodes D3 and D4 are electrically connected. Corresponding third auxiliary electrode 160. When the channel layers P4~P6 are formed by the voltage of the gate G2, the source S3 is electrically connected to the drain electrodes D3 and D4 through the channel layers P4 and P5, and the source S4 is electrically connected to the drain through the channel layer P6. D4.

Fig. 1B is an enlarged schematic view showing the structure of the portion A of Fig. 1A. Referring to FIG. 1A and FIG. 1B, in the present embodiment, the description of the "before" is shown above in the figure, and the "behind" is shown below the figure, but The embodiments of the invention are not limited thereto. Before the source S1 of the first transistor T1_1, the current flowing through the first auxiliary electrode 140 is approximately I ₁ + I ₂ + I ₃ + I ₄ . Wherein, the current I ₁ is the current flowing into the source S2 of the first transistor T1_2, I ₂ is the current flowing into the source S1 of the first transistor T1_2, and I ₃ is the source flowing into the first transistor T1_1. The current of S2, I ₄ is the current flowing into the source S1 of the first transistor T1_1.

Between the sources S1 and S2 of the first transistor T1_1, the current flowing through the first auxiliary electrode 140 is approximately I ₁ + I ₂ + I ₃ . Between the source S2 of the first transistor T1_1 and the source S1 of the first transistor T1_2, the current flowing through the first auxiliary electrode 140 is approximately I ₁ + I ₂ . The source electrode of the first transistor T1_2 between S2 and S1, the current flowing through the first auxiliary electrode 140 is about I _1. After the source S2 of the first transistor T1_2, the current flowing through the first auxiliary electrode 140 is about zero. Therefore, the closer to the first electrode 110, the higher the current density of the first auxiliary electrode 140, and the further away from the first electrode 110, the lower the current density of the first auxiliary electrode 140.

Before the drain D1 of the first transistor T1_1, the current flowing through the second auxiliary electrode 150 is about zero. Between the drains D1 and D2 of the first transistor T1_1, the current flowing through the second auxiliary electrode 150 is about I ₈ , wherein the current I ₈ is the current flowing from the drain D1 of the second transistor T1_1. Between the drain D2 of the first transistor T1_1 and the drain D1 of the first transistor T1_2, the current flowing through the second auxiliary electrode 150 is about I ₇ + I ₈ , wherein the current I ₇ is the second transistor T1_1 The current flowing out of the bungee D2.

Between the drains D1 and D2 of the first transistor T1_2, the current flowing through the second auxiliary electrode 150 is approximately I ₆ + I ₇ + I ₈ , wherein the current I ₆ is the drain of the drain D1 of the second transistor T1_2 Current. After the first electrode of the transistor drain T1_2 D2, a current flowing through the second auxiliary electrode 150 is about _{I 5 + I 6 + I 7} + I 8, I ₅ wherein the current drain of a second electrical pole crystal T1_2 outflow D2 Current. Therefore, the closer to the second electrode 120, the higher the current density of the second auxiliary electrode 150, and the further away from the second electrode 120, the lower the current density of the second auxiliary electrode 150.

Before the drain D3 of the second transistor T2_1, the current flowing through the third auxiliary electrode 160 is approximately I ₉ + I ₁₀ + I ₁₁ + I ₁₂ . Wherein, the current I ₉ is the current flowing into the drain D3 of the second transistor T2_1, I ₁₀ is the current flowing into the drain D4 of the second transistor T2_1, and I ₁₁ is the drain flowing into the second transistor T2_2. The current of D3, I ₁₂ is the current flowing into the drain D4 of the second transistor T2_2. Between the drains D3 and D4 of the second transistor T2_1, the current flowing through the third auxiliary electrode 160 is approximately I ₁₀ + I ₁₁ + I ₁₂ .

Between the drain D4 of the second transistor T2_1 and the drain D3 of the second transistor T2_2, the current flowing through the third auxiliary electrode 160 is approximately I ₁₁ + I ₁₂ . The drain electrode of the second transistor T2_2 between D3 and D4, the current flowing through the third auxiliary electrode 160 is about I _12. After the drain D4 of the second transistor T2_2, the current flowing through the third auxiliary electrode 160 is about zero. Therefore, the closer to the second electrode 120, the higher the current density of the third auxiliary electrode 160, and the further away from the second electrode 120, the lower the current density of the third auxiliary electrode 160.

Before the source S3 of the second transistor T2_1, the current flowing through the fourth auxiliary electrode 170 is about zero. In between the pole S3 and S4 T2_1 of a second transistor source, the current flowing through the fourth auxiliary electrode 170 is about I _13, where I ₁₃ is the current source of the second current electrode of transistor T2_1 S3 flowing. Between the source S4 of the second transistor T2_1 and the source S3 of the second transistor T2_2, the current flowing through the fourth auxiliary electrode 170 is approximately I ₁₃ +I ₁₄ , wherein the current I ₁₄ is the second transistor T2_1 The current flowing from the source S4.

Between the sources S3 and S4 of the second transistor T2_2, the current flowing through the fourth auxiliary electrode 170 is approximately I ₁₃ + I ₁₄ + I ₁₅ , wherein the current I ₁₅ flows out of the source S3 of the second transistor T2_2 Current. After the source S4 of the second transistor T2_2, the current flowing through the fourth auxiliary electrode 170 is approximately I ₁₃ +I ₁₄ +I ₁₅ +I ₁₆ , wherein the current I ₁₆ flows out of the source S4 of the second transistor T2_2 Current. Therefore, the closer to the third electrode 130, the higher the current density of the fourth auxiliary electrode 170, and the further away from the third electrode 130, the lower the current density of the fourth auxiliary electrode 170.

2 is a schematic structural view of an output stage according to another embodiment of the present invention. Referring to FIG. 1A and FIG. 2, the structure of FIG. 2 is similar to the structure of FIG. 1A except that the first transistor T3 and the second transistor T4, wherein the first transistor T3 operates similarly to the first transistor T1, and the second The operation of the transistor T4 is similar to that of the second transistor T2. In the present embodiment, the first transistor T3 of the output stage 200 spans the corresponding first auxiliary electrode 140, and the two second auxiliary electrodes 150 adjacent to the corresponding first auxiliary electrode 140 partially overlap. At this time, each of the first auxiliary electrodes 140 is electrically connected to the adjacent two second auxiliary electrodes 150 through the two first transistors T3 that are turned on.

Also, the second transistor T4 spans the corresponding third auxiliary electrode 160, and the two fourth auxiliary electrodes 170 adjacent to the corresponding third auxiliary electrode 160 partially overlap. Therefore, each of the third auxiliary electrodes 160 is electrically connected to the adjacent two fourth auxiliary electrodes 170 through the two second transistors T4 that are turned on. Thereby, the current of the first auxiliary electrode 140 can flow to the adjacent two second auxiliary electrodes 150 through the turned-on first transistor T3, and the current of the third auxiliary electrode 160 can flow through the second transistor T4 that is turned on. The adjacent two fourth auxiliary electrodes 170 can thus increase the flow rate of the current.

In addition, in other embodiments, the first transistor T3 may span the corresponding second auxiliary electrode 150, and the two first auxiliary electrodes 140 adjacent to the corresponding second auxiliary electrode 150 partially overlap, so as to cause each second The auxiliary electrode 150 is electrically connected to the adjacent two first auxiliary electrodes 140 through the two first transistors T3 that are turned on. And, the second transistor T4 may overlap the corresponding fourth auxiliary electrode 170, and the two third auxiliary electrodes 160 adjacent to the corresponding fourth auxiliary electrode 170 partially overlap, so that each of the fourth auxiliary electrodes 170 is permeable. The two second transistors T4 are electrically connected to the adjacent two third auxiliary electrodes 160.

3 is a system block diagram of an operational amplifier in accordance with an embodiment of the present invention. Referring to FIG. 3, in the present embodiment, the operational amplifier 300 includes a pre-amplification circuit 310 and an output stage 320, wherein the output stage 320 can be implemented using the output stage 100 or 200 described above. The preamplifier circuit 310 receives the input voltage Vin+ at the positive terminal and the input voltage Vin- at the negative terminal, and generates control signals SC1 and SC2 accordingly. The control signal SC1 is here, for example, used to control the first transistor (such as T1 or T3) in the output stage 320 to be turned on or off, and the control signal SC2 is used here, for example, to control the second transistor in the output stage 320 ( If T2 or T4) is turned on or off, thereby controlling the output stage 320 to output the desired output voltage Vo.

In addition, the output stage 100 or 200 described in the above embodiments can also be applied to a pulse width modulator and a power switch with high driving capability, which is different from the above operational amplifier in that the front stage circuits of the output stages 100 and 200 are pulsed. The wide modulation control circuit or the switch control circuit, the pulse width modulation control circuit and the switch control circuit also generate control signals SC1 and SC2 to control the output stage 100 or 200 to output the desired output voltage Vo.

In summary, the output stage of the embodiment of the present invention sets the width variation of the auxiliary electrode according to the current density distribution of the auxiliary electrode, thereby maximizing the current flowing through the auxiliary electrode. Also, the transistor can overlap the corresponding auxiliary electrode and partially overlap the adjacent two auxiliary electrodes, thereby increasing the flow rate of the current.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 320‧‧‧ output stage

110‧‧‧First electrode

120‧‧‧second electrode

130‧‧‧ third electrode

140‧‧‧First auxiliary electrode

150‧‧‧Second auxiliary electrode

160‧‧‧ third auxiliary electrode

170‧‧‧4th auxiliary electrode

300‧‧‧Operational Amplifier

310‧‧‧Preamplifier circuit

D1~D4‧‧‧Bungee

G1, G2‧‧‧ gate

I ₁ ~I ₁₆ ‧‧‧ Current

P1~P6‧‧‧ channel layer

S1~S4‧‧‧ source

SC1, SC2‧‧‧ control signals

T1, T1_1, T1_2, T3‧‧‧ first transistor

T2, T2_1, T2_2, T4‧‧‧ second transistor

TG‧‧‧ grounding terminal

TO‧‧‧ output

TP‧‧‧ power terminal

Vin+, Vin-‧‧‧ input voltage

W1~W4‧‧‧Width

FIG. 1A is a schematic structural diagram of an output stage according to an embodiment of the invention.

Fig. 1B is an enlarged schematic view showing the structure of the portion A of Fig. 1A.

2 is a schematic structural view of an output stage according to another embodiment of the present invention.

3 is a system block diagram of an operational amplifier in accordance with an embodiment of the present invention.

100‧‧‧Output

110‧‧‧First electrode

120‧‧‧second electrode

130‧‧‧ third electrode

140‧‧‧First auxiliary electrode

150‧‧‧Second auxiliary electrode

160. . . Third auxiliary electrode

170. . . Fourth auxiliary electrode

D1~D4. . . Bungee

G1, G2. . . Gate

P1~P6. . . Channel layer

S1~S4. . . Source

T1. . . First transistor

T2. . . Second transistor

TG. . . Ground terminal

TO. . . Output

TP. . . Power terminal

W1~W4. . . width

Claims (11)

An output stage structure includes: a first electrode; a second electrode; a third electrode; a plurality of first auxiliary electrodes disposed between the first electrode and the second electrode, and connected to the first electrode, The width of each of the first auxiliary electrodes is inversely proportional to the distance from the first electrode; the plurality of second auxiliary electrodes are disposed between the first electrode and the second electrode, and are connected to the second electrode, The width of each of the second auxiliary electrodes is inversely proportional to the distance from the second electrode; a plurality of third auxiliary electrodes are disposed between the second electrode and the third electrode, and are connected to the second electrode, The width of each of the third auxiliary electrodes is inversely proportional to the distance from the second electrode; a plurality of fourth auxiliary electrodes are disposed between the second electrode and the third electrode, and are connected to the third electrode, wherein The width of each of the fourth auxiliary electrodes is inversely proportional to the distance from the third electrode; the plurality of first transistors, the first auxiliary electrodes and the second auxiliary electrodes respectively transmit the first electricity that is turned on Crystal and electrically connected to each other ; And a plurality of second transistors, the plurality of third auxiliary electrode and the plurality of fourth auxiliary electrode are respectively transmitted through the plurality of second transistor is turned on and electrically connected to each other. The output stage structure of claim 1, wherein the first auxiliary electrode, the second auxiliary electrode, and the third auxiliary electrode And the shapes of the fourth auxiliary electrodes are respectively a trapezoid. The output stage structure of claim 1, wherein the first electrode, the second electrode and the third electrode are sequentially disposed between a power terminal and a ground terminal. The output stage structure of claim 3, wherein the first electrode is electrically connected to the power terminal, the second electrode is electrically connected to an output terminal, and the third electrode is electrically connected to the ground terminal. The output stage structure of claim 1, wherein each of the first auxiliary electrodes is electrically connected to at least one of the adjacent first transistors to be electrically connected to the adjacent two second auxiliary electrodes. One. The output stage structure of claim 1, wherein each of the first auxiliary electrodes is electrically connected to the adjacent two second auxiliary electrodes through at least one of the first transistors that are turned on. The output stage structure of claim 1, wherein each of the second auxiliary electrodes is electrically connected to the adjacent two first auxiliary electrodes through at least one of the first transistors that are turned on. The output stage structure of claim 1, wherein each of the third auxiliary electrodes is electrically connected to at least one of the adjacent second transistors to be electrically connected to the adjacent two fourth auxiliary electrodes. One. The output stage structure of claim 1, wherein each of the third auxiliary electrodes is electrically connected to the adjacent two fourth auxiliary electrodes through at least one of the second transistors that are turned on. The output stage structure of claim 1, wherein each of the fourth auxiliary electrodes transmits at least the second transistors that are turned on One of them is electrically connected to the adjacent two third auxiliary electrodes. The output stage structure of claim 1, wherein the first transistors are respectively a PMOS transistor, and the second transistors are respectively an NMOS transistor.