TWI473236B - Anti-fusse structure and method of fabricating the same - Google Patents

Description

Circuit structure with anti-fuse and manufacturing method thereof

The present invention relates to a circuit structure and a method of fabricating the same, and more particularly to a circuit structure having an antifuse and a method of fabricating the same.

A typical antifuse is a metal layer-insulation layer-metal layer structure. The method of stabilizing and storing digital information by using an antifuse is to apply a high voltage to the antifuse to make the insulating layer in the antifuse. The phenomenon of electric collapse occurs, and the anti-fuse is in an "On" state. Conversely, when no voltage is applied, the antifuse is in an "off" state. In other words, when the insulating layer is electrically non-conductive, the anti-fuse is in a default state; when the insulating layer is electrically turned on, the anti-fuse is in a programmed state.

In general, such antifuse is used in the first end process and in the lower order aluminum process. However, as the integration of integrated circuits increases, the number of metal conductors required increases, and the requirements for the conduction efficiency of metal conductors and the line width of conductors increase, so aluminum is often not suitable as an antifuse. material. Copper has the advantages of low impedance, effective prevention of electromigration, and high melting point (the melting point of copper is about 1060 ° C, and the melting point of aluminum is only about 660 ° C), which has gradually replaced the traditional aluminum. Process. Therefore, what is needed now is an antifuse that can be applied to a copper process and combined with a post-stage process.

The invention provides an anti-fuse structure which can be arranged on the basis of the back-end process Bottom, as a single programmable memory, and can also be applied above the copper process wiring, in line with the needs of today's semiconductor components.

The invention provides a method for manufacturing an anti-fuse structure, which can form an anti-fuse in a process of the latter stage of the wafer, and can be applied to a copper process, which can further promote the miniaturization of the component.

The anti-fuse structure of the present invention is disposed on a substrate having at least one component and a copper metal layer. The anti-fuse structure includes a bottom conductor layer, an insulating layer and a top conductor layer. The bottom conductor layer is disposed above the copper metal layer and electrically connected to the copper metal layer. The insulating layer is compliantly disposed on the bottom conductor layer to cover the edge or corner of the bottom conductor layer to form a corner portion. The top conductor layer is compliantly disposed on the insulating layer.

In an embodiment of the invention, the substrate further includes a dielectric layer disposed between the substrate and a portion of the bottom conductor layer, wherein the corner portion is located at an edge of the dielectric layer.

In an embodiment of the invention, the bottom conductor layer is in contact with the copper metal layer.

In an embodiment of the invention, the substrate further includes a dielectric layer disposed between one end of the bottom conductor layer and the substrate. In still another embodiment, the substrate further includes another dielectric layer disposed between the other end of the bottom conductor layer and the substrate. In still another embodiment, the bottom layer of the bottom conductor layer is electrically connected to the copper metal layer.

In an embodiment of the invention, the substrate further includes a capacitor including a lower electrode, a capacitor dielectric layer and an upper electrode from bottom to top, wherein the lower electrode and the bottom conductor layer are formed of the same material layer, and the capacitor dielectric layer The insulating layer is formed of the same material layer, and the upper electrode and the top conductor layer are formed of the same material layer. In still another embodiment, the thickness of the insulating layer is smaller than that of the capacitor The thickness of the electrical layer.

In an embodiment of the invention, the material of the bottom conductor layer and the top conductor layer comprises titanium, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum, tantalum nitride, aluminum, nickel, zinc, zinc nitride, Chromium or chromium nitride.

In an embodiment of the invention, the component in the substrate includes an interconnect and a MOS component or a memory component under the interconnect and electrically connected to the interconnect.

In an embodiment of the invention, the anti-fuse structure described above is used as a single-programmable memory.

A method of manufacturing an anti-fuse structure of the present invention is as follows. A substrate is provided first in which at least one component and a copper metal layer have been formed. A dielectric layer is then formed on the substrate with openings exposing the copper metal layer. A first conductor layer, an insulating material layer and a second conductor layer are then conformally formed on the dielectric layer to fill the opening. Next, the second conductor layer and the insulating material layer are patterned to form a top conductor layer and an insulating layer, and the insulating layer forms a corner portion at an interface between the open end and the dielectric layer. The first conductor layer is then patterned to form a bottom conductor layer.

In an embodiment of the invention, the insulating layer forms another corner portion at the junction of the other end of the opening and the dielectric layer. In still another embodiment, a lower copper conductor layer is electrically connected under each of the bottom conductor layers of the two ends of the opening.

In an embodiment of the invention, in the step of patterning the second conductor layer and the insulating material layer and patterning the first conductor layer, an upper electrode, a capacitor dielectric layer and a lower electrode are simultaneously formed on the substrate.

In an embodiment of the invention, after forming the insulating material layer and before forming the second conductor layer, further comprising removing a portion of the insulating material layer above the opening, so that The thickness of the insulating layer of the subsequently formed anti-fuse structure is smaller than that of the capacitor dielectric layer.

In an embodiment of the invention, the components in the substrate include interconnects and MOS or memory components that are electrically connected to the interconnects.

Another method of manufacturing the anti-fuse structure of the present invention is as follows. A substrate is first provided in which at least one component and a copper metal layer have been formed. A dielectric layer and a first conductor layer are then formed on the substrate. Thereafter, a portion of the first conductor layer is removed to expose the sidewalls of the first conductor layer. Forming an insulating material layer and a second conductor layer conformally on the first conductor layer, and then patterning the second conductor layer and the insulating material layer to form a top conductor layer and an insulating layer, wherein the insulating layer forms a corner portion on the sidewall of the first conductor layer . The first conductor layer is then patterned to form a bottom conductor layer.

In an embodiment of the invention, in the step of patterning the second conductor layer and the insulating material layer and patterning the first conductor layer, an upper electrode, a capacitor dielectric layer and a lower electrode are simultaneously formed on the substrate.

In an embodiment of the invention, the method of fabricating the anti-fuse structure further includes removing a portion of the dielectric layer in the step of removing a portion of the first conductor layer.

The anti-fuse structure of the present invention can be disposed over the wiring within the back-end process and can be used in a copper process and used as a single programmable memory. Not only can the metal anti-fuse be further applied in the next generation process to increase the component's integration, and it can be integrated with the original capacitor process without the need to develop a new process, so it is quite simple and also helps to save costs. .

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1E illustrate a process of manufacturing a capacitor in a first embodiment of the present invention. A cross-sectional view of the manufacturing process of the anti-fuse structure. FIG. 1F illustrates an example of a circuit structure including the anti-fuse structure of FIG. 1E. FIG. 1G illustrates another example of a circuit structure including the anti-fuse structure of FIG. 1E.

Referring to FIG. 1A, a substrate 100 is first provided, in which at least one component and a copper metal layer 110 have been formed in the substrate 100. The copper metal layer 110 is, for example, a copper wire or a part of a copper metal interconnect. For the components in the substrate 100, please refer to the description of FIG. 1F below. A dielectric layer 120 is formed on the substrate 100. The dielectric layer 120 has an opening 127 to expose the copper metal layer 110. The material of the dielectric layer 120 is, for example, a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride. In the present embodiment, the dielectric layer 120 is composed of, for example, a bottom dielectric layer 122 made of tantalum nitride and a top dielectric layer 124 made of tantalum oxide. The opening 127 of the dielectric layer 120 is formed by, for example, a lithography process, forming a patterned photoresist layer 125 over the dielectric layer 120, and then removing the exposed dielectric layer 120.

Referring to FIG. 1B, after the patterned photoresist layer 125 is removed by wet or dry photoresist, the first conductor layer 130, the insulating material layer 140 and the second conductor layer 150 are formed conformally on the dielectric layer 120. Fill in the opening 127. The first conductor layer 130 and the second conductor layer 150 are made of, for example, titanium, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum, tantalum nitride, aluminum, nickel, zinc, zinc nitride, chromium or chromium nitride. . The formation method thereof is, for example, physical vapor deposition or chemical vapor deposition. The material of the insulating material layer 140 is a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride, or may be a dielectric material of two or more layers, such as a three-layer stacked structure of hafnium oxide, tantalum nitride and hafnium oxide. The method of forming the insulating material layer 140 is, for example, a chemical vapor deposition method. In an embodiment, the second A protective layer 160 may also be formed over the conductor layer 150 to cover the second conductor layer 150. The material of the protective layer 160 is, for example, cerium oxide whose source is tetraethoxy cerium (TEOS), and is formed by, for example, chemical vapor deposition. In an embodiment, after forming the insulating material layer 140, before forming the second conductive layer 150, a portion of the insulating material layer 140 above the opening 127 may be removed first, thereby reducing the thickness of the portion of the insulating material layer 140, thereby adjusting The breakdown voltage of the subsequently formed antifuse.

Next, referring to FIG. 1C, the second conductor layer 150 and the insulating material layer 140 are patterned to form a top conductor layer 150a and an insulating layer 140a. The insulating layer 140a forms a corner portion 145 at the junction of the opening 127 and the dielectric layer. The method of patterning the second conductive layer 150 and the insulating material layer 140 is, for example, forming a patterned photoresist layer 163 on the substrate 100, covering the second conductor layer 150 above the opening 127, the insulating material layer 140 and the first A conductor layer 130. Then, the patterned photoresist layer 163 is used as a mask, and the exposed second conductor layer 150 and the insulating material layer 140 are removed, and then the patterned photoresist layer 163 is removed. The method of removing the exposed second conductor layer 150 and the insulating material layer 140 is, for example, a dry etching method such as reactive ion etching. In the present embodiment, the insulating material layer 130 exposed by the patterned photoresist layer 163 is not completely removed, leaving a thin layer on the first conductor layer 130.

The result of patterning the second conductor layer 150 and the insulating material layer 140 is that the top conductor layer 150a and the insulating layer 140a are formed. It is also possible to simultaneously form the upper electrode 150b and the capacitor dielectric layer 140b on the substrate 100 as shown in FIG. 1C.

Referring to FIG. 1D, after the patterned photoresist layer 163 is removed, another protective layer 165 may be formed over the protective layer 160. The first conductor layer 130 is then patterned to form the bottom conductor layer 130a. The bottom conductor layer 130a, the insulating layer 140a, and the top conductor layer 150a constitute an antifuse 155a. The method of patterning the first conductor layer 130 is, for example, a lithography process, using the patterned photoresist layer 169 as a mask, removing a portion of the first conductor layer 130, and then removing the patterned photoresist layer 169. A method of removing a portion of the first conductor layer 130 is, for example, a dry etching method such as a reactive ion etching method. While the first conductor layer 130 is patterned, a lower electrode 130b may be formed under the capacitor dielectric layer 140b. The lower electrode 130b, the capacitor dielectric layer 140b, and the upper electrode 150b constitute a capacitor 155b. In an embodiment, the capacitor 155b is for example used in a multimedia memory card (MMC).

In one embodiment, the insulating material layer 140 over the opening 127 is removed a portion first, and thus the insulating layer 140a in the anti-fuse 155a is relatively thin. In other words, the thickness of the capacitor dielectric layer 140b of the capacitor 155b may be greater than the thickness of the insulating layer 140a of the antifuse 155a.

Thereafter, referring to FIG. 1E, an interlayer dielectric layer 170, a plug 175, a dielectric layer 180, and an aluminum pad 190 are sequentially formed on the substrate 100, so that appropriate voltages are applied to the respective nodes to operate the circuit structure. The method of forming the interlayer dielectric layer 170, the plug 175, the dielectric layer 180 and the aluminum pad 190 is well known to those skilled in the art and will not be described herein.

Referring to FIG. 1F, it is particularly noted that the antifuse of the present embodiment is formed in a subsequent process, in other words, at least one component has been formed in the substrate 100. This component is, for example, an interconnect 108 and a MOS component 104 or memory component 106 that is electrically connected to the underlying interconnect 108. Between the MOS element 104 and the memory element 106 is, for example, an isolation structure 102 Phase separation. Of course, the components in the substrate 100 may also be other passive components such as inductors, capacitors, or resistors, or various components such as non-volatile memory, random access memory, and the like. The antifuse provided in this embodiment is not limited to forming any particular element.

Since electrons are easily concentrated at the corners of the anti-fuse 155a, digital information can be stored in the anti-fuse 155a by applying a sufficient voltage to be greater than the breakdown voltage at the corner 145 of the insulating layer 140a. The antifuse 155a is used as a single programmable memory.

Referring to FIG. 1G, since the anti-fuse 155a has two corner portions 145a, 145b, in another embodiment, the opening 127 may be disposed on the copper metal layers 113a, 113b so that the two corners are below the 145a, 145b. The bottom conductor layer 130a is electrically connected to the copper metal layers 113a and 113b, respectively. In this way, a single memory of a single memory cell can be formed, and the digit information of one bit is stored at the corners 145a and 145b, respectively.

In addition to the above structure, the anti-fuse of the present invention may have other layout and formation methods. Please refer to the fabrication of the anti-fuse structure integrated with the capacitor process according to the second embodiment of the present invention illustrated in FIGS. 2A-2E. A cross-sectional view of the process. 2F shows an example of a circuit structure including the anti-fuse structure of FIG. 2E. Regarding the material and formation method of each film layer in this embodiment, similar to the previous embodiment, reference can be made to the description in the previous embodiment.

Referring to FIG. 2A, a substrate 200 is first provided, in which at least one component and a copper metal layer 210 have been formed in the substrate 200. For the components in the substrate 200, please refer to the description of FIG. 2F below. A dielectric layer 220 and a first conductor layer 230 are formed on the substrate 200. In this embodiment, the dielectric layer 220 is, for example, tantalum nitride. The bottom dielectric layer 222 of the material and the top dielectric layer 224 of the yttria material. Thereafter, a portion of the first conductor layer 230 is removed to expose the sidewalls of the first conductor layer 230. In the embodiment, in the step of removing a portion of the first conductor layer 230, for example, a portion of the dielectric layer 220 (the top dielectric layer 224) is removed. The method of removing a portion of the first conductive layer 230 is, for example, by forming a patterned photoresist layer 235 above the first conductive layer 230 by a photolithography etching process, and then removing the bare by dry etching, such as reactive ion etching. It is completed by the first conductor layer 230.

Referring to FIG. 2B, after the patterned photoresist layer 235 is removed by wet photoresist or dry photoresist removal, the insulating material layer 240 and the second conductive layer 250 are conformally formed on the first conductor layer 230. The material of the first conductor layer 230 and the second conductor layer 250 is, for example, titanium, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum, tantalum nitride, aluminum, nickel, zinc, zinc nitride, chromium or Chromium nitride. The material of the insulating material layer 240 is a dielectric material such as hafnium oxide, tantalum nitride or hafnium oxynitride, or may be a dielectric material of two or more layers, such as a three-layer stack of hafnium oxide, tantalum nitride and hafnium oxide. The method of forming the insulating material layer 240 is, for example, a chemical vapor deposition method. In an embodiment, a protective layer 260 may be formed over the second conductor layer 250 to cover the second conductor layer 250. The material of this protective layer 260 is, for example, cerium oxide whose source is tetraethoxy cerium (TEOS). In an embodiment, after the formation of the insulating material layer 240, before forming the second conductive layer 250, the portion of the insulating material layer 240 on the right side is removed, and the thickness of the insulating material layer 240 is reduced thereby, thereby adjusting the subsequent formation. The breakdown voltage of the anti-fuse.

Next, referring to FIG. 2C, the second conductor layer 250 and the insulating material are patterned. The material layer 240 forms a top conductor layer 250a and an insulating layer 240a. The insulating layer 240a forms a corner portion 245 at the edge of the first conductor layer 230. The method of patterning the second conductive layer 250 and the insulating material layer 240 is, for example, forming a patterned photoresist layer 263 on the substrate 200, and the patterned photoresist layer 263 covers the step above the edge of the first conductor layer 230. The second conductor layer 250 and the insulating material layer 240. Then, the patterned photoresist layer 263 is used as a mask, and the exposed second conductor layer 250 and the insulating material layer 240 are removed, and then the patterned photoresist layer 263 is removed. In the present embodiment, the insulating material layer 240 exposed by the patterned photoresist layer 263 is not completely removed, leaving a thin layer on the first conductor layer 230.

The result of patterning the second conductor layer 250 and the insulating material layer 240 is that the top conductor layer 250a and the insulating layer 240a are formed. It is also possible to simultaneously form the upper electrode 250b and the capacitor dielectric layer 240b on the substrate 200 as shown in FIG. 2C.

Referring to FIG. 2D, after the patterned photoresist layer 263 is removed, another protective layer 265 may be formed over the protective layer 260, and then the first conductor layer 230 is patterned to form the bottom conductor layer 230a. The bottom conductor layer 230a, the insulating layer 240a, and the top conductor layer 250a constitute an antifuse 255a. The method of patterning the first conductor layer 230 is, for example, a lithography process, using the patterned photoresist layer 269 as a mask, removing a portion of the first conductor layer 230, and then removing the patterned photoresist layer 269. While patterning the first conductor layer 230, a lower electrode 230b may also be formed under the capacitor dielectric layer 240b. The lower electrode 230b, the capacitor dielectric layer 240b, and the upper electrode 250b constitute a capacitor 255b. In an embodiment, the capacitor 255b is for example used in a multimedia memory card (MMC).

In one embodiment, the insulating material layer 240 at the edge of the first conductor layer 230 is removed a portion first, and thus the insulating layer 240a in the anti-fuse 255a is relatively thin. In other words, the thickness of the capacitor dielectric layer 240b of the capacitor 255b may be greater than the thickness of the insulating layer 240a of the antifuse 255a to meet different electrical requirements.

Thereafter, referring to FIG. 2E, an interlayer dielectric layer 270, a plug 275, a dielectric layer 280, and an aluminum pad 290 are formed on the substrate 200 in sequence, which illustrates the interlayer dielectric formed on the substrate 100 as in the first embodiment. Layer 170, plug 175, dielectric layer 180 and aluminum pad 190.

Referring to FIG. 2F, it is particularly noted that the antifuse in this embodiment is formed in a subsequent process, in other words, at least one component has been formed in the substrate 200. This component is, for example, an interconnect 208 and a MOS component 204 or memory component 206 that is electrically connected to the interconnect 208 under the interconnect 208. The MOS element 204 and the memory element 206 are separated from one another by, for example, an isolation structure 202.

Since the electrons are easily concentrated at the corners of the anti-fuse 255a, digital information can be stored in the anti-fuse 255a by applying a sufficient voltage to be greater than the breakdown voltage at the corner 245 of the insulating layer 240a. The antifuse 255a is used as a single programmable memory.

In summary, the present invention can form the antifuse in the back-end process, and utilize the structural layout and design to integrate the metal anti-fuse process on the copper process, and form a single pass on the copper metal layer. Stylized memory. In this way, the metal anti-fuse process can be applied to the next generation of semiconductor processes. In addition, the manufacturing process of the above anti-fuse is very simple, and it is not necessary In addition, the development of new processes, and even the integration of the original capacitor process, can save production costs and simplify the process.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ base

102, 202‧‧‧ isolation structure

104, 204‧‧‧MOS components

106, 206‧‧‧ memory components

108, 208‧‧‧ interconnection

110, 113a, 113b, 210‧‧‧ copper metal layer

120, 220‧‧‧ dielectric layer

122, 222‧‧‧ bottom dielectric layer

124, 224‧‧‧ top dielectric layer

125, 163, 169, 235, 263, 269‧‧‧ patterned photoresist layers

127‧‧‧ openings

130, 230‧‧‧ first conductor layer

130a, 230a‧‧‧ bottom conductor layer

130b, 230b‧‧‧ lower electrode

140, 240‧‧‧Insulation layer

140a, 240a‧‧‧Insulation

140b, 240b‧‧‧ capacitor dielectric layer

145, 145a, 145b, 245a, 245b‧‧‧ corner

150, 250‧‧‧ second conductor layer

150a, 250a‧‧‧ top conductor layer

150b, 250b‧‧‧ upper electrode

155a, 255a‧‧‧ anti-fuse

155b, 255b‧‧‧ capacitor

160, 165, 260, 265‧ ‧ protective layer

170, 270‧‧ ‧ interlayer dielectric layer

175, 275‧‧ ‧ plug

180, 280‧‧ dielectric layer

190, 290‧‧‧ aluminum pad

1A-1E are cross-sectional views showing a manufacturing process of an anti-fuse structure integrated with a capacitor process in a first embodiment of the present invention.

FIG. 1F illustrates an example of a circuit structure including the anti-fuse structure of FIG. 1E.

FIG. 1G illustrates another example of a circuit structure including the anti-fuse structure of FIG. 1E.

2A-2E are cross-sectional views showing a manufacturing process of an anti-fuse structure integrated with a capacitor process in a second embodiment of the present invention.

FIG. 2F illustrates an example of a circuit structure including the anti-fuse structure of FIG. 2E.

100‧‧‧Base

102‧‧‧Isolation structure

104‧‧‧MOS components

106‧‧‧ memory components

108‧‧‧Interconnection

110‧‧‧ copper metal layer

120‧‧‧ dielectric layer

122‧‧‧ bottom dielectric layer

124‧‧‧Top dielectric layer

127‧‧‧ openings

130a‧‧‧Bottom conductor layer

130b‧‧‧ lower electrode

140a‧‧‧Insulation

140b‧‧‧capacitor dielectric layer

145‧‧‧ Corner

150a‧‧‧Top conductor layer

150b‧‧‧Upper electrode

155a‧‧‧Anti-fuse

155‧‧‧ capacitor

160, 165‧‧ ‧ protective layer

170‧‧‧Interlayer dielectric layer

175‧‧‧ plug

180‧‧‧ dielectric layer

190‧‧‧Aluminum pad

Claims (8)

An anti-fuse structure is disposed on a substrate having at least one component and a copper metal layer, and the anti-fuse structure comprises: a bottom conductor layer disposed above the copper metal layer, the bottom conductor layer Electrically connecting with the copper metal layer; an insulating layer is disposed on the bottom conductor layer, the insulating layer covers an edge or a corner of the bottom conductor layer to form a corner portion; and a top conductor layer conformally Provided on the insulating layer; a dielectric layer disposed between the substrate and the bottom conductor layer, and another dielectric layer disposed between the dielectric layer and the substrate, wherein the bottom conductor layer and the dielectric layer The sidewall of the electrical layer is aligned and covers the other dielectric layer; and a capacitor comprising a lower electrode, a capacitor dielectric layer and an upper electrode from bottom to top, the lower electrode and the bottom conductor layer being of the same material layer Forming, the capacitor dielectric layer and the insulating layer are formed of the same material layer, and the upper electrode and the top conductor layer are formed of the same material layer. The anti-fuse structure of claim 1, wherein the dielectric layer is disposed between the substrate and a portion of the bottom conductor layer, and the corner portion is located at an edge of the dielectric layer. The anti-fuse structure of claim 1, wherein the bottom conductor layer is in contact with the copper metal layer. The anti-fuse structure according to claim 1, wherein the bottom conductor layer is electrically connected to the two copper metal layers respectively. The anti-fuse structure according to claim 1, wherein the insulating layer has a thickness smaller than a thickness of the capacitor dielectric layer. The anti-fuse structure according to claim 1, wherein the bottom conductor layer and the top conductor layer material comprise titanium, titanium nitride, tungsten nitride, titanium tungsten nitride, tantalum, tantalum nitride, aluminum, Nickel, zinc, zinc nitride, chromium or chromium nitride. The anti-fuse structure of claim 1, wherein the component comprises an interconnect, and a MOS component or a memory component under the interconnect and electrically connected to the interconnect. The anti-fuse structure as described in claim 1, which is used as a single-programmable memory.