TWI473208B - Method of fabricating cmos - Google Patents

Description

Method for fabricating complementary MOS semiconductor crystal

This invention relates to a semiconductor device, and more particularly to a method of fabricating a complementary MOS transistor.

A conventional metal oxide semiconductor (MOS) transistor usually includes a substrate, such as a germanium substrate, a source region, a drain region, a channel between the source region and the drain region, and a gate. The pole is located above the channel, a gate dielectric layer is interposed between the gate and the substrate, and a sidewall is located on the sidewall of the gate and gate dielectric layers. In general, a MOS transistor, under a fixed electric field, will have a current flow through the channel proportional to the carrier mobility in the channel. Therefore, increasing the carrier mobility to increase the speed of the MOS transistor has become a major issue in the field of semiconductor technology.

Among the currently known techniques, there is a method of manufacturing mechanical stress in a channel to enhance carrier mobility. For example, epitaxial formation of a germanium germanium (SiGe) channel layer on a germanium substrate to form a compressive strained channel can significantly increase hole mobility. Or epitaxially forming a silicon channel on the germanium telluride layer to form a tensile strained channel, which can significantly increase the electron mobility. It utilizes the different lattice constants of the bismuth telluride layer and the enthalpy, so that the bismuth epitaxial layer is structurally strained in the ruthenium substrate to form strain enthalpy. Since the lattice constant of the tantalum layer is larger than that of the tantalum, this causes a change in the band structure of the tantalum, which causes an increase in carrier mobility, thereby increasing the speed of the MOS transistor.

However, as the size of MOS transistors continues to be toward miniaturization, the speed demand for MOS transistors is continually increasing, and it has been difficult to achieve the desired degree by using the compressive stress or tensile stress formed by the above-mentioned conventional techniques.

In view of this, the applicant proposes a method of fabricating a MOS transistor to improve the disadvantages of the above-mentioned prior art, thereby improving the performance of the CMOS transistor.

The present invention provides a method of fabricating a MOS transistor, first providing a substrate comprising a first transistor region, a second transistor region, and an insulator located in the first transistor region and the second transistor region The first transistor region is a transistor for forming a first conductivity type, and the first transistor region includes a first gate and a first source/drain region. The second transistor region is a transistor for forming a second conductivity type, and the second transistor region includes a second gate and a second source/drain region, and then a first An amorphous germanium forming process forms an amorphous germanium structure in the first source/drain region, and then forms a first stress layer covering the first gate and the first source/drain region, and then performing a first a tempering process, after forming a first strain channel in the substrate under the first gate, removing the first stress layer, and then performing a second amorphous deuteration process on the second source/汲An amorphous deuterated structure is formed in the polar region, and then a second stress layer is formed to cover a second gate and the second source/drain region, followed by a second tempering process, forming a second strain channel in the substrate under the second gate, and finally removing the second Stress layer.

The present invention further provides a method of fabricating a MOS transistor, first providing a substrate including a first transistor region, a second transistor region, and an insulator located in the first transistor region and the second transistor region The first transistor region is configured to form a first conductivity type of transistor, and the first transistor region includes a first gate and a first source/drain region. The second transistor region is used to form a second conductivity type transistor, and the second transistor region includes a second gate and a second source/drain region, and then an amorphous deuteration process is performed. Forming an amorphous germanium structure in the first source/drain region and the second source/drain region, and then forming a first surface on the first gate and the first source/drain region a stress layer, and then forming a second stress layer on the surface of the second gate and the second source/drain region, and then performing a tempering process for the first gate and the second gate Forming a first strain channel and a second strain channel in the lower substrate The first layer and the stress of the second stress layer is finally removed.

The complementary MOS transistor process of the present invention utilizes an amorphous germanium structure in the source/drain region, and is then overlaid on the N-type semiconductor and the P-type semiconductor using the stretch and compressive stress layers, respectively, and is tempered. In addition, the stress memory technology of the source/drain region is completed; in addition, the present invention can also form a tantalum carbide in the source/drain regions of the N-type semiconductor and the P-type semiconductor in combination with the solid phase epitaxial technique. And phlegm. As a result, CMOS has an additive carrier mobility achieved by stress memory technology (SMT) and solid phase epitaxy (SPE).

Please refer to FIG. 1 to FIG. 6 . FIG. 1 to FIG. 6 are schematic diagrams showing a process for fabricating a CMOS transistor according to a first preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10, such as a germanium substrate or an insulating layer overlying germanium (SOI) substrate, etc., is provided first, and the substrate 10 includes a first transistor region 12 and a second transistor region 14, And is isolated by an insulator such as shallow trench isolation (STI) 16, wherein the first transistor region 12 is an active region of a transistor for forming a first conductivity type, that is, is disposed at the first The transistor in the crystal region 12 is in a first conductivity type, such as an N-type MOS transistor; the second transistor region 14 is an active region of a transistor used to form a second conductivity type, that is, disposed in The transistor in the second transistor region 14 is in a second conductivity type, such as a P-type MOS transistor.

In addition, the first transistor region 12 includes a first gate 18 and a source/drain region 22; the second transistor region 14 includes a second gate 20 and a source/drain region 24. A gate dielectric layer 26 is further included between the first gate 18 and the substrate 10, and a gate dielectric layer 28 is further included between the second gate 14 and the substrate 10. The first gate 18 and the second gate are further included. The side walls of the pole 20 are also provided with side walls 30, 32, respectively. Generally, the first gate 18 and the second gate 20 comprise a conductive material such as doped polysilicon or metal germanide, and the gate dielectric layers 26 and 28 may comprise an insulating material such as a germanium oxide compound or a germanium oxide compound, or A high-k dielectric material, and the sidewall sub-system is composed of an insulating material such as a cerium oxide compound or a cerium compound. It should be noted that, in addition to the single layer structure as shown in the figure, the side wall may also be a two-layer structure including an offset spacer and a main spacer, or A side wall (not shown) comprising a three-layer structure.

Next, an amorphous deuteration process is performed, and the first gate 18 and the second gate 20 are used as masks to form an amorphous germanium structure in the source/drain regions 22, 24. It is worth noting that the amorphous deuteration process can be a blanket single ion implantation process, for example, using Xenon (Xe) ions or argon (Ar) ions, etc. The transistor region 12 and the source/drain regions 22, 24 of the second transistor region 14. In accordance with a preferred embodiment of the present invention, after the amorphous germanium structure is completed, then dopants can be implanted in the source/drain regions 22, 24 as source/drain conductive, for example, when When the first conductivity type is N-type and the second conductivity type is P-type, N-type dopant is implanted in the source/drain region 22, and P-type is implanted in the source/drain region 24. Doping. At this time, the first gate 18, the source/drain region 22, the gate dielectric layer 26 and the sidewall spacer 30 in the first transistor region 12 together form a transistor 33 having a first conductivity type; Similarly, the second gate 20, the source/drain region 24, the gate dielectric layer 28 and the sidewall spacer 32 in the second transistor region 14 together form a transistor 35 having a second conductivity type. However, the invention is not limited to implanting dopants in the source/drain regions 22, 24 only at the aforementioned points in time. Depending on the product design, the dopants in the source/drain regions 22, 24 as conductive species can also be implanted in subsequent processes; or the source/germination can be implanted before the amorphous germanium structure is completed. The dopants of the polar regions 22, 24. This should be within the scope of the invention.

Then, as shown in FIG. 2, a deposition process is performed to form a first stressor layer 34 on the substrate 10, covering the first gate 18, the source/drain region 22, the shallow trench isolation 16, and the second gate. Pole 20 and source/drain regions 24. Next, as shown in FIG. 3, the second gate 20 and source/drain regions 24, and portions of the first trench layer 34 on the shallow trench isolations 16 are removed using a lithography and etching process.

As shown in FIG. 4, another deposition process is performed to form a second stressor layer 36 on the substrate 10. The second stressor layer 36 covers the first gate layer 18, the first stressor layer 34 on the source/drain region 22, the second gate 20 and the source/drain regions 24, and a portion of the shallow trench isolation 16. As shown in FIG. 5, the second stressor layer 36 on the first gate 18, the source/drain region 22, and a portion of the shallow trench isolation 16 is then removed. It should be noted that when the first conductive type and the second conductive type are respectively N-type and P-type, the first stress layer 34 and the second stress layer 36 are respectively a tensile film. And a compressive film.

As shown in FIG. 6, then, a tempering process is performed. According to a preferred embodiment of the present invention, the tempering process is a low temperature tempering process, and the temperature ranges from 580 ° C to 850 ° C to source the source / The amorphous deuterated structure in the drain regions 22, 24 utilizes this single tempering process while rearranging the germanium atoms in accordance with the stretching/compression directions provided by the first stressor layer 34 and the second stressor layer 36, A first strain channel 40 is formed in the substrate 10 below the gate 18, and a second strain channel 42 is formed in the substrate 10 below the second gate 14. Finally, the first stressor layer 34 and the second stressor layer 36 are removed. The stress memorization technique (SMT) of the source/drain region was completed using a single low temperature tempering process. It should be noted that when the first transistor 12 and the second transistor 14 are respectively N-type and P-type, the first strain channel 40 and the second strain channel 42 are respectively a strain strain channel, and A compression strain 矽 channel.

According to a second preferred embodiment of the present invention, the present invention can also be directly substituted with carbon (carbon) ions and germanium (Ge) ions during the single ion implantation process of the aforementioned blanket. Helium ions or argon ions are used to ionize the corresponding electro-optic crystals to be amorphous. For example, when the first conductivity type is N-type and the second conductivity type is P-type, carbon ions may be implanted in the source/drain region 22 and implanted in the source/drain region 24 Helium ion. The remaining steps are the same as those in the first preferred embodiment. Compared with the first embodiment, the second embodiment can form an amorphous germanium structure directly in the source/drain regions 22, 24 by using carbon ions and germanium ions, and then use a tempering process to make the germanium atoms according to the first The tensile/compression directions provided by the stress layer 34 and the second stress layer 36 are rearranged to form corresponding tensile strain channels and compressive strain channels, and the implanted carbon ions and helium ions are also present in this single In the low temperature tempering process, solid-phase epitaxy (SPE) is formed in the source/drain regions 22, 24 in the substrate 10 on both sides of the first gate 18 and the second gate 20, for example, Embedded silicon carbon dioxide (eSiC) is formed in the source/drain region 22, and embedded silicon Germanium (eSiGe) is formed in the source/drain region 24 (not shown). As is well known to those skilled in the art or those skilled in the art, solid phase epitaxy of tantalum carbide and tantalum carbide can also provide tensile/compression stress in the tantalum substrate, such that the first strained channel 40 and the second strained channel The tension/compression stress in 42 is more strengthened, so that it can be made The resulting crystal has an additive carrier mobility. Similarly, the source/drain regions 22, 24 are used as conductive dopants, and the implantation step can be performed before or after the carbon ions and cesium ions are implanted or after the carbon ions and cesium ions are implanted. After solid phase epitaxy.

According to the third preferred embodiment of the present invention, in the first single ion implantation process in the foregoing first embodiment, helium ions or argon ions may be used simultaneously in the source/drain regions 22, 24. Forming an amorphous deuterated structure, and then, when the first conductivity type is N type and the second conductivity type is P type, carbon ions may be implanted in the source/drain region 22, and the source/汲The polar region 24 is further implanted with erbium ions to individually provide the dopants required for solid phase epitaxy (SPE) for the corresponding electrical transistors. The remaining steps are the same as those in the first preferred embodiment, and the stress/memory (SMT) and solid phase epitaxy (SPE) of the source/drain regions are simultaneously performed by a single low temperature tempering process. Similarly, the dopants used as the conductive in the source/drain regions 22, 24 may be implanted in a carbon ion and germanium ion cloth before the completion of the amorphous germanium structure or after the completion of the amorphous germanium structure. Before planting or after forming solid phase epitaxy.

Please refer to FIG. 7 to FIG. 12 . FIG. 7 to FIG. 12 are schematic diagrams showing a process for fabricating a CMOS transistor according to a fourth preferred embodiment of the present invention. For the sake of simplicity, the components of the same function are extended to the first. The symbol of the component in the embodiment.

As shown in FIG. 7, first, a substrate 10 such as a germanium substrate or an insulating layer overlying germanium (SOI) substrate is provided, and the substrate 10 includes a first transistor region 12 and a second transistor region 14, It is isolated by insulation such as shallow trench isolation (STI) 16. The first transistor region 12 is an active region of a transistor for forming a first conductivity type, that is, is disposed at the first electrode. The transistor in the crystal region 12 is in a first conductivity type, such as an N-type MOS transistor; the second transistor region 14 is an active region of a transistor used to form a second conductivity type, that is, a set The transistor in the second transistor region 14 is in a second conductivity type, such as a P-type MOS transistor.

In addition, the first transistor region 12 includes a first gate 18 and a source/drain region 22; the second transistor region 12 includes a second gate 20 and a source/drain region 24. A gate dielectric layer 26 is further included between the first gate 18 and the substrate 10, and a gate dielectric layer 28 is further included between the second gate 14 and the substrate 10. The first gate 18 and the second gate are further included. The side walls of the pole 20 are also provided with side walls 30, 32, respectively. Generally, the first gate 18 and the second gate 20 comprise conductive materials such as doped polysilicon and metal telluride, and the dielectric layers 26 and 28 are composed of an insulating material such as a silicon oxide compound or a nitrogen oxide compound. The sidewall substructure is composed of an insulating material such as a silicon oxide compound or a nitrogen ruthenium compound. It should be noted that, in addition to the single layer structure as shown in the figure, the side wall may also be a two-layer structure including an offset spacer and a main spacer, or A side wall (not shown) comprising a three-layer structure.

Next, a mask 50, such as a photoresist, is formed over the second transistor region 14 and a portion of the shallow trench isolation 16 to expose the first transistor region 12. Next, an amorphous deuteration process is performed, for example, ion implantation is performed in the source/drain region 22 using helium ions or argon ions, and an amorphous deuteration process is performed only in the source/drain regions 22 to form an amorphous deuterated structure. . In accordance with a preferred embodiment of the present invention, upon completion After the amorphous germanium structure, a dopant can then be implanted in the source/drain region 22 as a source/drain conductor, for example, when the first conductivity type is N-type, then the source An N-type dopant is implanted in the pole/drain region 22. At this time, the first gate 18, the source/drain region 22, the gate dielectric layer 26 and the sidewall spacer 30 in the first transistor region 12 constitute a transistor 33 having a first conductivity type. Then, the mask 50 is removed. However, the present invention is not limited to implanting dopants in the source/drain regions 22 only at the aforementioned point in time. Depending on the product design, the dopants in the source/drain regions 22 may also be implanted in subsequent processes; or the implants in the source/drain regions 22 may be implanted prior to completion of the amorphous germanium structure. quality.

Subsequently, as shown in FIG. 8, a deposition process is performed to form a first stressor layer 34 on the substrate 10, covering the first gate 18, the source/drain region 22, the shallow trench isolation 16, and the second gate. Pole 20 and source/drain regions 24. Then, a first tempering process is performed. According to a preferred embodiment of the present invention, the first tempering process is a low temperature tempering process, and the temperature ranges from 580 ° C to 850 ° C, and the source/drain region is The amorphous germanium structure in 22 utilizes a first tempering process to rearrange the germanium atoms in accordance with the stress direction provided by the first stressor layer 34 to form a first strain in the substrate 10 below the first gate electrode 18. Channel 40. Then, as shown in Fig. 9, the first stressor layer 34 is removed.

Next, as shown in FIG. 10, a mask 52, such as a photoresist, is formed over the first transistor region 12 and a portion of the shallow trench isolation 16 to expose the second transistor region 14. Next, an amorphous deuteration process is performed, for example, using a cesium ion Or argon ions are ion implanted in the source/drain regions 24 to form an amorphous germanium structure in the source/drain regions 24. In accordance with a preferred embodiment of the present invention, after the amorphous germanium structure is completed, a dopant can then be implanted in the source/drain region 24 as a source/drain conductive, for example, when When the conductivity type is P-type, a P-type dopant is implanted in the source/drain region 24. At this time, the second gate 20, the source/drain region 24, the gate dielectric layer 28 and the sidewall spacer 32 in the second transistor region 14 constitute a transistor 35 having a second conductivity type. Then, the mask 52 is removed. However, the present invention is not limited to implanting dopants in the source/drain regions 24 only at the aforementioned point in time. Depending on the product design, the dopant in the source/drain region 24 can also be implanted in subsequent processes; or the dopant in the source/drain region 24 can be implanted before the amorphous germanium structure is completed. . This should be within the scope of the invention.

Next, as shown in FIG. 11, a second stress film 36 is formed covering the first gate 18, the source/drain regions 22, the shallow trench isolation 16, the second gate 20, and the source/drain regions 24 .

Then, a second tempering process is performed. According to a preferred embodiment of the present invention, the second tempering process is a low temperature tempering process, and the temperature range is from 580 ° C to 850 ° C, and the source/drain region is The amorphous germanium structure in 24 utilizes a second tempering process to rearrange the germanium atoms in accordance with the stress direction provided by the second stressor layer 36 to form a second strain in the substrate 10 below the second gate electrode 20. Channel 42. Finally, as shown in Fig. 12, the second stressor layer 36 is removed, at which time the stress/memory technique (SMT) of the source/drain regions is completed.

It should be noted that when the first conductive type and the second conductive type are N-type and P-type, respectively, the first stress layer 34 and the second stress layer 36 are respectively a tensile film and a compressed film. (compressive film), the first strained channel 40 and the second strained channel 42 are respectively a tensile strain channel and a compression strain channel.

According to the fifth preferred embodiment of the present invention, the cesium ion or argon ion used in the amorphous bismuth process of the fourth preferred embodiment of the present invention may be replaced with carbon ions and cerium ions. For example, when the first conductivity type and the second conductivity type are N-type and P-type, respectively, the carbon ions can be directly implanted in the amorphous deuteration process shown in FIG. In the amorphous deuteration process shown in Fig. 10, the cesium ions are directly used for implantation. Compared with the fourth embodiment, the fifth embodiment forms an amorphous germanium structure in the source/drain region 22 by using carbon ions, and then uses the first tempering process to make the germanium atoms according to the first stress layer 34. The provided extension directions are rearranged to form the extension strain channel 40, and the implanted carbon ions are also required for the first tempering process to provide solid phase epitaxy (SPE) for the N-type transistor. The dopant further forms embedded silicon carbon (eSiC) in the source/drain region 22; likewise, the subsequent erbium ion implantation forms amorphous germanium in the source/drain region 24. Structure, and during the second tempering process, the germanium atoms are rearranged according to the compression direction provided by the second stressor layer 36 to form a compressive strain channel 42 and the implanted germanium ions are also The secondary tempering process serves as a dopant for the solid phase epitaxy (SPE) of the P-type transistor, thereby forming an embedded silicon germanium (eSiGe) in the source/drain region 24 (Fig. Show). As is well known to those skilled in the art or those skilled in the art, solid phase epitaxy of bismuth telluride and tantalum carbide can also provide relative tensile/compression stress in the ruthenium substrate, such that the first strain enthalpy channel 40 and the second strain The tensile/compression stress in the channel 42 is further enhanced, so that the transistor has an additive carrier mobility achieved by stress memory technology (SMT) and solid phase epitaxy (SPE). Similarly, the source/drain regions 22, 24 are used as conductive dopants, and the implantation step can be performed before the carbon ions and cesium ions are implanted or after the carbon ions and cesium ions are implanted, and tempered. Before the process or after the formation of solid phase epitaxy.

According to the sixth preferred embodiment of the present invention, in the amorphous deuteration process shown in FIG. 7 of the foregoing fourth embodiment, the source/drain regions 22 may be amorphously formed using helium ions or argon ions. Structure, then, when the first conductivity type is N-type and the second conductivity type is P-type, carbon ions are implanted directly in the source/drain region 22. Subsequently, in the amorphous deuteration process shown in Fig. 10 of the foregoing fourth embodiment, similarly, germanium ions or argon ions are used first to form an amorphous germanium structure in the source/drain regions 24, which is then more The source/drain region 24 is then implanted with strontium ions. The remaining steps are the same as those in the fourth preferred embodiment, and the stress/memory technology (SMT) and solid phase epitaxy (SPE) of the source/drain regions are completed by a secondary low temperature tempering process. Similarly, the dopants used as the conductive in the source/drain regions 22, 24 may be implanted in a carbon ion and germanium ion cloth before the completion of the amorphous germanium structure or after the completion of the amorphous germanium structure. Before planting or after forming solid phase epitaxy.

In addition, the time points implemented by the stress memory technology (SMT) in the above various embodiments may be selectively performed after the completion of the sidewalls of the single-layer structure or after the completion of the partial sidewalls in the sidewalls of the two-layer structure or the main After the completion of the sidewalls or after the completion of the second layer of the sidewalls of the three-layer structure is completed.

Furthermore, various embodiments of the present invention may be combined with other techniques that can form mechanical stresses, such as epitaxial formation of germanium telluride/zinc carbide (SiGe/SiC refill) in the substrate on either side of the gate, or using strain. Stress liner technology and the like are used in other ways. In this way, the performance of the MOS transistor can be improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Base

12. . . First transistor region

14. . . Second transistor region

16. . . Shallow trench isolation

18. . . First gate

20. . . Second gate

22, 24. . . Source/bungee area

26, 28. . . Gate dielectric layer

30, 32. . . Side wall

34. . . First stress layer

36. . . Second stress layer

40. . . First strain channel

42. . . Second strain channel

50, 52. . . Mask

33. . . First conductivity type transistor

35. . . Second conductivity type transistor

1 to 6 are schematic views showing a process for fabricating a CMOS transistor according to a preferred embodiment of the present invention.

7 to 12 are schematic views showing a process of fabricating a CMOS transistor according to another preferred embodiment of the present invention.

10. . . Base

12. . . First transistor region

14. . . Second transistor region

16. . . Shallow trench isolation

18. . . First gate

20. . . Second gate

22, 24. . . Source/bungee area

26, 28. . . Dielectric layer

30, 32. . . Side wall

40. . . First strain channel

42. . . Second strain channel

33. . . First conductivity type transistor

35. . . Second conductivity type transistor

Claims (20)

A method of fabricating a complementary MOS transistor, the complementary MOS semiconductor system formed on a substrate, the substrate comprising a first gate and a first source/drain region a transistor region, a second gate region having a second gate and a second source/drain region, and an insulator between the first transistor region and the second transistor region, the first An optoelectronic region is used to form a first conductivity type of transistor, and the second transistor region is used to form a second conductivity type of transistor, the method comprising: only the first source Performing a first amorphous deuteration process in the pole/polar region; forming a first stress layer covering the first gate and the first source/drain region; performing a first tempering process, the first Forming a first strain channel in the substrate under the gate; removing the first stress layer; performing a second amorphous deuteration process in the second source/drain region; forming a second stress layer covering The second gate and the second source/drain region; performing a second tempering process, Formed in the substrate below the gate electrode a second strained silicon channel; and removing the second stress layer to form the complementary metal oxide semiconductor transistor. Making a complementary MOS semiconductor as described in Patent Application No. 1 A method of a transistor, wherein the first conductivity type is an N type and the second conductivity type is a P type. A method of fabricating a complementary MOS transistor as described in claim 2, wherein the first amorphous crystallization process comprises an ion implantation process using carbon ions. A method of fabricating a complementary MOS transistor as described in claim 3, wherein after the first tempering process, tantalum carbide is formed in the first source/drain region. A method of fabricating a complementary MOS transistor as described in claim 2, wherein the second amorphous crystallization process comprises an ion implantation process using ruthenium ions. A method of fabricating a complementary MOS transistor as described in claim 5, wherein after the second tempering process, bismuth telluride is formed in the second source/drain region. A method of fabricating a complementary MOS transistor as described in claim 2, wherein the first strained channel has a tensile strain. Making a complementary MOS semiconductor as described in Patent Application No. 2 A method of a transistor, wherein the second strained channel has a compressive strain. A method for fabricating a complementary MOS transistor as described in claim 1, wherein the first and second amorphous crystallization processes are all ion implantation processes using cesium ions or argon ions. A method of fabricating a complementary MOS transistor as described in claim 1 wherein the first tempering process is a low temperature tempering process. A method of fabricating a complementary MOS transistor as described in claim 1, wherein the second tempering process is a low temperature tempering process. A method for fabricating a complementary MOS transistor, the complementary MOS transistor comprising a first transistor region having a first gate and a first source/drain region, and a second gate a second transistor region of the pole and a second source/drain region and an insulator between the first transistor region and the second transistor region, the first transistor region being used to form a a first conductivity type transistor, and the second transistor region is used to form a second conductivity type transistor, the method comprising: the first source/drain region and the second source An amorphous deuteration process is performed in the polar/polar region; after the amorphous deuteration process, carbon is implanted in the first source/drain region; after the amorphous deuteration process, the second source/drain Area planting Forming a first stress layer on the surface of the first gate and the first source/drain region; forming a second stress layer on the surface of the second gate and the second source/drain region; Performing a tempering process to form a first strain channel and a second strain channel in the substrate under the first gate and the second gate; and removing the first stress layer and the A second stressor layer to form the complementary MOS transistor. A method of fabricating a complementary MOS transistor as described in claim 12, wherein the first conductivity type is an N type and the second conductivity type is a P type. A method of fabricating a complementary MOS transistor as described in claim 13 wherein the amorphous crystallization process comprises ion implantation using the carbon ions in the first source/drain region. A method of fabricating a complementary MOS transistor as described in claim 14, wherein after the tempering process, tantalum carbide is formed in the first source/drain region. Making a complementary gold-oxygen semiconductor guide as described in claim 13 A method of bulk crystal, wherein the amorphous deuteration process comprises ion implantation in the second source/drain region using erbium ions. A method of fabricating a complementary MOS transistor as described in claim 16, wherein after the tempering process, bismuth telluride is formed in the second source/drain region. A method of fabricating a complementary MOS transistor as described in claim 13 wherein the first strained channel has a tensile strain and the second strained channel has a compressive strain. A method of fabricating a complementary MOS transistor as described in claim 12, wherein the amorphous crystallization process comprises ion implantation in the first source/drain region using erbium ions or argon ions, and Second source/drain region. A method of fabricating a complementary MOS transistor as described in claim 12, wherein the tempering process is a low temperature tempering process.