TWI473156B - Method for selective formation of trench - Google Patents

Description

Method for selectively forming trenches METHOD FOR SELECTIVE FORMATION OF TRENCH

The present invention is directed to a method of selectively forming a trench. In particular, the present invention relates to a method of first changing the etching selectivity of a substrate using a dopant, thereby selectively forming a trench around the semiconductor device without masking.

In general, in the fabrication of semiconductor components, if it is desired to selectively form trenches at certain locations in the substrate, additional masks are needed to protect locations in the substrate that cannot be etched. Figures 1-3 illustrate the manner in which trenches are conventionally formed at certain locations in the substrate. As shown in Fig. 1, the substrate 101 is provided first. On the substrate 101, P-type semiconductor elements 110 and N-type semiconductor elements 120 located in different regions are respectively established in advance. Between the P-type semiconductor element 110 and the N-type semiconductor element 120, shallow trench isolation 130 is used to separate.

At this time, as shown in FIG. 2, if it is necessary to form a trench in the substrate 101 in the vicinity of the N-type semiconductor device 120, as described above, the P-type semiconductor device 110 is covered with a mask 140 such as a photoresist. The relevant regions are protected to protect the P-type semiconductor device 110 from the upcoming etching step. Next, as shown in FIG. 3, the intended etching step can be performed, for example, using the dry etching method to form the desired trench 150 in the substrate 101 near the N-type semiconductor device 120.

However, in order to protect the relevant region of the P-type semiconductor device 110 or the like by establishing the mask 140 on the relevant region of the P-type semiconductor device 110 or the like, it is necessary to additionally design a mask. The problem, however, is that the cost of reticle design and fabrication is extremely expensive. Therefore, additional mask requirements can place a heavy cost burden on semiconductor manufacturers. In addition, the use of dry etching has the advantage of a faster etching rate, which in turn makes the etching process less susceptible to uniform control. In view of this, it can be understood that there is still much room for improvement in the conventional manner in which it is desired to selectively form trenches at certain locations in the substrate.

The present invention thus proposes a novel method of selectively forming a trench. By using the method of the present invention, on the one hand, the step of establishing another mask on the adjacent region of the first semiconductor element can be dispensed with, and the etching process can be directly performed to form the desired trench in the substrate near the second semiconductor element. . On the other hand, the first semiconductor component is not substantially damaged by the etching process.

The present invention provides a method of selectively forming a trench. First, a substrate is provided. The substrate includes a first semiconductor component and the second semiconductor component is isolated from the shallow trench. The first semiconductor component has a dopant. The bismuth telluride structure can be located in the vicinity of the first semiconductor element as occasion demands. Secondly, wet etching is performed to selectively form a group of trenches in the substrate surrounding the second semiconductor component, selectively perform first source/drain ion implantation on the first semiconductor component, or selectively on the second The semiconductor component performs a second source/drain ion implantation. Preferably, the wet etching does not substantially affect the first semiconductor component. This group of ditches can also be used as a strain source for the substrate in the future.

In the method of the present invention, since the dopant is used to change the selection ratio of the substrate to the wet etching, the protection of the mask can be eliminated, the etching process can be directly performed, and the desired trench can be obtained in the substrate in the vicinity of the second semiconductor element. The reticle design omitting one step means that the production cost can be drastically reduced, which is one of the advantages of the present invention. Since the method of the present invention can produce an excellent etching selectivity ratio, the first semiconductor element is not substantially harmed by the lack of mask protection, but is another advantage of the present invention.

The present invention provides a method of selectively forming a trench in a substrate. 4-11 illustrate a method of selectively forming a trench in a substrate in accordance with a preferred embodiment of the present invention. Referring to Figure 4, a substrate 201 is first provided. Substrate 201 is typically a semiconductor substrate, such as a tantalum substrate. The substrate 201 includes at least a first semiconductor element 210, a second semiconductor element 220, and a shallow trench isolation between the first semiconductor element 210 and the second semiconductor element 220 for electrically insulating the first semiconductor element 210 from the second semiconductor element 220. 230. In the preferred embodiment, the first semiconductor component may be a P-type semiconductor component, such as a P-channel MOSFET (PMOS), and the second semiconductor component may be an N-type semiconductor component. However, it is not limited to this, such as N-channel MOSFETs (NMOS).

The first semiconductor element 210 has previously passed through the first ion implantation step such that the substrate 201 located near the first semiconductor element 210 has a dopant 211. However, the second semiconductor device 220 has not undergone this plasma implantation step, so that the substrate 201 in the vicinity of the second semiconductor device 220 has no dopant 211. Any suitable dopant can be selected for the first ion implantation step, such as a Group III or Group V ion. The first ion implantation step can be, for example, but not limited to, lightly doped (LDD) ion implantation or the like.

In a preferred embodiment of the present invention, a germanium telluride structure 212 is present in the vicinity of the first semiconductor device 210 having a P-type conductive dopant. The bismuth telluride structure 212 can be used to establish a compressive strained channel such that the gate channel under the first semiconductor component 210 has a compressive stress to enhance carrier mobility. Since the first semiconductor element 210 has previously passed through the first ion implantation step, the top end of the germanium telluride structure 212 also has a dopant 211.

Then, wet etching, first source/drain ion implantation, and second source/drain ion implantation are performed, respectively. The sequence of three operational steps, such as wet etching, first source/drain ion implantation, and second source/drain ion implantation, can be adjusted as needed. Several possible operational sequences are exemplified below, but are not limited thereto.

In the first embodiment of the present invention, referring to FIG. 5, in the unshielded state, wet etching is first performed to selectively form a group of trenches 240 in the substrate 201 around the second semiconductor element 220. The wet etching step can be performed using an etchant. For example, a wet etching step is performed using an alkaline etchant such as ammonia or an etchant of other chemical components. An advantage of using the wet etching method is that it is easier to uniformly control the etching process. At this time, the doping of the first semiconductor element 210, such as a PMOS element, may be SiGe epitaxial in-situ doping or shallow-dip doping.

As described above, since the substrate 201 in the vicinity of the first semiconductor element 210 has the dopant 211, the substrate 201 in the vicinity of the second semiconductor element 220 has no dopant 211, and the composition difference of the material causes the doping. The substrate 201 of the substance 211 or the germanium telluride structure 212 is extremely difficult to be etched, in other words, it can be considered that it is not substantially etched, but the substrate 201 in the vicinity of the second semiconductor element 220 is easily etched. Table 1 illustrates the etch rate of a substrate having a dopant and a substrate without a dopant.

In summary, the dopant 211 produces a sufficiently large etch selectivity ratio to the substrate 201 adjacent the first semiconductor component 210 and the substrate 201 adjacent the second semiconductor component 220. As such, the wet etching can form a set of trenches 240 in the substrate 201 around the second semiconductor component 220, but does not substantially affect the first semiconductor component 210 and the substrate 201 surrounding it.

The first source/drain ion implantation can then be performed on the first semiconductor device 210 and a second source/drain ion implantation on the second semiconductor device 220. The first source/drain ion implantation can be performed before or after the second source/drain ion implantation, as the case requires.

For example, if the first source/drain ion implantation is performed before the second source/drain ion implantation, please refer to FIG. 6 , and a mask 250 may be used to cover the relevant region of the second semiconductor device 220. The first source/drain ion implantation is performed. After the first source/drain ion implantation is completed, the mask 250 can be removed. Then, referring to FIG. 7, the mask 251 is used to cover the relevant region of the first semiconductor device 210, and then the second source/drain ion implantation is performed. After the second source/drain ion implantation is completed, the mask 251 can be removed. The mask 250 and the mask 251 may each be a patterned photoresist layer. The photoresist layer may be a positive photoresist or a negative photoresist depending on the exposure conditions. In addition, depending on the exposure wavelength, the photoresist layer may comprise a plurality of different organic materials, such as acrylate, vinyl ketone, polyhydroxystyrene (PHS), and the like. Those skilled in the art can select appropriate photoresist materials according to different needs.

In addition, if the first source/drain ion implantation is performed after the second source/drain ion implantation, referring to FIG. 7, the relevant region of the first semiconductor device 210 may be covered with the mask 251 first, A second source/drain ion implantation is performed. After the second source/drain ion implantation is completed, the mask 251 can be removed. Then, referring to FIG. 6, the first source/drain ion implantation is performed by covering the relevant region of the second semiconductor device 220 with the mask 250. After the first source/drain ion implantation is completed, the mask 250 can be removed.

In the second embodiment of the present invention, at least one of the first source/drain ion implantation and the second source/drain ion implantation is performed to perform wet etching in a maskless state. Thus, a set of trenches 240 can be selectively formed around the second semiconductor component 220. That is, as needed, the wet etching step can be performed after both the first source/drain ion implantation and the second source/drain ion implantation are completed. Alternatively, the wet etching step can be performed between the first source/drain ion implantation and the second source/drain ion implantation. At this time, the doping of the first semiconductor element 210, such as a PMOS element, may be source/drain doping.

For example, if the wet etching step is performed between the first source/drain ion implantation and the second source/drain ion implantation, refer to FIG. 8 to cover the second semiconductor element with a mask 250 first. In the relevant area of 220, the first source/drain ion implantation is performed. After the first source/drain ion implantation is completed, the mask 250 can be removed. Then, referring to FIG. 9, wet etching is performed to selectively form a set of trenches 240 around the second semiconductor component 220. The wet etching step can be performed using an alkaline etchant. For example, the wet etching step is performed using ammonia water as an alkaline etchant. Continuing, please refer to FIG. 10, and then cover the relevant region of the first semiconductor device 210 with a mask (not shown), and then perform second source/drain ion implantation. After the second source/drain ion implantation is completed, the mask can be removed (not shown). The mask can be a patterned layer of photoresist material.

Next, please refer to FIG. 11 to form the desired stress layer 260. For example, a stress memorization technique (SMT) is performed to establish a strained channel. Or forming at least one contact etch stop layer (CESL) covering the substrate 201 to provide a compressive stress or tensile stress corresponding to the first semiconductor component 210 of the substrate 201 and the second semiconductor component 220. . These techniques are well known to those skilled in the art and are therefore not described in detail herein.

It is to be noted that since the present invention utilizes the substrate 201 in the vicinity of the first semiconductor device 210 to have the dopant 211, the substrate 201 in the vicinity of the second semiconductor device 220 has no dopant 211, and the composition of the materials is different. A set of trenches 240 are selectively formed around the second semiconductor component 220 in a maskless manner using a wet etch step. Therefore, not only does the need for an additional mask, the process is simplified, the etching is uniform, and the wet etching step does not cause the problem of the dry etching trench destroying the lattice structure. As such, the present invention covers the stressor layer on the second semiconductor component 220, such as a contact etch stop layer (CESL) with tensile stress, so as to directly act on the channel position of the second semiconductor component 220, and more effectively provide the second The semiconductor component 220 forms a tensile strained channel to enhance carrier mobility.

In addition, please refer to FIG. 11, and if necessary, a metal telluride layer 270 may be formed around the first semiconductor element, that is, around the second semiconductor element, to reduce the contact resistance. These techniques are well known to those skilled in the art and are therefore not described in detail herein.

In the above preferred embodiment, the first semiconductor element is a P-type semiconductor element, and the second semiconductor element is described by taking an N-type semiconductor element as an example. However, not limited thereto, the present invention can also be applied to components of opposite conductivity type, that is, the N-type semiconductor device has a dopant, and is selectively formed around the P-type semiconductor device by maskless wet etching. The trenches are such that a compressive stress layer subsequently overlying the P-type semiconductor component, such as a contact etch stop layer (CESL) with tensile stress, acts directly on the channel location of the P-type semiconductor component to form a compressive strained channel. Channel). N-type semiconductor components can be used to create tensile strained channels using tantalum carbide epitaxy or other SMT methods.

Since the method of the present invention uses a dopant to change the selection ratio of the substrate to wet etching, the etching process can be directly performed without the mask protection, and the desired trench can be obtained in the substrate near the second semiconductor element. The mask design that omits one step means that the production cost can be greatly reduced. Since the method of the present invention can produce an excellent etching selectivity ratio, the first semiconductor element is not substantially damaged by the lack of protection of the mask.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

101. . . Substrate

110. . . P-type semiconductor component

120. . . N-type semiconductor component

130. . . Shallow trench isolation

140. . . Mask

150. . . ditch

201. . . Substrate

210. . . First semiconductor component

211. . . Doping

212. . .锗 矽 structure

220. . . Second semiconductor component

230. . . Shallow trench isolation

240. . . ditch

250. . . Mask

260. . . Stress layer

270. . . Metal telluride layer

Figures 1-3 illustrate the manner in which trenches are conventionally formed at certain locations in the substrate.

Figures 4-11 illustrate a method of selectively forming a trench in a substrate of the present invention.

201. . . Substrate

210. . . First semiconductor component

211. . . Doping

212. . .锗 矽 structure

220. . . Second semiconductor component

230. . . Shallow trench isolation

240. . . ditch

Claims (15)

A method of selectively forming a trench, comprising: providing a bare substrate, the substrate comprising a first semiconductor component and a second semiconductor component, wherein the first semiconductor component has a dopant, and the second semiconductor component does not Having a dopant; a wet etching of the substrate having the first semiconductor component and the second semiconductor component to selectively remove the substrate having the second semiconductor component without removing the first a substrate of the semiconductor component, and forming a set of trenches in the substrate having the second semiconductor component; selectively performing a first source/drain ion implantation on the first semiconductor component; and selectively pairing The second semiconductor component performs a second source/drain ion implantation. The method of claim 1, wherein the substrate further comprises a shallow trench isolation in the substrate for electrically isolating the first semiconductor component from the second semiconductor component. The method of claim 1, wherein the first semiconductor component is a P-type semiconductor component and the second semiconductor component is an N-type semiconductor component. The method of claim 1, wherein the wet etching is performed using an alkaline etchant. The method of claim 4, wherein the alkaline etchant is aqueous ammonia. The method of claim 1, wherein the first source/drain ion implantation and the second source/drain ion implantation are performed after the wet etching. The method of claim 1, wherein the wet etching is performed after the first source/drain ion implantation and the second source/drain ion implantation. The method of claim 1, wherein the wet etching is performed after the first source/drain ion implantation, and the second source/drain ion implantation is performed after the wet etching. The method of claim 1, further comprising: forming a germanium telluride (SiGe) layer having the dopant and surrounding the first semiconductor component to establish a compressive strained channel. The method of claim 1, further comprising: performing a stress memorization technique (SMT) to establish a strained channel. The method of claim 1, further comprising: forming a contact etch stop layer (CESL) covering the substrate to provide a strain force to the substrate. For example, the method of claim 1 further includes: A metal telluride layer is formed around the first semiconductor component. The method of claim 1, further comprising: forming a metal telluride layer around the second semiconductor element. The method of claim 1, wherein the second semiconductor component is covered with a mask to selectively perform the first source/drain ion implantation of the first semiconductor component. The method of claim 1 wherein a mask is used to cover the first semiconductor component to selectively perform the second source/drain ion implantation of the second semiconductor component.