TWI470930B - Multi-output decoding circuit - Google Patents

Description

Multiple output decoding circuit

The present invention relates to a decoder, and more particularly to a multiple output decoding circuit.

In the field of electronics, a mulitplexer can select one of a plurality of input signals as an output, and the application range is quite wide, such as channel selection, bus, and the like. The multiplexer can be composed of a plurality of switching elements whose switching elements are respectively controlled by control signals to form a specific conduction path, thereby achieving the function of selecting an input signal. A similar circuit architecture can also be used in a Resistor Strings Digital to Analog Converter as a Decoder to deliver a selected voltage to the output based on a digital signal.

The decoder can output one or more voltages to the circuits of the subsequent stage according to the digital signal, and its internal circuit architecture is similar to the combination of multiple multiplexers. Each multiplexer is responsible for outputting a set of voltages whose relationship to the output voltage, such as voltage or interval voltage, depends on the voltage sequence to which each multiplexer is connected.

It is worth noting that the number of switching elements required by the multiplexer will increase with the number of bits. For example, a 4-bit multiplexer requires 30 switching elements, and a 5-bit multiplexer requires 62 switching elements. If you need to output two adjacent voltages, you need two multiplexers, and the switching components used will multiply. Therefore, the conventional decoder has a large design area, high power consumption, and high cost.

The present invention provides a multi-output decoding circuit that can utilize a low-order selector to form a high-order selector, which generally uses fewer switching elements.

The invention provides a multi-output decoding circuit, which is suitable for selecting Y voltages from X voltages as an output according to an n-bit digital signal, wherein n, X, Y are positive integers, Y is smaller than X, and X is n bits. The decimal input value, the multi-output decoding circuit includes a first selection unit and a second selection unit. The first selection unit has a 2 ^m (nm) bit selector and (Y-1) adders, and the (Y-1) adders respectively according to a low byte of the n-bit digital signal Adjusting one of the n-bit digital signals to generate (Y-1) reference bytes, and the 2 ^m (nm) bit selectors are based on the reference bits and the original a high byte, selecting 2 ^m voltages as the output from the X voltages, wherein the high byte is a (nm) bit, the low byte is an m bit, m is a positive integer and less than n, and Y is less than or equal to 2 ^m . The second selection unit has Y m-bit selectors correspondingly coupled to the outputs of the (nm) bit selectors, according to the low-order tuples in the n-bit digital signal, from the selected 2 ^m Y voltages are selected as outputs, wherein the n-bit digital signal is composed of the high byte and the low byte.

The c-th adder of the adders generates the reference byte according to the sum of the high-order tuple and an integral term corresponding to the low-order tuple, and the sum of the product terms is expressed as follows:

F _(c) (b _m-1 , b _m-2 , b _m-3 ,...,b ₀ )=Σ m ((2 ^m - Y + c ), (2 ^m - Y + c +1) , (2 ^m - Y + c +2),...,(2 ^m -1));

Where c is a positive integer and less than or equal to (Y-1).

The invention further provides a multi-output decoding circuit, which is suitable for selecting Y voltages from X voltages as outputs according to n-bit digital signals, wherein n, X, Y are positive integers, Y is smaller than X, and X is n bits. The multi-output decoding circuit includes a first selection unit and a second selection unit. a first selection unit having (2 ^m + Y-1) (nm) bit selectors, wherein the (nm) bit selectors are based on a high byte of the n-bit digital signal, from the X (2 ^m + Y-1) voltages are selected as the output, wherein the high byte is a (nm) bit, m is a positive integer and less than n, and (2 ^m + Y-1) is less than X. The second selection unit has Y m-bit selectors correspondingly coupled to the outputs of the (nm) bit selectors, according to a low byte in the n-bit digital signal, selected from (2 ^m The Y voltages are selected as the output from the +Y-1) voltages, wherein the low byte is m bits, wherein the n-bit digital signal is composed of the high byte and the low byte.

In summary, the multi-output decoding circuit proposed by the present invention can simultaneously select a plurality of voltage outputs, and can use a lower bit selector to implement the function of the high bit selector, thereby achieving reduction in chip area cost and power consumption. efficacy.

The above described features and advantages of the present invention will be more apparent from the following description.

In the following, the invention will be described in detail by the embodiments of the invention, and the same reference numerals are used in the drawings.

(First Embodiment)

1 is a circuit diagram of a multi-output decoder according to a first embodiment of the present invention. The multi-output decoding circuit 100 can select Y voltages from the X voltages as an output according to the n-bit digital signal (b _n-1 b _n-2 b _n-3 ... b ₀ ), where n, X, and Y are A positive integer, Y is less than X, and X is a decimal value of n bits, for example, when n is equal to 10, X is equal to 1024. As shown in Figure 1, the X voltages include the input voltage V _r(0) ~ , Y voltages include V _out(1) ~ Y is represented by 2 ^p -i, where P and i are positive integers. The X voltages can be generated by a resistor string, but the invention is not limited.

In this embodiment, the n-bit digital signal is divided into a high byte (b _n-1 b _n-2 ... b _m ) of (nm) bits and a low byte of m bits (b _m-1 b _{m -2} ... b ₀ ), where m is a positive integer and less than n. The high byte (b _n-1 b _n-2 ... b _m ) refers to the higher (nm) bits of the n-bit digital signal and the lower byte (b _m-1 b _m-2 . ..b ₀ ) refers to the lower m bits of the n-bit digital signal. For example, if n is equal to 8, m is equal to 4, and the digit signal is 00001111, it indicates that the high byte is 0000 and the low byte is 1111. In the present embodiment, b _n-1 b _n-2 ... b _{0 is} a binary representation of the digital signal.

The multi-output decoding circuit 100 includes a first selection unit 110 and a second selection unit 120, and the first selection unit 110 is based on a high order tuple (b _n-1 b _n-2 ... b _m ) and a low bit of the n-bit digital signal. Tuple (b _m-1 b _m-2 ... b ₀ ), select 2 ^m voltages from X voltages V _s(1) ~ As an output. The second selection unit 120 selects Y voltages as the output from the selected 2 ^m voltages according to the low byte (b _m-1 b _m-2 ... b ₀ ). It is worth noting that Y is preferably less than or equal to 2 ^m .

Please refer to FIG. 2 at the same time, which illustrates an internal circuit diagram of the first selection unit 110. The first selection unit 110 has 2 ^m (nm) bit selectors 201 to 209 and (Y-1) adders 211 to 213, wherein the first to (Y-1)th adders 211 to 213 are used for adjustment. High-order tuples (b _n-1 b _n-2 ... b _m ) corresponding to the first to (Y-1)th (nm) bit selectors 201 to 203 to generate corresponding reference byte groups 251 ~253. In the present embodiment, Y is represented by 2 ^p + i, where P and i are positive integers. The first to (Y-1)th (nm) bit selectors 201 to 203 generate a voltage V _s(1) according to the reference bit groups 251 to 253. . Voltage V _s(1) ~ Is selected from the received X voltages V _r(0) ~ . In addition, the voltage V _s(1) ~ It means that the individual voltages differ only by one bit, or the adjacent partial voltages on the resistor string. Y-through ^of 2 ^m (nm) bit selector outputs a corresponding voltage generated in accordance with the high byte Therefore, the first to second ^m (nm) bit selectors generate 2 ^m according to the corresponding reference bytes 251 to 253 and the high byte (b _n-1 b _n-2 ... b _m ). Voltage V _s(1) ~ To the second selection unit 120.

The input terminals of the (nm) bit selectors 201 to 209 are coupled to the voltage V _r(0) in the order of the bit corresponding to the pin. Taking the first (nm) bit selector 201 as an example, the voltage coupled from the low bit to the high bit is V _r(0), . The sequence in which the pins of the remaining (nm) bit selectors are coupled is as shown in FIG. 2 and will not be described here. It is worth noting that in the same (nm) bit selector (such as 201), the voltages received by the respective pins are 2 ^m voltages, such as 00...00 receiving V _r(0) , and 00...01 receiving . Adjacent (nm) bit selectors (such as 201, 202), the voltages received by the opposite pins (same bits) are separated by a voltage, such as 00...00 of the (nm) bit selector 201 receiving V _r(0) , and 00...00 of the (nm) bit selector 202 receives _Vr(1) . Such a voltage arrangement allows the (nm) bit selectors 201-209 to output the voltages of adjacent bits, but the present invention does not limit this configuration. Each adder 211~213 will correspond to a set of adjustment values f ₍₁₎ ~ , this adjustment value f ₍₁₎ ~ It is related to the lower byte (b _m-1 b _m-2 ... b ₀ ) of the _n- bit digital signal (b _n-1 b _n-2 b _n-3 ... b ₀ ). The value of the adjustment value f ₍₁₎ ~f ₍₂ ^p _-i+1) is 0 or 1, which corresponds to an adjustment value corresponding to the lower byte (b _m-1 b _m-2 ... b ₀ ) The formula for the adjustment value is as follows:

F _(c) (b _m-1 , b _m-2 , b _m-3 ,...,b ₀ )=Σ m ((2 ^m - Y + c ), (2 ^m - Y + c +1) , (2 ^m - Y + c +2),...,(2 ^m -1));

C denotes the order of the adders 211 to 213, for example, the first adder 211, and c is equal to 1. The above formula of the adjustment value can be generated by the truth table of the voltage receiving order of the low byte (b _m-1 b _m-2 ... b ₀ ) and (nm) bit selectors 201 to 209.

The second selection unit 120 selects Y voltages as the output from the 2 ^m voltages output by the first selection unit 110 according to the low byte (b _m-1 b _m-2 ... b ₀ ). The second selection unit 120 has Y m-bit selectors, as shown in FIG. 3, which shows an internal circuit diagram of the second selection unit 120 of the first embodiment of the present invention. The second selection unit 120 includes Y m-bit selectors 311 319 319 each having an output terminal for outputting a voltage V _out(1) ~ . Voltage V _out(1) ~ It is selected from the output of (nm) bit selectors 201-209. Each of the m-bit selectors 311-319 corresponds to the output voltage of the (nm) bit selectors 201-209, and the coupling relationship is as shown in FIG.

For example, the m-bit selector 311 has 2 ^m inputs corresponding to the lower bytes of the m-bits (b _m-1 b _m-2 ... b ₀ ), and the 2 ^m inputs are respectively coupled The voltage V _s(1) connected to the (nm) bit selectors 201 to 209 ~ . The input terminals of the m-bit selector 312 are respectively coupled to the voltage V _s(2) ~ , V _s(1) . The voltage sequence to which the m-bit selector 312 is coupled differs from the m-bit selector 311 by one bit. By analogy, the m-bit selector 313 and the m-bit selector 312 also differ by one bit. Such a coupling sequence allows the m-bit selectors 311-319 to output Y adjacent voltages V _out(1) ~ . Similarly, adjusting the voltage sequence or the arrangement of the input terminals of the m-bit selectors 311-319 can change the voltage order of the output. After the description of the above embodiments, those skilled in the art should be able to infer other embodiments, and no further details are provided herein.

In addition, since the voltages received by the adjacent m-bit selectors 311-319 differ only by one bit, the outputs of the same (nm) bit selectors 201-209 are coupled to a plurality of m-bits. The 311-319, for example V _s(1), is coupled to the m-bit selectors 311, 312. The above (nm) bit selectors 201 to 209 and the m bit selectors 311 to 319 can be realized by a multi-to-one multiplexer whose function is to select one of the received voltages and output according to the digital signal.

(Second embodiment)

The multiple output decoding circuit 100 in the first embodiment described above may have different embodiments. In FIG. 2, the functions of the adders 211 to 213 are such that the same (nm) bit selectors 201 to 209 can be selected differently according to different lower bytes (b _m-1 b _m-2 ... b ₀ ). The voltage is output to the corresponding m-bit selectors 311 to 319. In other words, the number of (nm) bit selectors used can be reduced by the adders 211 to 213 to reduce the overall number of switching elements. The present invention can also directly use more than one selector to generate the input voltage required by the m-bit selectors 311-319. Referring to FIG. 4, an internal circuit diagram of a first selection unit according to a second embodiment of the present invention is shown. The first selection unit 410 includes (2 ^m + Y-1) (nm) bit selectors 411 to 419, wherein the receiving ends of the first to second ^m (nm) bit selectors 411 to 413 are coupled At voltage V _r(0) ~ The partial voltage in the voltage is 2 ^m bits. Taking the first (nm) bit selector 411 as an example, the voltage sequence coupled to the receiving end is V _r(0) . ,..., . Please refer to FIG. 4 for the coupling order of the receiving ends of the individual (nm) bit selectors, and no further details are provided herein.

The (nm) bit selectors 411 to 419 are used to output (2 ^m + Y-1) voltages, including V _s(1) ~ With V _s ' _(I) ~ , where Y is equal to 2p-i. In addition, it is worth noting that since X is equal to 2n, the maximum bit voltage is Therefore, the voltage number to which the (nm) bit selectors 411 to 419 are coupled exceeds The part can be considered as floating, such as .

Corresponding to the adjustment of the circuit of the first selection unit 410, the circuit adjustment of the second selection unit 420 is as shown in FIG. 5, which shows an internal circuit diagram of the second selection unit 420 of the second embodiment of the present invention. The second selection unit 420 includes Y m-bit selectors 521-529, which respectively select a voltage output according to the lower byte (b _m-1 b _m-2 ... b ₀ ) to generate Y voltages V _{out (0 )} ~ . The receiving ends of the Y m-bit selectors 521 to 529 are respectively coupled to the output ends of the (nm) bit selectors 411 to 419 to receive the voltage V _s(1) ~ With V _s ' ₍₁₎ ~ . Taking the m-bit selector 521 as an example, it is coupled to the voltage V _s(1) ~ , individual m bit selectors 521~529 and voltage V _s(1) ~ With V _s ' ₍₁₎ ~ The coupling relationship is shown in FIG. 5 and will not be described here.

m bit selectors 521~529 and voltage V _s(1) ~ , V _s ' ₍₁₎ ~ The coupling sequence determines the output voltage V _out(0) ~ , which can be determined according to design needs. Taking FIG. 5 as an example, the m-bit selectors 521 to 529 output Y adjacent voltages. After the description of the above embodiments, those skilled in the art should be able to infer other embodiments, and no further details are provided herein.

(Third embodiment)

Next, the technical means of the present invention will be described by taking a 4-bit input voltage and a multi-output decoding circuit that generates two adjacent voltages as an example. The 4-bit input voltage can be generated by a series resistor string, as shown in Figure 6A, which shows a resistor string that produces an input voltage. The resistor string 601 includes 17 series resistors R which can be used to generate 16 divided voltages V _r(0) ~ V _r(15) . It is worth noting that the manner in which the partial pressures V _r(0) ~ V _r(15) are generated is not limited to FIG. 6A.

Please refer to FIG. 6B and FIG. 6C simultaneously, which illustrate schematic diagrams of selector configurations of the first selection unit and the second selection unit. In this embodiment, the first selection unit 610 of the multi-output decoding circuit uses the 2-bit selector to perform voltage selection in the first stage, and the second selection unit 620 also uses the 2-bit selector to perform the voltage in the second stage. Select. That is, Y is equal to 2, m is equal to 2, n is equal to 4, and X is equal to 16. In this embodiment, the second selection unit has two 2-bit selectors 621, 622 that output adjacent voltages VH, VL according to the lower byte b ₁ b ₀ . The voltages VH and VL need to be adjacent to one bit. For example, when the low byte b ₁ b ₀ is 11, the voltage VL is V _r(3) and the voltage VH is V _r(4) . In order to meet the output requirements of the 2-bit selectors 621, 622, the voltage sequence to which the input terminals are coupled must be as shown in FIG. 6B.

The first selection unit generates the voltage sequence required by the 2-bit selectors 621, 622 based on the high byte b ₃ b ₂ . Referring to FIG. 6B, two 2-bit selectors 621, 622 require eight voltage sequences, which can be directly implemented by eight 2-bit selectors. However, it can be found from FIG. 6B that some of the voltage sequences are the same, such as the voltage sequence corresponding to the 01, 10, 11 bit in the 2-bit selector 621 and the 00 in the 2-bit selector 622. The voltage sequences corresponding to 01 and 10 are the same. Thus, the first selection unit can be implemented by five 2-bit selectors, ie 2 ^m + Y-1 2-bit selectors, m equals 2, Y equals 3.

Referring to 6C, the first selection unit 620 includes five two yuan selectors 611 to 615, respectively, a voltage _{V s (1) ~ V s} (4) and V _{s' (The} high byte b ₃ b _{2 1)} . The 2-bit selectors 611-615 are required to form the 2-bit selectors 621, 622 according to the voltages V _s(1) ~ V _s(4) and V _s ' ₍₁ ) output by the high-order tuple b ₃ b ₂ . Voltage sequence.

The above-described circuits of FIGS. 6B and 6C are completed by the technical means of the second embodiment described above. It should be noted that the number of output voltages (Y), the bits (nm) of the selector used by the first selection unit 610, and the bits (m) of the selector used by the second selection unit 620 can be designed according to the design requirements. However, this embodiment is not limited. The designer can determine the corresponding voltage sequence by first determining the number of bits required by the second selection unit 620 and the number of voltages to be output. The desired output voltage can then be obtained by using the selector in the first selection unit 610 to generate the desired voltage sequence.

(Fourth embodiment)

Since the voltage sequence corresponding to the voltage V _s(1) and V _s ' ₍₁₎ differs by only one bit, the 2-bit selectors 611 and 615 can be realized by the 2-bit selector 611 and an adder. As can be seen from FIG. 6B, when the low byte b ₁ b ₀ is 11, the voltage sequence is one bit different from b ₁ b ₀ when it is 00, so as long as the low byte b ₁ b ₀ is 11, 2 bits are used. The high byte b ₃ b ₂ corresponding to the meta selector 611 plus one can cause the 2-bit selector 611 to output the voltages V _s(1) and V _s ' ₍₁₎ . Referring to FIG. 6D, an internal circuit diagram of a first selection unit according to a fourth embodiment of the present invention is shown. The first selection unit can be implemented by four 2-bit selectors 611-614 and an adder 602. The adder 601 is coupled to the 2-bit selector 611, and adds an adjustment value f=b ₁ b ₀ to the adjustment high-order tuple. b ₃ b ₂ to generate a reference byte. The adjustment value f = b ₁ b ₀ can be generated via a truth table calculation. After the description of the above embodiments, those skilled in the art should be able to infer the calculation manner, and no further details are provided herein.

(Fifth Embodiment)

Similarly, the present invention can also implement a multi-output decoding circuit having two outputs by using a 1-bit selector and a 3-bit selector, that is, n is equal to 4, m is equal to 1, Y is equal to 2, and X is equal to 16. The 4-bit partial pressure of Fig. 6A is also taken as an example. Referring to FIG. 7A and FIG. 7B, FIG. 7 is a schematic diagram showing internal circuits of a first selection unit and a second selection unit according to a fifth embodiment of the present invention. The second selection unit 720 includes two 1-bit selectors 721, 722 coupled to the voltage sequence as shown in FIG. 7A. 1 yuan selector 721, 722 can be produced in accordance with the digital signal b low ₃ b ₂ b ₁ b ₀ b ₀ tuples two adjacent output voltages VH, VL, the voltage VH, VL is selected from the resistor string 601 Voltage V _r(0) ~V _r(15) . First selection unit 710 includes selectors 711 to 3 yuan 713 for generating a voltage _{V s (1), V s} (2) and V _{s' (1)} to the selectors 721, 722 1 yuan.

The overall multi-output decoding circuit 700 is shown in FIG. 7C, which is a schematic diagram of a multi-output decoding circuit 700 according to a fifth embodiment of the present invention. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

(Sixth embodiment)

The 3-bit selectors 711 and 713 in FIG. 7B above may be implemented by a 3-bit selector 711 plus an adder. Referring to FIG. 8, the 3-bit selector 711 is substituted for the 3-bit selector 711. , 713 circuit diagram. The adder 810 will be high digital signal b ₃ b ₂ b ₁ b ₀ tuple b ₃ b ₂ b ₁ f = b and the adjustment value of the adder _0. That is, when b ₀ is equal to 1, the 3-bit selector 711 adds a bit output to generate the voltage V _s ' ₍₁₎ . The circuits of the remaining 3-bit selector 712 and second selection unit 720 are the same as in the fifth embodiment described above. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

In addition, it is to be noted that the coupling relationship between the above elements includes a direct or indirect electrical connection as long as the required electrical voltage transfer function can be achieved, and the invention is not limited. The technical means in the above embodiments may be combined or used alone, and the components may be added, removed, adjusted or replaced according to their functions and design requirements, and the invention is not limited. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

In summary, the present invention utilizes a lower bit selector to implement the function of the high bit selector, and can simultaneously select a plurality of voltages to achieve the effect of reducing the overall number of switches and area cost.

Although the preferred embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and any one of ordinary skill in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention should be determined by the scope of the appended claims.

100. . . Multiple output decoding circuit

110. . . First selection unit

120. . . Second selection unit

201~209. . . (n-m) bit selector

211~213. . . Adder

251~253. . . Reference byte

311~319. . . m bit selector

410. . . First selection unit

411~419. . . (n-m) bit selector

420. . . Second selection unit

521~529. . . m bit selector

601. . . Resistor string

602. . . Adder

610. . . First selection unit

620. . . Second selection unit

611~615. . . 2-bit selector

621, 622. . . 2-bit selector

700. . . Multiple output decoding circuit

710. . . First selection unit

711~713. . . 3-bit selector

720. . . Second selection unit

721, 722. . . 1-bit selector

810. . . Adder

V _r(0) ~ , V _s ' ₍₁₎ ~ . . . Voltage

V _out(1) ~ , V _s(1) ~ . . . Voltage

b _n-1 b _n-2 ...b ₀ . . . Digital signal

b _n-1 b _n-2 ... b _m . . . High byte

b _m-1 b _m-2 ...b ₀ . . . Low byte

f, f ₍₁₎ ~ . . . Adjustment value

R. . . resistance

VH, VL. . . Voltage

1 is a circuit diagram of a multi-output decoder according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of an internal circuit of the first selection unit 110.

FIG. 3 is a schematic diagram showing the internal circuit of the second selection unit 120 according to the first embodiment of the present invention.

4 is a schematic diagram of an internal circuit of a first selection unit according to a second embodiment of the present invention.

FIG. 5 is a schematic diagram of an internal circuit of a second selection unit 420 according to a second embodiment of the present invention.

FIG. 6A is a schematic diagram of a resistor string that generates an input voltage.

6B and 6C are schematic diagrams showing the configuration of selectors of the first selection unit and the second selection unit.

FIG. 6D is a schematic diagram showing the internal circuit of the first selection unit according to the fourth embodiment of the present invention.

7A and 7B are schematic diagrams showing internal circuits of a first selection unit and a second selection unit according to a fifth embodiment of the present invention.

FIG. 7C is a schematic diagram of a multiple output decoding circuit 700 according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram showing the replacement of the 3-bit selectors 711 and 713 by the 3-bit selector 711.

100. . . Multiple output decoding circuit

110. . . First selection unit

120. . . Second selection unit

V _r(0) ~ . . . Voltage

V _out(1) ~ , V _s(1) ~ . . . Voltage

b _n-1 b _n-2 ...b ₀ . . . Digital signal

b _n-1 b _n-2 ... b _m . . . High byte

Claims (10)

A multi-output decoding circuit is suitable for selecting Y voltages from X voltages as an output according to an n-bit digital signal, wherein n, X, and Y are positive integers, Y is smaller than X, and X is a decimal value of n bits. The multi-output decoding circuit includes: a first selection unit having 2 ^m (nm) bit selectors and (Y-1) adders, wherein the (Y-1) adders are respectively according to the n A low byte of the bit digit signal adjusts a high byte of the n-bit digital signal to generate (Y-1) reference bytes, and the 2 ^m (nm) bit selectors are The reference byte and the original high byte select 2 ^m voltages as the output from the X voltages, wherein the high byte is a (nm) bit, the low byte is an m bit, and m is a positive integer and less than n, Y is less than or equal to 2 ^m ; and a second selection unit having Y m-bit selectors correspondingly coupled to the outputs of the (nm) bit selectors, according to the n-bits the low byte of the digital signal, the voltage ^of 2 ^m from the selected voltage as an output select Y, wherein the n-bit digital signal by the Department of the upper and the lower tuple Group composition. The multi-output decoding circuit of claim 1, wherein the voltage sequence to which the (n-m) bit selector is coupled is associated with the corresponding m-bit selector. The multi-output decoding circuit of claim 1, wherein each of the m-bit selectors is coupled to the (nm) bit selectors, and according to the low-order tuples, respectively The output of one of the (nm) bit selectors is selected as an output, wherein the number of m-bit selectors coupled to the outputs of the (nm) bit selectors exceeds one. The multi-output decoding circuit of claim 1, wherein X is equal to 1024 when n is equal to 10. The multi-output decoding circuit of claim 1, wherein the c-th adder of the adders generates the reference byte according to the high-order tuple and an adjustment value corresponding to the low-order tuple. The adjustment value is expressed as follows: F _(c) (b _m-1 , b _m-2 , b _m-3 , ..., b ₀ ) = Σ m ((2 ^m - Y + c ), (2 ^m - Y + c +1), (2 ^m - Y + c + 2), ..., (2 ^m -1)); wherein c is a positive integer and less than or equal to (Y-1). The multi-output decoding circuit of claim 5, wherein the first to (Y-1)th (nm) bit selectors of the (nm) bit selectors are based on the reference bits group, X voltages respectively from the selected voltage as an output, the first to the second ^of 2 ^m Y (nm) bit selector is based on the high bytes, respectively, from the X voltages selected as a voltage output. A multi-output decoding circuit is suitable for selecting Y voltages from X voltages as an output according to an n-bit digital signal, wherein n, X, and Y are positive integers, Y is smaller than X, and X is a decimal value of n bits. The multi-output decoding circuit includes: a first selection unit having (2 ^m + Y-1) (nm) bit selectors, wherein the (nm) bit selectors are based on the n-bit digital signals a high byte, selecting (2 ^m + Y-1) voltages from the X voltages as outputs, wherein the high byte is a (nm) bit, m is a positive integer and less than n, (2 ^m + Y -1) is smaller than X; and a second selection unit having Y m-bit selectors correspondingly coupled to the outputs of the (nm) bit selectors, according to a low bit in the n-bit digital signal Group, selecting Y voltages as the output from the selected (2 ^m + Y-1) voltages, wherein the low byte is m bits, wherein the n-bit digital signal is from the high byte and the low bit The tuple is composed. The multi-output decoding circuit of claim 7, wherein the voltage sequence coupled to each of the (n-m) bit selectors is associated with a corresponding m-bit selector. The multi-output decoding circuit of claim 7, wherein each of the m-bit selectors is coupled to a 2 ^m (nm) bit selector of the (nm) bit selectors, and Selecting, according to the lower byte, an output of one of the corresponding (nm) bit selectors as an output, wherein a portion of the (nm) bit selectors are coupled with an m-bit selection The number of devices is more than one. The multi-output decoding circuit of claim 7, wherein when n is equal to 10, X is equal to 1024.