TWI470643B - Wordline driver for memory - Google Patents

Description

Word line driver for memory

The subject matter disclosed herein pertains to access memory, and more particularly to the operation of a word line driver.

For example, memory devices can be used in many types of electronic equipment, such as computers, cellular phones, PDAs, data loggers, gaming, and navigation devices. The ever-increasing demand for smaller and/or more capable electronic equipment can lead to the need for smaller, higher density memory devices that can address the lower boundary and atomic or molecular level electronic behavior associated with materials. The small semiconductor feature size of the approach. Thus, methods for increasing memory density in addition to reducing semiconductor feature size may involve, for example, new configurations, new circuit layouts, and/or new methods for operating memory components.

The phrase "an embodiment" or "an embodiment" as used throughout the specification means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the claimed subject matter. . Thus, the phrase "in an embodiment" or "an embodiment" In addition, certain features, structures, or characteristics may be combined in one or more embodiments.

In one embodiment, the process of driving one of the word lines in a memory array can involve a word line driver incorporating a specific combination of one of a complementary metal oxide semiconductor (CMOS) transistor and one or more resistors. . For example, one or more N-channel metal oxide semiconductor field effect (NMOS) transistors can be used to perform the pull-up process, while one or more resistors can be used to perform a pull-up process. The word line driver can provide benefits including one of the memory devices occupied by a word line driver compared to the area of a full CMOS transistor word line device (eg, sans resistors) The area is reduced. This savings in area can be achieved without loss of performance. For example, circuitry for column and row decoding and/or word line driving in phase change memory (PCM) or NOR flash memory can occupy approximately one-third of the area occupied by one of the arrays of memory. . This ratio of occupied area may depend, at least in part, on the desired performance of the memory. Embodiments set forth herein may allow for the reduction of this ratio of memory areas allocated to column decode and/or word line drive functions. Of course, this benefit is only an example, and the claimed subject matter is not limited thereto.

In a particular embodiment, a memory device can include a memory cell that can address one of the memory cell arrays via a word line, the word line can correspond to a column of the memory cell array. A memory device can also include a series of circuit elements, referred to herein as a pull-up pull-down (PUPD) string, to select or deselect a word line of a memory cell array. The PUPD string can be electrically connected between a word line and a current sink to select the word line under the pull transistor, and electrically connected between the word line and a voltage source to deselect the word. One or more pull-up resistors on the line. These pull up resistors can be connected in series to the pull down transistor, as explained in further detail below. In a particular embodiment, one or more of the pull-up resistors can include a germanium diffusion on or near one of the edges of one of the memory cell arrays. For example, the germanium diffuser can comprise one of the n-type materials implanted in a substrate. The pull-up resistor including the germanium diffusion portion may be located on or near one of the word lines of the base of the memory cell extending into a memory cell array. Of course, the claimed subject matter is not limited to such details as one of the PUPD strings set forth in the above examples.

In another particular embodiment, a memory device can further include an additional transistor to inject current into a PUPD string between two consecutive pull-down transistors. This configuration may allow a word line to be deselected at a rate faster than that performed without this injected current, as explained in detail below. In a particular embodiment, an inverter can be electrically connected between the base of one of the two successive pull-down transistors and one of the bases of the additional transistor, but the claimed subject matter is not limited. herein.

1 is a schematic circuit diagram of a word line driver 100 incorporating a pull-up and pull-down CMOS transistor to deselect and select one word line 105 of a memory cell array (not shown), respectively, in accordance with an embodiment. For example, word line driver 100 can include a power supply 135 node connected to one or more parallel P-channel metal oxide semiconductor field effect (PMOS) transistors 110, 112, and 114, a P-channel metal oxide semiconductor field effect Crystals 110, 112, and 114 are coupled to one or more NMOS transistors 120, 122, and 124, which are coupled to ground or other low voltage 130. In one embodiment, column decode gate signal L1X can be applied to both PMOS 110 and NMOS 120, column decode gate signal L2X can be applied to both PMOS 112 and NMOS 114, and the column decode gate can be applied. Signal L3X is applied to both PMOS 114 and NMOS 124. Therefore, depending on one of the values of L1X, L2X, and L3X, the word line WL can be pulled up or pulled down to deselect or select the word line.

2 is a schematic circuit diagram of a word line driver 200 incorporating a pull-up portion and a pull-down portion to deselect and select one of the word lines 205 of a memory cell array (not shown), respectively, in accordance with an embodiment. For example, word line driver 200 can include a power supply 235 node connected to one of PUPD strings including one of pull-up resistors 210 in series with one or more NMOS transistors 220, 222, and 224, NMOS transistors 220, 222 And 224 is connected to ground or other low voltage 230. In one embodiment, the column decode gate signal L1X can be applied to the NMOS 220, the column decode gate signal L2X can be applied to the NMOS 214, and the column decode gate signal L3X can be applied to the NMOS 224. Therefore, depending on one of the values of L1X, L2X, and L3X, the word line WL can be pulled up or pulled down to deselect or select the word line. As will be explained in more detail below, pull-up resistor 210 can be implemented using a germanium diffusion on one of the edges of a memory array. Of course, such details of a word line driver are merely examples, and the claimed subject matter is not limited thereto.

3 is a schematic circuit diagram of one of the word line drivers applied to a portion of a memory array 340, in accordance with an embodiment. Memory array 340 can include columns and rows of memory cells 345. As explained below, individual rows may correspond to bit lines. The individual columns of word lines 335 corresponding to the memory cells can be selected or deselected based at least in part on one of the voltage levels of the word lines established by PUPD string 320. In a particular embodiment, the individual memory unit 345 can include a selector transistor 350 coupled to a storage unit 360, which can include, for example, a PCM unit, a NOR flash memory unit, or Other types of storage units. For example, the plurality of memory cells 345 that are coupled to one of the bases of the respective selector transistors 350 can include word lines 335. The plurality of memory cells 345 that are connected to one of the emitters of the respective selector transistors 350 may include a one-bit line 375. To select a particular memory cell 345 for a read and/or write operation, the selector transistor 350 corresponding to the particular memory cell can be turned on by pulling a voltage on the word line 335. On the other hand, to deselect a particular memory cell 345, the selector transistor 350 corresponding to the particular memory cell can be turned off by pulling a voltage on the word line 335. One of the voltages of this pull-down or pull-up word line may be performed by PUPD string 320, which may include word line driver 200 as shown in FIG. 2, but the claimed subject matter is not limited thereto. In particular, PUPD string 320 can include a pull up resistor 310. Node 325 can connect pull up resistor 310 with NMOS transistor string 330. A word line 335 of memory array 340 can be coupled to PUPD string 320 via node 325.

Although several configurations are possible, in a particular embodiment, NMOS transistor string 330 can be used to perform word line selection (pull down). The NMOS transistor string 330 can be selected to select various numbers of word lines in a hierarchical manner. In one embodiment, for example, one of the first column NMOS transistors receiving the column decode gate signal L1X can be turned on to select the word line 335. In particular, turning on one of the NMOS transistors in the NMOS transistor string 330 pulls down a voltage on the word line 335 (eg, to ground), thereby reducing a voltage on a respective base of the selector transistor 350, This results in the selection of a memory cell corresponding to word line 335. In a similar manner, for example, one of the receive column decode gate signals L2X can be turned on to select one of a plurality of word lines, such as 32 word lines. Also, for example, one of the receive column decode gate signals L3X can be turned on to select one of a plurality of word lines, such as 256 word lines. Of course, the number of word lines in a group can vary, and the claimed subject matter is not limited in this respect. In another implementation, word line or column decoding may involve selecting a word line using a combination of one of the decoded signals. For example, if an L1X NMOS transistor is turned on (for example, among 32 such NMOS transistors), an L2X NMOS transistor is turned on (for example, among 8 such NMOS transistors) and one is turned on. For L3X NMOS transistors (eg, among 8 such NMOS transistors), a unique word line can be selected (eg, among 2048 such word lines). However, more than one L1X, L2X or L3X NMOS transistor can be turned on at the same time, and in this case, more than one word line can be selected.

In a particular embodiment, pull-up resistor 310 can be used to perform word line deselection (pull-up). Turning off the NMOS transistor in the NMOS transistor string 330 can pull up a voltage on the word line 335 (eg, to a supply voltage VHX), thereby boosting a voltage on each of the respective bases of the selector transistor 350, thereby causing The memory cells corresponding to word line 335 are deselected. In one embodiment, a pull-up resistor (or an adjacent group of pull-up resistors) can deselect a word line. A resistance value of one of the pull-up resistors can be selected based at least in part on a desired performance speed and power consumption of a memory device. For example, word line driver 300 can include a pull up resistor having a relatively high resistance to provide a relatively low voltage during word line selection such that power consumption is relatively low. Alternatively, word line driver 300 can include a pull-up resistor having a relatively low resistance such that the inherent resistor-capacitor (RC) time constant is from a read/write operation to a subsequent read/write. The transition to the inbound operation is relatively fast. These wordline driver operating speed issues are discussed below. Of course, the details of the word line driver discussed above are merely examples, and the claimed subject matter is not limited thereto.

4 is a schematic circuit diagram of one of the word line drivers 400 including an additional transistor, in accordance with an embodiment. For example, the additional transistor 475 can include an NMOS transistor to inject current into the PUPD string 420 between two consecutive pull-down transistors 422 and 424. Including such an additional transistor to inject current can cause a word line to be deselected at a rate that is faster than would be performed without the injected current. For example, a pull up process can be performed while including an additional NMOS transistor. After a read operation, the two-stage column decoding via pull-down transistors 422 and 420 can be left unchanged for a specified time (eg, a few nanoseconds) while the third stage via one of pull-down transistors 424 can be turned off. Column decoding. Thus, the additional NMOS transistor can be turned on to allow one of the word lines 435 to pull up relatively quickly. The ability to add an injection current to improve the operating speed of the word line driver can be achieved by adding an NMOS transistor and an inverter (which can be implemented by a PMOS-NMOS transistor pair) to a third stage column decode. Thus, the area occupied by one of the memory devices by incorporating such a method to improve the operating speed can be relatively low compared to other methods, for example, which can involve more than one additional transistor.

In one embodiment, one of the bases of the additional transistor 475 can receive an electrical signal that is inverted relative to an electrical signal applied to one of the pull-down transistors 424 included in the PUPD string 420. Thus, if the applied signal is relatively high (eg, a logic high voltage), pull-down transistor 424 can be turned on to electrically connect word line 435 to ground node 480 (or other relative that includes a voltage sink) Low voltage node). Thus, pull-down transistor 424 can pull down one of the voltages of word line 435, while the inverted applied signal can turn off additional transistor 475 to electrically isolate word line 435 from a power supply voltage VHX. On the other hand, if the applied signal is relatively low (eg, a logic low voltage), the pull-down transistor 424 can be turned off to electrically isolate the word line 435 from the ground node 480 such that the pull-up resistor 410 can be pulled up. One of the word lines 435. At the same time, the applied signal can be turned on by the reverse phase to turn on the additional transistor 475 to electrically connect the word line 435 to the power supply voltage VHX so as to be performed at a rate lower than in the case where there is no such electrical connection to the power supply voltage VHX. The word rate 435 is deselected at a faster rate. Of course, such details of a word line driver are merely examples, and the claimed subject matter is not limited thereto.

FIG. 5 is a schematic circuit diagram of one of word line drivers 500 including an additional transistor in accordance with another embodiment. For example, such an additional transistor 575 can include an NMOS transistor to inject current into the PUPD string 520 between two consecutive pull-down transistors 522 and 524. Including such an additional transistor to inject current can cause a word line to be deselected at a rate that is faster than would be performed without the injected current. For example, the operation of this additional transistor can be similar to that described above for word line driver 400 in FIG. In one embodiment, for example, one of the bases of the additional transistor 575 can receive a global signal 590 provided by a memory controller (such as the memory controller 815 shown in FIG. 8). An electrical signal. This global signal can be applied to the base of the additional transistor 575 to selectively turn the additional transistor 575 on/off by coordination with respect to the time of the read/write operation of one or more columns of memory. For example, a pull up process can be performed after a read operation, as set forth above. In particular, the two-stage column decoding via pull-down transistors 520 and 522 can be left unchanged for a specified time (eg, a few nanoseconds) while the third stage column decoding via one of pull-down transistors 524 can be turned off. Thus, the additional NMOS transistor can be turned on via global signal 590 to allow one of word lines 535 to pull up relatively quickly. The ability to add an injection current can be achieved by adding an NMOS transistor to a third stage column decode to improve the operating speed of the word line driver. Thus, by incorporating such a method to improve the operating speed, the area occupied by one of the memory devices can be compared to, for example, other methods that can involve more than one additional transistor and/or an inverter. Relatively low. Of course, such details of a word line driver are merely examples, and the claimed subject matter is not limited thereto.

Figure 6 is a schematic circuit diagram of one of a word line driver and a memory array in accordance with an embodiment and Figure 7 is a cross-sectional view thereof. For example, a PUPD string 620 can be coupled to one of the memory cells 645 at node 655, which can include a storage unit 660 and a selector transistor 650. The PUPD string 620 can include a series of transistors 630 connected to one of the pull-up resistors 610 on a substrate 795 at or near one edge of the memory cell array 640/740. In one embodiment, one of the edges of the memory cell array 640 can include a start region that extends to one of the base lines 635 of the base of the selector transistor 650. Word line 635 can be coupled to a power supply voltage VHX via pull-up resistor 610.

As shown in FIG. 7, the storage unit 760 can be located on the p-emitter diffusion portion 763 and an n-base diffusion portion 765 forming part of a selector transistor 650/750. A metal line 788 can include a node 655/755 that electrically connects the pull up resistor 610/710 to the pull down transistor 650/750. In one embodiment, the n-base diffusion 765 can be fabricated in the same process as one of the pull-up resistors 610/710. For example, an n-type semiconductor material can be implanted and/or deposited on a substrate 795 to create an n-base diffusion 765, while at substantially the same time, an n-type semiconductor material is implanted to create a pull-up resistor. 610/710. Thus, a single mask can be used to form at least a portion of one of the memory cell arrays 660/760 and pull-up resistors 610/710. This portion, for example, can include a base of a bipolar junction transistor (BJT) selector. At the same time, a p-type semiconductor material can be implanted and/or deposited on substrate 795 to form a p-substrate that can comprise one of the collectors of one of selector transistors 650/750. In one embodiment, metal line 788 can be electrically connected to a series of transistors, such as transistor 630 shown in FIG. The n-base diffusion 765 including a word line can be electrically connected to a power supply voltage VHX via pull-up resistors 610/710. Of course, such details of a word line driver are merely examples, and the claimed subject matter is not limited thereto.

8 is a schematic diagram of a computing system and a memory device in accordance with an embodiment. Such a computing device can include, for example, one or more processors to execute an application and/or other code. For example, the memory device 810 can include the memory array 340 shown in FIG. A computing device 804 can represent any device, appliance, or machine that can be configurable to manage the memory device 810. The memory device 810 can include a memory controller 815 and a memory 822. By way of example and not limitation, computing device 804 can comprise: one or more computing devices and/or platforms such as a desktop computer, a laptop computer, a workstation, a server device, or the like One or more personal computing or communication devices or appliances, such as, for example, a number of assistants, mobile communication devices, or the like; a computing system and/or associated service provider capabilities, such as, for example, a database or material Storage service provider/system; and/or any combination thereof.

It will be appreciated that all or a portion of the various devices shown in system 800 can be implemented using hardware, firmware, software, or any combination thereof, or otherwise include a hardware, a firmware, a soft body, or any combination thereof. Thus, by way of example and not limitation, computing device 804 can include at least one processing unit 820 and a host or memory controller 815 operatively coupled to memory 822 through a bus 840. Processing unit 820 represents one or more circuits configurable to perform at least a portion of a data calculation program or process. By way of example and not limitation, processing unit 820 may include one or more processors, controllers, microprocessors, microcontrollers, dedicated integrated circuits, digital signal processors, programmable logic devices, and field programmable Gate array and similar devices or any combination thereof. Processing unit 820 can include an operating system configured to communicate with memory controller 815. This operating system can, for example, generate commands to be sent to the memory controller 815 via the bus 840. These commands can include read and / or write commands. In response to a write command, for example, the memory controller 815 can provide a bias signal, such as to write information associated with the write command to one of the memory partition settings or reset Pulse (for example). In one embodiment, for example, the memory controller 815 can operate the memory device 810, wherein the processing unit 820 can load one or more applications and/or initiate a write command to the memory controller to provide a pair Access to the memory unit in memory device 810.

In one embodiment, a system can include: a memory controller for operating a memory device, wherein the memory device can include a memory unit that can address one of the memory cell arrays via a word line a PUPD string for selecting or deselecting the word line in response to an electronic signal generated by decoding a command. The PUPD can include an electrical connection between the word line and a voltage source to deselect a pull-up resistor of the word line and/or a series connection to a pull-up resistor in the PUPD string and electrically coupled to the word Between the line and a current sink to select the word line below the pull transistor. The system can further include a processor to load one or more applications and initiate commands to the memory controller to provide access to the memory cells in the array of memory cells.

Memory 822 represents any data storage facility. Memory 822 can include, for example, a primary memory 824 and/or an auxiliary memory 826. The primary memory 824 can include, for example, a random access memory, read only memory, and the like. Although illustrated in this example as being separate from processing unit 820, it should be understood that all or a portion of primary memory 824 may be provided within processing unit 820 or otherwise co-located/coupled with processing unit 820.

The auxiliary memory 826 can include, for example, the same or similar types of memory and/or one or more data storage devices or systems as the primary memory, such as, for example, a disk drive, a disk drive, a magnetic tape. Machine, a solid state memory disk drive, etc. In some embodiments, the auxiliary memory 826 can be operatively received by the computer readable medium 828 or can be otherwise configured to be coupled to the computer readable medium 828. Computer-readable medium 828 can include, for example, data, code, and/or instructions that can be carried by one or more of the devices in system 800 and/or one of the devices in system 800 Or any medium that has access to data, code, and/or instructions.

Computing device 804 can include, for example, an input/output 832. Input/output 832 represents one or more devices or features that may be configurable to accept or otherwise introduce human and/or machine inputs, and/or may be configurable to deliver or otherwise provide humans and/or Or the machine outputs one or more devices or features. By way of example and not limitation, the input/output device 832 can include an operationally configured display, speaker, keyboard, mouse, trackball, touch screen, data cartridge, and the like.

While the embodiment of the present invention has been illustrated and described, it will be understood by those skilled in the art that various modifications and alternatives can be made without departing from the claimed subject matter. . In addition, many modifications may be made to adapt a particular situation to the teachings of the claimed subject matter. Therefore, it is intended that the subject matter of the invention should not be

100. . . Word line driver

105. . . Word line

110. . . P-channel metal oxide semiconductor field effect transistor

112. . . P-channel metal oxide semiconductor field effect transistor

114. . . P-channel metal oxide semiconductor field effect transistor

120. . . N-channel metal oxide semiconductor field effect transistor

122. . . N-channel metal oxide semiconductor field effect transistor

124. . . N-channel metal oxide semiconductor field effect transistor

130. . . low voltage

135. . . power supply

200. . . Word line driver

205. . . Word line

210. . . Pull-up resistor

220. . . N-channel metal oxide semiconductor field effect transistor

222. . . N-channel metal oxide semiconductor field effect transistor

224. . . N-channel metal oxide semiconductor field effect transistor

230. . . low voltage

235. . . power supply

310. . . Pull-up resistor

320. . . Pull-up pull-down string

325. . . node

330. . . N-channel metal oxide semiconductor field effect transistor string

335. . . Word line

340. . . Memory array

345. . . Memory unit

350. . . Selector transistor

360. . . Storage unit

375. . . Bit line

400. . . Word line driver

410. . . Pull-up resistor

420. . . Pull-up pull-down string

422. . . Pull down transistor

424. . . Pull down transistor

435. . . Word line

475. . . Transistor

480. . . Ground node

500. . . Word line driver

520. . . Pull-up pull-down string

522. . . Pull down transistor

524. . . Pull down transistor

535. . . Word line

575. . . Transistor

590. . . Global signal

610. . . Pull-up resistor

620. . . Pull-up pull-down string

630. . . Transistor

635. . . Word line

640. . . Memory cell array

645. . . Memory unit

650. . . Selector transistor

655. . . node

660. . . Storage unit

710. . . Pull-up resistor

740. . . Memory cell array

750. . . Pull down transistor

755. . . node

760. . . Storage unit

763. . . P-emitter diffusion

765. . . N base diffusion

788. . . metal wires

795. . . Substrate

800. . . system

804. . . Computing device

810. . . Memory device

815. . . Memory controller

820. . . Processing unit

822. . . Memory

824. . . Main memory

826. . . Assisted memory

828. . . Computer readable medium

832. . . input Output

840. . . Busbar

VHX. . . Supply voltage

The non-limiting and non-exhaustive embodiments are described with reference to the following figures, wherein the same reference numerals refer to the same parts throughout the various figures unless otherwise indicated.

1 through 5 are schematic circuit diagrams of a word line driver in accordance with an embodiment.

6 is a schematic circuit diagram of one of a word line driver and a memory array, in accordance with an embodiment.

7 is a cross-sectional view of a portion of a word line driver and a memory array, in accordance with an embodiment.

8 is a schematic diagram of a computing system and a memory device in accordance with an embodiment.

100. . . Word line driver

105. . . Word line

110. . . P-channel metal oxide semiconductor field effect transistor

112. . . P-channel metal oxide semiconductor field effect transistor

114. . . P-channel metal oxide semiconductor field effect transistor

120. . . N-channel metal oxide semiconductor field effect transistor

122. . . N-channel metal oxide semiconductor field effect transistor

124. . . N-channel metal oxide semiconductor field effect transistor

130. . . low voltage

135. . . power supply

Claims (16)

A memory device comprising: a plurality of memory cells of a memory cell array, which are addressable via a word line; a pull-up pull-down string for selecting or deselecting the word line, the pull-up pull-down string The method includes: a pull-down transistor electrically connected between the word line and a current sink to select the word line; and one or more pull-up resistors electrically connected between the word line and a voltage source to cancel Selecting the word line, wherein the one or more pull-up resistors are connected in series to the pull-down transistors; and an additional transistor for use between successive ones of the pull-down transistors A current is injected into the pull-up pull-down string to deselect the word line at a rate that is faster than performing a deselection of the word line without the injected current. A memory device as claimed in claim 1, wherein the one or more pull-up resistors comprise a germanium diffusion portion on or near an edge of one of the memory cell arrays. The memory device of claim 2, wherein the germanium diffusion portion comprises one of n-type materials implanted in a germanium substrate. The memory device of claim 1, wherein the one or more pull-up resistors comprise a germanium diffusion portion at or near one of the word lines extending to a base of the memory cells. The memory device of claim 1, further comprising an electrical connection to the connection An inverter between one of the two pull-down transistors and one of the bases of the additional transistor. A memory device as claimed in claim 1, wherein the pull-down transistors comprise a plurality of NMOS transistors. A method for forming a memory device, the method comprising: forming a word line on a substrate to address memory cells of a memory cell array; and forming one or more pull-up resistors on the substrate, The one or more pull-up resistors are used to boost a voltage to deselect the word line; and a transistor is formed to inject current between two consecutive pull-down transistors connected in series to the one or more pull-up resistors The word line is deselected at a rate that is faster than the rate at which the word line is deselected without the injected current. The method of claim 7, further comprising forming the memory cell array and the one or more pull-up resistors at substantially the same time using an identical mask. The method of claim 7, wherein the one or more pull-up resistors are formed using a germanium diffusion. The method of claim 9, wherein the germanium diffusion comprises one of n-type materials implanted in the substrate. The method of claim 10, wherein the edge of one of the array of memory cells comprises one of the word lines extending to the bases of the memory cells. The method of claim 7, further comprising: An inverter is formed to electrically connect one of the bases of one of the two successive pull-down transistors to a base of one of the additional transistors. The method of claim 7, wherein the two consecutive pull-down transistors comprise an NMOS transistor. A computing system comprising: a memory controller for operating a memory device, the memory device comprising: a plurality of memory cells of a memory cell array, which are addressable via a word line; Pulling down a string for selecting or deselecting the word line in response to an electronic signal generated by decoding a command, wherein the pull-up string comprises electrically connecting between the word line and a voltage source Deselecting one or more pull-up resistors of the word line; a plurality of pull-down transistors connected in series to the one or more pull-up resistors in the pull-up pull-down string and electrically connected to the word line and a current Between the slots to select the word line; an additional transistor for injecting current into the pull-up string between successive ones of the pull-down transistors to deselect the rate at a rate a word line that is faster than performing a deselection of the word line without the injected current; and a processor for loading one or more applications and for initiating the command to the Memory controller Provide access to the memory cell array of those memory cells. The system of claim 14, wherein the pull-down transistors comprise NMOS Crystal. The system of claim 14, wherein the one or more pull-up resistors comprise a germanium diffusion on or near an edge of one of the memory cell arrays.