TWI469304B - Circuit layout structure and method to scale down ic layout - Google Patents

Description

Circuit layout structure and method for reducing integrated circuit layout

The present invention relates to a circuit layout structure and a method of reducing the layout of an integrated circuit. In particular, the present invention relates to a circuit layout structure in which the area line width is substantially different, and a method of reducing the integrated circuit layout without substantially affecting the electronic characteristics of the element.

In order to accommodate the largest number of semiconductor components over a limited wafer area to reduce manufacturing costs, those skilled in the art have come up with a variety of semiconductor methods to make the size of the components smaller and smaller and the density of components on the wafers larger. On the one hand, a faster operating speed can be obtained when the size of the component is reduced, and on the other hand, the operating energy consumption of the component can be reduced when the size of the component is reduced. Therefore, reducing the layout structure of the integrated circuit has become an important issue for those skilled in the art to camp.

In general, after the size of the component is reduced, the layout pattern of the integrated circuit is substantially changed. As a result, even if the size of the simple component is reduced, the integrated circuit layout pattern before the reduction is no longer applicable and must be re design. The design of an integrated circuit layout pattern is known to be a costly and time consuming preparation step.

In order to avoid various costs of redesigning the integrated circuit layout pattern, a method of directly reducing the original integrated circuit layout pattern to obtain an integrated circuit layout pattern of a desired reduced size is known. However, since the method of reducing the layout pattern of the original integrated circuit is to comprehensively reduce the size of all parts of the element, the size of the gate conductor layer is also simultaneously reduced. However, the operational characteristics of the component are closely related to the size of the gate conductor layer. The change in the size of the gate conductor layer means that the operational characteristics of the component are also changed at the same time. These changes are even deviated from the operational characteristics of the original integrated circuit and are no longer Use together.

Therefore, although the current method reduces the layout of the integrated circuit, it also substantially affects the electronic characteristics of the component, which may cause the new electronic characteristics of the component to be unsuitable. Therefore, there is a need for a method that can reduce the overall circuit layout without substantially affecting the electronic characteristics of the device.

SUMMARY OF THE INVENTION The present invention is directed to a circuit layout structure and a method of reducing the integrated circuit layout without substantially affecting the electronic characteristics of the device. With the method of the present invention, it is possible to reduce the size of the integrated circuit layout as the case may be, while maintaining the electronic characteristics before the component is shrunk.

The present invention first proposes a circuit layout structure. The circuit layout structure of the present invention includes a substrate including a first region and a second region, and a set of wires including a first wire and a second wire and passing through the first region and the second region. The first wire and the second wire have a variable gap, and respectively have a first region line width on the first region and a second region line width on the second region, and the first region line width The line width is substantially different from the second area. Since the line width of the first area is substantially different from the line width of the second area, the original electronic characteristics of the element can be maintained while reducing the necessary size of the element.

The present invention secondly proposes a method of reducing the overall circuit layout without substantially affecting the electronic characteristics of the device. First, a circuit layout is provided that includes a set of wires. The wire set includes a first wire and a second wire and passes through the first region and the second region. The first wire and the second wire respectively have a first region original line width, a first region original gap and a first region original pitch on the first region, and a second region original line width on the second region, The original spacing of the second region is the original spacing from the second region. Next, performing a reduction operation, so that the first wire and the second wire selectively have a first area reduction line width and a first area on the first area according to a first area rule and a second area rule respectively. The reduction gap and the first area are reduced in spacing, and further have a second area original line width, a second area reduction gap and a second area reduction pitch on the second area. Preferably, the first area reduction line width is substantially different from the second area original line width.

The present invention first provides a method of adjusting a predetermined pattern of an integrated circuit without substantially affecting the electronic characteristics of the formed device. 1 to 5 are diagrams showing a preferred embodiment of a method of reducing the integrated circuit layout of the present invention without substantially affecting the electronic characteristics of the device. First, as shown in FIG. 1, a circuit layout 100 predetermined to be formed on a semiconductor wafer is provided. The predetermined pattern in circuit layout 100 includes a set of wire patterns that can be stored in a database. The predetermined wire pattern 110, that is, the wire group 110, may include a first wire pattern 111 and a second wire pattern 112, which are simply referred to as a first wire 111 and a second wire 112.

The first wire 111 and the second wire 112 in the wire group 110 are respectively intended to pass through the first region 121 and the second region 122 on the semiconductor wafer. The first region 121 may be an insulating region, such as a shallow trench isolation (STI) region, a field oxide layer region, etc., and the second region 122 may be an active region, such as a metal oxide semiconductor (MOS) region, a component. Area, etc. When the first wire 111 and the second wire 112 pass through the second region 122, the first wire 111 and the second wire 112 located in the second region 122 can serve as a gate of a semiconductor component (not shown).

In FIG. 1 , the first wire 111 and the second wire 112 respectively have a first line original line width W1 and a first area original space before the selective reduction operation on the first region 121 . S1 is initially spaced from the first region by a pitch P1. In addition, the first wire 111 and the second wire 112 have a second region original line width W2, a second region original gap S2 and a second region original pitch P2 on the second region 122.

Line width, gap and spacing will satisfy the line width + gap = spacing relationship in any area. For example, if the pitch remains the same, as the line width becomes larger, the gap is reduced. For the convenience of the following description, the 0.18 μm process is taken as an example, and W1 is assumed to be 0.18 μm, S1 is 0.24 μm, P1 is 0.42 μm, W2 is 0.18 μm, S2 is 0.28 μm, and P2 is 0.46 μm. .

Next, a reduction operation is performed in order to selectively have the first wire 111 and the second wire 112 located in the first region 121 and the second region 122 to have appropriate sizes, respectively. For example, the circuit layout pattern 100 intended to be formed on the semiconductor wafer can be adjusted upon initial preparation of the reticle pattern, or subsequent optical proximity correction (OPC). On the one hand, the reduced size of the wire can reduce the area of the integrated circuit layout as a whole to increase the density of components on the wafer. On the other hand, the constant size of the wire can maintain the electronic characteristics before the component is reduced. The reduction operation for the first wire size and the second wire size may require the predetermined first area rule and the second area rule according to a case.

Next, the zoom-out operation is performed according to the predetermined first area rule and the second area rule. Therefore, the first wire 111 and the second wire 112 selectively have a first region reduction line width w1, a first region reduction gap s1 and a first region reduction pitch p1, and a second region 122 on the first region 121, respectively. There is a second region original line width W2, a second region reduction gap s2, and a second region reduction pitch p2. According to a preferred embodiment of the present invention, the first region reduction line width w1 and the second region original line width W2 may be substantially different. For example, the first region line width is smaller than the second region line width. Preferably, the first region reduction line width w1 is smaller than the second region original line width W2.

After the reduction operation, although the first region reduction line width w1 is thus smaller than the first region original line width W1, the gate size of the switching element operation characteristic, that is, corresponds to the first wire in the second region 122 The width of the second and the second wire, that is, the original line width W2 of the second region, is intentionally maintained, so that the electronic characteristics before the component is reduced can be maintained. For the convenience of explanation, This is explained by a reduction operation with a ratio of 90%, so w1 is 0.162 μm, s1 is 0.216 μm, p1 is 0.378 μm, W2 is 0.18 μm, s2 is 0.252 μm, and p2 is 0.414 μm.

In a first preferred embodiment of the present invention, the aforementioned reducing operation may include performing two sub-steps respectively: a preliminary reduction operation and an amplification operation. For example, first, as shown in FIG. 3, a preliminary reduction operation is performed. These preliminary reduction operations cause all line widths, gaps, and pitches of the first wire 111 and the second wire 112 to be reduced by a predetermined equal ratio, for example, 90%. Therefore, the first wire 111 and the second wire 112 selectively obtain the first region reduction line width w1, the first region reduction gap s1 on the first region 121, the first region reduction pitch p1, and the second region 122 A second area reduction line width w2 and a second area reduction pitch p2 are obtained.

Next, an enlargement operation is performed, as shown in FIG. 2, and the second region reduction line width w2 on the second region 122 is restored to the second region original line width W2, and thus the second region reduction gap s2 is obtained. .

In a second preferred embodiment of the present invention, the aforementioned reduction operation may include performing three sub-steps: a preliminary reduction operation, a preliminary enlargement operation, and a modification reduction operation. For example, first, as shown in FIG. 3, a preliminary reduction operation is performed. These preliminary reduction operations cause all line widths, gaps, and pitches of the first wire 111 and the second wire 112 to be reduced by a predetermined equal ratio, for example, 90%. Therefore, the first wire 111 and the second wire 112 selectively obtain the first region reduction line width w1, the first region reduction gap s1 on the first region 121, the first region reduction pitch p1, and the second region 122 A second area reduction line width w2 and a second area reduction pitch p2 are obtained.

Next, a preliminary amplification operation is performed. As shown in FIG. 4, the line widths of the first wire 111 and the second wire 112 in the wire group 110 are respectively restored to the original region width W1 of the first region and the original line width of the second region. W2. Please note that in this operation, the distance between the first wire 111 and the second wire 112 is not changed by the preliminary amplification operation, and is still maintained as p1 and p2.

Then, as shown in Fig. 2, a modification and reduction operation is performed. A modification and reduction operation is selectively performed on the first area 121, so that the first area reduction line width w1 and the first area reduction gap s1 are obtained. Similarly, in this operation, the distance between the first wire 111 and the second wire 112 is not changed by the modification reduction operation, and is still maintained as p1 and p2.

In summary, the circuit layout pattern 100 that is formed on the semiconductor wafer as in FIG. 1 is used, either by the method illustrated in the first preferred embodiment or the method in the second preferred embodiment, and finally As shown in FIG. 2, the first area reduction line width w1, the first area reduction gap s1, the first area reduction pitch p1, and the second area 122 are obtained on the second area 122. The original line width W2, the second area reduction gap s2, and the second area reduction pitch p2. Therefore, after the operation steps of the present invention, although the overall size of the wire group 110 is reduced to increase the component density on the wafer, the original original line width W2 in the second region maintains the electronic characteristics before the component is reduced. . At this point, the adjusted circuit layout pattern can be outputted onto a reticle to obtain a usable reticle.

In an embodiment of the present invention, as shown in FIG. 1, due to the wire set 110 The first region 121 and the second region 122 respectively have the same line width, so the wire group 110 may include at least one 45 degree turn angle in the first region 121. On the other hand, in another embodiment of the present invention, as shown in FIG. 5, the wire group 110 may include at least one 90 degree turn angle in the first region 121.

In a preferred embodiment of the invention, the set of wires 110 selectively has different line widths in the first region 121. For example, referring to FIG. 2, the first wire 111 and the second wire 112 may have an original line width W2 of a predetermined length L in the first region 121 adjacent to the second region 122. These predetermined lengths L may be between 1/3 times and 1 times the channel width X. The channel width X is determined by the set of wires 110 that pass through the second region 122. Preferably, the predetermined length L may be between 1/2 times and 2/3 times the channel width X.

After the method of reducing the integrated circuit layout of the present invention without substantially affecting the electronic characteristics of the device, a usable photomask can be obtained. By using the reticle, a circuit layout structure can be formed on the substrate on a substrate in combination with exposure, development, and etching and deposition of the substrate. 5 to 7 are schematic views showing a preferred embodiment of the circuit layout structure of the present invention. First, as shown in Fig. 6, the circuit layout structure 100 of the present invention is intended to be formed on a substrate 101. Substrate 101 is typically a semiconductor substrate such as tantalum. The substrate 101 may include a plurality of different regions, such as a first region 121 and a second region 122. The first region 121 may be an insulating region, such as a shallow trench isolation (STI) region, a field oxide layer region, and the second region 122 may be an active region, such as a metal oxide semiconductor (MOS) region, an element region. Wait.

A set of wires 110 forms a set of wires 110 that may include a first wire 111 and a second wire 112. The first wire 111 and the second wire 112 may respectively comprise a suitable conductive material, such as a metal or a doped polysilicon. The first wire 111 and the second wire 112 in the wire group 110 pass through the first region 121 and the second region 122, respectively. When the first wire 111 and the second wire 112 pass through the second region 122, the first wire 111 and the second wire 112 located in the second region 122 are respectively regarded as gates of a semiconductor element (not shown).

The first wire 111 and the second wire 112 may be in parallel with each other, for example, according to a first region rule and a second region rule, respectively. For example, if the first area rule is different from the second area rule, there is a variable gap S0 between the first wire 111 and the second wire 112.

In addition, the line widths of the first wire 111 and the second wire 112 are not completely the same. For example, any one of the first wire 111 and the second wire 112 selectively has a first region line width w1 on the first region 121 and a second region line width W2 on the second region 122. The first region line width w1 is substantially different from the second region line width W2. Preferably, the first area line width w1 is smaller than the second area line width W2.

On the other hand, due to the variable gap S0, the first wire 111 and the second wire 112 may selectively have a first gap s1 in the first region 121 and a second gap s2 in the second region 122. In addition, the first wire 111 and the second wire 112 may also selectively have a first pitch p1 in the first region 121 and a second pitch p2 in the second region 122. When the first area rule is different from the second area rule, the first gap s1 may be smaller than the second gap s2, or Yes, the first pitch p1 is smaller than the second pitch p2.

In a first embodiment of the present invention, as shown in FIG. 6, the wire set 110 may include at least one 45 degree turn angle in the first region 121. On the other hand, in another embodiment of the present invention, as shown in FIG. 5, the wire group 110 may include at least one 90 degree turn angle in the first region 121.

In a second embodiment of the invention, the set of wires 110 selectively has different line widths in the first region 121. For example, referring to FIG. 6, the first wire 111 and the second wire 112 are adjacent to the first region 121 of the second region 122, and may additionally have a line width W2 different from the first region line width w1.

In a third embodiment of the present invention, please refer to FIG. 7. Although the wire group 110 has different line widths in the first region 121 and the second region 122, respectively, the first wire 111 and the second wire 112 At least one side is aligned. Preferably, the outer sides of the lower side of the first wire 111 and the second wire 112 are aligned with each other.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Circuit layout

101‧‧‧Substrate

110‧‧‧Wire set

111‧‧‧First wire

112‧‧‧Second wire

121‧‧‧First area

122‧‧‧Second area

1 to 5 are diagrams showing a preferred embodiment of a method of reducing the integrated circuit layout of the present invention without substantially affecting the electronic characteristics of the device.

6 to 7 illustrate schematic views of a preferred embodiment of the circuit layout structure of the present invention.

100. . . Circuit layout

101. . . Substrate

110. . . Wire set

111. . . First wire

112. . . Second wire

121. . . First area

122. . . Second area

Claims (18)

A circuit layout structure includes: a substrate including a first region and a second region; and a set of wires including a first wire and a second wire and passing through the first region and the second region The first wire and the second wire have a variable gap and respectively have a first region line width on the first region and a second region line width on the second region. The first area line width is substantially different from the second area line width, wherein the set of wires has the second area line width in the first area adjacent to the second area. The circuit layout structure of claim 1, wherein the first area is a shallow trench isolation area and the second area is an active area. The circuit layout structure of claim 1, wherein the set of wires has a 45 degree turn angle in the first region. The circuit layout structure of claim 1, wherein the set of wires has a 90 degree turn angle in the first region. The circuit layout structure of claim 1, wherein the first area line width is smaller than the second area line width. The circuit layout structure of claim 1, wherein the first wire and the second wire are under Align at least one side of the square side. The circuit layout structure of claim 1, wherein the first wire and the second wire selectively have a first gap in the first region and a second gap in the second region, such that the first gap Less than the second gap. The circuit layout structure of claim 1, wherein the first wire and the second wire selectively have a first pitch in the first region and a second pitch in the second region, such that the first pitch Less than the second pitch. A method of reducing an integrated circuit layout without substantially affecting electronic characteristics of the device, comprising: providing a circuit layout comprising a set of wires, the set of wires comprising a first wire and a second wire and passing through a first region a second region, wherein the first wire and the second wire selectively have a first region original line width, a first region original gap and a first region original pitch on the first region, and The second area has a second area original line width, a second area original gap and a second area original spacing; and a reduction operation is performed, so that the first wire and the second wire are in accordance with a first area rule and a The second area rule selectively has a first area reduction line width, a first area reduction gap and a first area reduction interval on the first area, and the second area original on the second area a line width, a second area reduction gap and a second area reduction pitch, wherein the first area reduces the line width and the second area is original The line width is substantially different. The method of claim 9, the reducing operation comprises: performing a preliminary reduction operation, so that all the line widths, the gaps, and the spacings of the first wire and the second wire are all scaled down, and in the Selectively obtaining a reduced area line width of the first area, a narrowing gap of the first area, a reduced pitch of the first area, and a reduced spacing of the second area on the second area; and the first wire and the The second wire performs an enlarging operation, and the original line width of the second area and the second area are reduced in the second area. The method of claim 9, the reducing operation comprises: performing a preliminary reduction operation, so that all the line widths, the gaps, and the spacing of the first wire and the second wire are all scaled down; performing a preliminary enlargement Operating such that the set of wires has an original line width of the first region and an original line width of the second region: and performing a trim reduction operation, and selectively obtaining the first region reduction line width and the first region on the first region A region narrows the gap. The method of claim 9, wherein the first area is a shallow trench isolation area and the second area is an active area. The method of claim 9, wherein the set of wires has a 45 degree turn angle in the first region. The method of claim 9, wherein the set of wires has a 90 degree turn angle in the first region. The method of claim 9, wherein the first area line width is smaller than the second area line width. The method of claim 9, wherein the set of wires has an original line width of the second region of a predetermined length in the first region adjacent to the second region. The method of claim 16, wherein the predetermined length is between 1/3 times and 1 times the channel width, the channel width being determined by the set of wires passing through the second region. The method of claim 16, wherein the predetermined length is between 1/2 times and 2/3 times the channel width, the channel width being determined by the set of wires passing through the second region.