TWI469272B - Method of manufacturing damascene structue for nand flash memory - Google Patents

Description

Method for manufacturing NAND flash memory mosaic structure

The present invention relates to a method of fabricating a non-volatile memory, and more particularly to a method of fabricating a damascene structure of a NAND flash memory.

With advances in integrated circuit technology and shrinking component sizes, in order to overcome ever-increasing line widths and prevent mis-alignment, a self-alignment process design is often employed.

Taking NAND flash memory components as an example, in order to ensure electrical connection, each of the lines needs to cover the vias, and the vias must cover and vertically align with the corresponding contact windows, so multiple lithography is usually required. The process forms the above structure and requires high resolution, thereby easily increasing the risk of misalignment.

Therefore, there is a need for a method of fabricating an interconnect of a NAND flash memory that simplifies the process steps and avoids misalignment problems.

The invention provides a manufacturing method of a mosaic structure of a NAND flash memory, which can simplify the process steps and avoid misalignment.

The present invention further provides a method of fabricating a damascene structure of a NAND flash memory, which forms a bit line in a simple step while reducing the resistance value of the wire in the peripheral region.

The invention provides a method for manufacturing a mosaic structure of a NAND flash memory. Providing a substrate having an array of memory cells, the memory cell array comprising a plurality of NAND strings arranged in one direction, and in this direction, each NAND string comprises a plurality of word lines and a plurality of floating spaces below the plurality of word lines A gate, and two select transistors positioned at opposite ends of the plurality of word lines. A first dielectric layer covering the array of memory cells is formed on the substrate. At least one contact plug that contacts the substrate is formed between adjacent NAND strings. A termination layer and a second dielectric layer are sequentially formed on the first dielectric layer and the contact plug. A patterned termination layer is formed on the second dielectric layer having at least one first opening corresponding to the contact plug and exposing the second dielectric layer. A third dielectric layer is formed on the patterned termination layer and in the first opening. A patterned mask layer is formed on the third dielectric layer, and has at least one second opening corresponding to the first opening, and the second opening extends in the above direction and exposes the third dielectric layer. Using the patterned mask layer as a mask, removing the third dielectric layer exposed from the second opening to form a trench, and continuing to remove the second dielectric layer exposed from the first opening to form a via window and exposing the termination Floor. The exposed termination layer is removed to expose the contact window plug. A conductor layer in contact with the contact plug is formed in the trench and the via.

The invention further provides a method for manufacturing a damascene structure of a NAND flash memory. Providing a substrate having a memory cell array and a peripheral region, wherein the peripheral region includes at least one transistor, and the memory cell array includes a plurality of NAND strings arranged in one direction, and in this direction, each NAND string includes a plurality of word lines And a plurality of floating gates located below the plurality of word lines, and two selection transistors positioned at opposite ends of the plurality of word lines. A first dielectric layer covering the transistor of the memory cell array and the peripheral region is formed on the substrate. In the neighborhood At least one first contact window plug that contacts the substrate is formed between the NAND strings. A termination layer and a second dielectric layer are sequentially formed on the first dielectric layer and the first contact window plug. Forming a patterned termination layer on the second dielectric layer having at least one first opening corresponding to the first contact window plug and at least one second opening in the peripheral region, and exposing the second dielectric layer. A third dielectric layer is formed on the patterned termination layer and in the first opening and the second opening. Forming a patterned mask layer on the third dielectric layer, having at least one third opening corresponding to the first opening and extending in the above direction, and at least one fourth opening corresponding to the second opening, and exposing the third dielectric Floor. Forming the mask layer as a mask, removing the third dielectric layer exposed from the third opening and the fourth opening to form a trench, and continuing to remove the second dielectric layer exposed from the first opening and the second opening A via window is formed and the termination layer is exposed. The exposed termination layer is removed to expose the first contact plug and the first dielectric layer of the peripheral region. A conductor layer in contact with the first contact plug is formed in the trench and the via.

Based on the above, the manufacturing method of the NAND flash memory mosaic structure proposed by the present invention utilizes a self aligned daul damascene process to form a bit line and a via plug, thereby effectively reducing the process. Step complexity and avoid alignment errors. In addition, the manufacturing method of the NAND flash memory mosaic structure of the present invention can simultaneously process the memory cell array and the peripheral region on the substrate, thereby effectively reducing the process complexity and reducing the resistance of the wires in the peripheral region. value.

The above described features and advantages of the present invention will be more apparent from the following description.

1 to 7C are flowcharts showing the manufacture of a damascene structure of a NAND flash memory in accordance with a first embodiment of the present invention.

First, referring to Fig. 1, a substrate 100 having a memory cell array 102 thereon, such as a germanium substrate, is provided. In the BB line direction, the memory cell array 102 is configured with a plurality of NAND strings 104, each NAND string 104 including a plurality of word lines 106, floating gates 107 located below the word lines 106, and bits in multiple words. Two select transistors 108 are provided at both ends of the line 106, wherein the material of the word line 106 and the floating gate 107 is, for example, doped polysilicon. The word line 106 and the floating gate 107 further include an inter-gate dielectric layer 109, such as yttria/tantalum nitride/yttria. In addition, a gate oxide layer 110 is formed between the substrate 100 and the memory cell array 102, and the material thereof is, for example, ruthenium oxide, and the method for forming the method includes performing a thermal oxidation method. In addition, although only two word lines 106 are shown in each NAND string 104 in FIG. 1, the present invention is not limited to this.

Next, referring to FIG. 2, a first dielectric layer 112 is formed on the substrate 100 to cover the memory cell array 102. The material of the first dielectric layer 112 is, for example, ruthenium oxide, and the method of forming the method includes performing a chemical vapor deposition process. Thereafter, a contact plug 114 contacting the substrate 100 is formed between adjacent two NAND strings 104 in the B-B line direction. The material of the contact window plug 114 is, for example, metal tungsten, and the forming method thereof forms, for example, a contact window opening (not shown) exposing a portion of the substrate 100 in the first dielectric layer 112 and the gate oxide layer 110, and then in contact. The window opening is filled with a metal material to form the contact plug 114, but the invention is not limited thereto. In addition, in the formation of the first The electrical layer 112 may also be selected to form a spacer 111 on the sidewall of the selective transistor 108, the material of which is, for example, tantalum nitride. In the present embodiment, the contact window plug 114 is, for example, a bit line contact window plug, and the source line plug of the NAND string 104 can also be formed while forming the bit line contact window plug (not shown) ). In addition, in FIG. 2, although the five contact window plugs 114 are shown in the base 100, this invention is not limited to this.

In addition, although the first dielectric layer 112 illustrated in FIG. 2 is higher than the spacer 111 to cover the NAND string 104, the present invention is not limited thereto; in other words, the top surface of the first dielectric layer 112 may be Coplanar with the top surface of the spacer 111, just filling the gap between the NAND strings 104.

Thereafter, referring to FIG. 3, the termination layer 116 and the second dielectric layer 118 are sequentially formed on the first dielectric layer 112 and the contact window plug 114. The material of the termination layer 116 is, for example, tantalum nitride, and the method of forming the method includes performing a chemical vapor deposition process. The second dielectric layer 118 is, for example, a ruthenium oxide layer, and the formation method thereof includes performing a chemical vapor deposition process.

Then, referring to FIG. 4, a patterned termination layer 122 is formed on the second dielectric layer 118, and has at least one first opening 123 corresponding to the contact window plug 114, and exposes a portion corresponding to the first opening 123. Dielectric layer 118. The material of the patterned termination layer 122 is, for example, tantalum nitride, and the formation method thereof is, for example, firstly depositing a layer of material on the second dielectric layer 118, and then performing a photolithography process to form a layer in the material layer. An opening 123.

5A, 5B, and 5C, wherein FIG. 5A is a top view, FIG. 5B is a cross-sectional view taken along line B-B of FIG. 5A, and FIG. 5C is a cross-sectional view taken along line C-C of FIG. 5A. On the patterned termination layer 122 and A third dielectric layer 124 is formed in the first opening 123. The third dielectric layer 124 is, for example, a hafnium oxide layer, and the method of forming the same includes performing a chemical vapor deposition process. Next, a patterned mask layer 126 is formed on the third dielectric layer 124, and has at least one second opening 125 corresponding to the first opening 123, and the second opening 125 is groove-shaped and exposes the corresponding second opening 125. A portion of the third dielectric layer 124. The material of the patterned mask layer 126 is, for example, a photoresist material, and the second opening 125 is formed by a lithography process. In other embodiments, the patterned mask layer 126 can also be a hard mask.

Next, please refer to FIG. 6A and FIG. 6B, which respectively show the same perspective view of the next step of FIG. 5B and FIG. 5C. After the mask layer 126 is used as a mask to remove a portion of the third dielectric layer 124 exposed from the second opening 125 to form the trench 127, a portion of the second dielectric layer exposed from the first opening 123 is removed. A via window 128 is formed 118 and a portion of the termination layer 116 corresponding to the first opening 123 is exposed. A method of removing a portion of the third dielectric layer 124 and a portion of the second dielectric layer 118 is, for example, a dry etch process.

7A, 7B, and 7C, wherein Fig. 7A is a top view, Fig. 7B is a cross-sectional view taken along line B-B of Fig. 7A, and Fig. 7C is a cross-sectional view taken along line C-C of Fig. 7A. The exposed portion of the termination layer 116 is removed to expose the contact plug 114, and the method of removing the portion of the termination layer 116 includes a dry etch process. Next, a conductor layer 130 is formed in the trench 127 and the via 128, and the conductor layer 130 is in contact with the contact plug 114. The material of the conductor layer 130 is, for example, metal tungsten, and the forming method includes performing chemical vapor deposition. Process. The tungsten metal outside the trench 127 can then be removed by a chemical mechanical polishing process (CMP). In addition, before forming the conductor layer 130, The patterned mask layer 126 can be removed first, and the removal method includes a dry etch process. In the present embodiment, the conductor layer 130 extending in the B-B line direction is a bit line as a NAND flash memory.

According to the first embodiment, the method for fabricating the NAND flash memory has a patterned termination layer 122 sandwiched between the dielectric layers and a termination layer (such as tantalum nitride) by a dielectric layer (such as hafnium oxide). The high etching selectivity ratio forms the trench 127 and the via 128 in a one-step etching process, and completes the filling of the metal tungsten in one step, thereby being a self-aligned dual damascene process, which effectively reduces the complexity of the process steps and avoids Misalignment.

8A to 8G are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a second embodiment of the present invention. It should be noted that the illustrations are for illustrative purposes only and are not intended to limit the invention.

First, referring to FIG. 8A, a substrate 200 is provided. The substrate 200 is, for example, a germanium substrate, and has a memory cell array 202 and a peripheral region 203. The peripheral region 203 includes at least one transistor 205, and the transistor 205 is composed of a gate dielectric layer 205b. And a gate 205a on the gate dielectric layer 205b. In addition, in the cross-sectional direction, the memory cell array 202 is configured with a plurality of NAND strings 204, each NAND string 204 including a plurality of word lines 206, a plurality of floating gates 207 located below the word lines 206, and Two select transistors 208 at both ends of the plurality of word lines 206, wherein the material of the word line 206 and the floating gate 207 are, for example, doped polysilicon, which may be formed together with the gate 205a of the peripheral region 203. The word line 206 and the floating gate 207 further include an inter-gate dielectric layer 209, such as yttria/tantalum nitride/yttria. In addition, a gate is formed between the substrate 200 and the memory cell array 202. The oxide layer 210, which is made of, for example, tantalum oxide, can be formed together with the gate dielectric layer 205b of the peripheral region 203 by a process such as thermal oxidation. In addition, although only two word lines 206 are shown in each NAND string 204 in FIG. 8A, and only one transistor 205 is shown in the peripheral area 203, the present invention is not limited thereto.

Next, referring to FIG. 8B, a first dielectric layer 212 is formed on the substrate 200 to cover the memory cell array 202 and the transistor 205 of the peripheral region 203. The material of the first dielectric layer 212 is, for example, tantalum oxide, and the method of forming the method includes performing a chemical vapor deposition process. In addition, before forming the first dielectric layer 212, a spacer 211 may be formed on the sidewalls of the selective transistor 208 and the transistor 205, and the material thereof is, for example, tantalum nitride. In addition, although the first dielectric layer 212 illustrated in FIG. 8B is higher than the spacer 211 to cover the NAND string 204, the present invention is not limited thereto; in other words, the top surface of the first dielectric layer 212 may be Coplanar with the top surface of the spacer 211 just fills the gap between the NAND strings 204. Thereafter, a first contact plug 214 that contacts the substrate 200 is formed between adjacent NAND strings 204 in the cross-sectional direction. The material of the first contact window plug 214 is, for example, metal tungsten, and the forming method thereof, for example, forms a contact window opening (not shown) exposing a portion of the substrate 200 in the first dielectric layer 212 and the gate oxide layer 210, and then The contact opening is filled with a metal material to form the first contact window plug 214, but the invention is not limited thereto. In the present embodiment, the first contact window plug 214 is, for example, a bit line contact window plug, and the source line plug of the NAND string 204 can also be formed while forming the bit line contact window plug (not Painted).

Thereafter, please refer to FIG. 8C, at the first dielectric layer 212 and the first contact window. A termination layer 216 and a second dielectric layer 218 are sequentially formed on the plug 214. The material of the termination layer 216 is, for example, tantalum nitride, and the method of forming the method includes performing a chemical vapor deposition process. The second dielectric layer 218 is, for example, a ruthenium oxide layer, and the formation method thereof includes performing a chemical vapor deposition process.

Then, referring to FIG. 8D, a patterned termination layer 222 is formed on the second dielectric layer 218, and has at least one first opening 223 corresponding to the first contact window plug 214 and at least one second opening located in the peripheral region 203. 231, and a portion of the second dielectric layer 218 corresponding to the first opening 223 and the second opening 231 is exposed. The material of the patterned termination layer 222 is, for example, tantalum nitride, and the formation method thereof is, for example, firstly depositing a layer of material on the second dielectric layer 218, and then performing a photolithography process to form a layer in the material layer. An opening 223 and a second opening 231. Thereafter, a third dielectric layer 224 is formed on the patterned termination layer 222 and in the first opening 223 and the second opening 231. The third dielectric layer 224 is, for example, a hafnium oxide layer, and the method of forming the same includes performing a chemical vapor deposition process. In addition, although the second opening 231 in FIG. 8D is shown above the transistor 205 of the peripheral region 203, the invention is not limited thereto.

Next, referring to FIG. 8E, a patterned mask layer 226 is formed on the third dielectric layer 224, and has at least one third opening 225 on the memory cell array 202 corresponding to the first opening 223 and extending in the cross-sectional direction, and At least one fourth opening 233 corresponding to the second opening 231 is formed in the peripheral region 203, and a portion of the third dielectric layer 224 is exposed. The material of the patterned mask layer 226 is, for example, a photoresist material, and the third opening 225 and the fourth opening 233 are formed by a lithography process, but the invention is not limited thereto. In other embodiments, the patterned mask layer 226 can also be a hard mask. Wherein, the dotted line in FIG. 8E represents a diagram The patterned mask layer 226 is contoured parallel to the cross-sectional direction; and in the direction through the page, the third openings 225 in the patterned mask layer 226 are spaced apart, as in FIG. 5A and FIG. 5C is shown.

Then, referring to FIG. 8F, the mask layer 226 is patterned as a mask to remove a portion of the third dielectric layer 224 exposed from the third opening 225 and the fourth opening 233 to form a trench on the memory cell array 202 and The peripheral region 203 forms an opening 227, and further removes a portion of the second dielectric layer 218 exposed from the first opening 223 and the second opening 231 to form a via 228a on the memory cell array 202 and a via in the peripheral region 203. Window 228b and exposes a portion of termination layer 216. A method of removing a portion of the third dielectric layer 224 and a portion of the second dielectric layer 218 is, for example, a dry etch process. The trench in the memory cell array 202 of FIG. 8F is parallel to the cross-sectional direction, such as the trench 127 shown in FIG. 6B in the first embodiment.

Thereafter, referring to FIG. 8G, the exposed portion of the termination layer 216 is removed to expose the first contact window plug 214, and the first dielectric layer 212 of the peripheral region 203 is also exposed. The method of removing the portion of the termination layer 216 includes performing a dry etch process. Next, a conductor layer 230 is formed in the trench, the opening 227 and the via 228a-b, and the conductor layer 230 is in contact with the first contact plug 214, wherein the material of the conductor layer 230 is, for example, metal tungsten, and the forming method thereof Including the chemical vapor deposition process. The metal tungsten outside the trench and opening 227 can then be removed by a chemical mechanical polishing process. In addition, the patterned mask layer 226 may also be removed prior to forming the conductor layer 230, and the removal method includes performing a dry etching process. In this embodiment, the conductor layer 230 extending in the cross-sectional direction on the memory cell array 202 is a bit of the NAND flash memory. The wires, while the conductor layer 230 of the peripheral region 203 can serve as an interconnect.

Similarly, the second embodiment is to form a bit line and a via window plug in contact with the contact window plug by self-aligning the dual damascene process, thereby effectively reducing process complexity and avoiding alignment errors. In addition, in the second embodiment, since the bit lines and the interconnect lines of the NAND flash memory are fabricated by using a uniform step, not only the process complexity is not increased, but also the depth of the interconnect line is increased, thereby reducing the depth thereof. Resistance value.

9A to 9F are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a third embodiment of the present invention. Here, FIG. 9A is a step performed subsequent to FIG. 8A. In addition, the same or similar components in the third embodiment and the second embodiment may be carried out by the same material or method, and thus will not be described again.

First, referring to FIG. 9A, a first contact plug 314 contacting the substrate 200 is formed between adjacent two NAND strings 204 in the cross-sectional direction, and simultaneously formed on at least one side of the transistor 205 in the peripheral region 203. The second contact window plug 315 of the substrate 200 is contacted. The material of the first contact window plug 314 and the second contact window plug 315 is, for example, metal tungsten, and the method of forming the same can be referred to the above embodiments. In the present embodiment, the first contact window plug 314 is, for example, a bit line contact window plug, and the source line plug of the NAND string 204 can also be formed while forming the bit line contact window plug (not The second contact window plug 315 can be connected to the source/drain of the transistor 205 (not shown).

Next, referring to FIG. 9B, a termination layer 316 is sequentially formed on the first dielectric layer 212, the first contact window plug 314, and the second contact window plug 315. The second dielectric layer 318. The material of the termination layer 316 is, for example, tantalum nitride, and the formation method thereof can be referred to the above embodiments. The second dielectric layer 318 is, for example, a ruthenium oxide layer, and the method of forming the same may be referred to the above embodiments.

Then, referring to FIG. 9C, a patterned termination layer 322 is formed on the second dielectric layer 318, and has a second contact window corresponding to the first contact opening 323 of the first contact window plug 314 and the corresponding peripheral region 203. At least one fifth opening 331 of the plug 315 and a portion of the second dielectric layer 318 corresponding to the first opening 323 and the fifth opening 331 are exposed. The material of the patterned termination layer 322 is, for example, tantalum nitride, and the formation method thereof is, for example, firstly depositing a layer of material on the second dielectric layer 318, and then performing a photolithography process to form a layer in the material layer. An opening 323 and a fifth opening 331.

Thereafter, a third dielectric layer 324 is formed on the patterned termination layer 322 and in the first opening 323 and the fifth opening 331. The third dielectric layer 324 is, for example, a ruthenium oxide layer, and the formation method thereof can be referred to the above embodiments.

Next, referring to FIG. 9D, a patterned mask layer 326 is formed on the third dielectric layer 324, and has at least a third opening 325 on the memory cell array 202 corresponding to the first opening 323 and extending in the cross-sectional direction, and At least one sixth opening 333 corresponding to the fifth opening 331 is formed in the peripheral region 203, and a portion of the third dielectric layer 324 is exposed. The materials and formation of the patterned mask layer 326 can be referred to the above embodiments. The dashed line in FIG. 9D indicates the contour of the patterned mask layer 326 in a direction parallel to the cross-section; and is spaced apart from the third opening 325 in the patterned mask layer 326 in the direction through the page, such as the first 5A and 5C in the embodiment. In addition, the sixth opening 333 can extend not only in the direction of the page as shown in FIG. 9D. It can also be extended in the direction of the section according to the design requirements.

Then, referring to FIG. 9E, a patterned mask layer 326 is used as a mask to remove a portion of the third dielectric layer 324 exposed from the third opening 325 and the sixth opening 333 to form a trench on the memory cell array 202 and The peripheral region 203 forms an opening 327, and further removes a portion of the second dielectric layer 318 exposed from the first opening 323 and the fifth opening 331, forming a via 328a on the memory cell array 202 and forming a via in the peripheral region 203. Window 328b and exposes a portion of termination layer 316. A method of removing a portion of the third dielectric layer 324 and a portion of the second dielectric layer 318 is, for example, a dry etch process. The trench in the memory cell array 202 in FIG. 9E is parallel to the cross-sectional direction, such as the trench 127 shown in FIG. 6B in the first embodiment.

Thereafter, referring to FIG. 9F, the exposed portion of the termination layer 316 is removed, exposing the first contact window plug 314, and the second contact window plug 315 is also exposed. The method of removing the portion of the termination layer 316 includes performing a dry etch process. Next, a conductor layer 330 is formed in the trench, the opening 327 and the via 328a-b, and the conductor layer 330 is in contact with the first contact plug 314 and the second contact plug 315, and the material and formation of the conductor layer 330 The method can be referred to the above embodiments. In addition, the patterned mask layer 326 may also be removed prior to forming the conductor layer 330, and the removal method includes performing a dry etching process. In the present embodiment, the conductor layer 330 extending in the cross-sectional direction on the memory cell array 202 is a bit line as a NAND flash memory, and the conductor layer 330 of the peripheral region 203 can serve as an interconnect.

Similarly, the third embodiment effectively forms a bit line and a via window plug in contact with the contact window plug by self-aligning the dual damascene process. Low process complexity and avoid alignment errors. In addition, in the third embodiment, since the bit lines and the interconnect lines of the NAND flash memory are fabricated using a uniform step, the process complexity is not increased, thereby saving process cost.

10A through 10D are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a fourth embodiment of the present invention. 10A is a step performed subsequent to FIG. 9B. In addition, the same or similar components in the fourth embodiment and the third embodiment may be carried out by the same materials or methods, and thus will not be described again.

First, referring to FIG. 10A, a patterned termination layer 422 is formed on the second dielectric layer 318, which has at least one first opening 423 corresponding to the first contact window plug 314, and exposes a portion corresponding to the first opening 423. The second dielectric layer 318. Thereafter, a third dielectric layer 424 is formed on the patterned termination layer 422 and in the first opening 423.

Next, referring to FIG. 10B, a patterned mask layer 426 is formed on the third dielectric layer 424, and has at least one third opening 425 on the memory cell array 202 corresponding to the first opening 423 and extending in the cross-sectional direction, and At the peripheral region 203, there is at least a seventh opening 433 corresponding to the second contact window plug 315, and a portion of the third dielectric layer 424 is exposed. The dashed line in FIG. 10B indicates the contour of the patterned mask layer 426 in a direction parallel to the cross-section; and is spaced apart from the third opening 425 in the patterned mask layer 426 in the direction through the page, such as the first 5A and 5C in the embodiment. In addition, the seventh opening 433 may extend not only in the direction of the page as shown in FIG. 10B but also in the cross-sectional direction as required by the design.

Then, referring to FIG. 10C, the mask layer 426 is patterned as a mask. A portion of the third dielectric layer 424 exposed from the third opening 425 and the seventh opening 433 is removed to form a trench on the memory cell array 202 and an opening 427 is formed in the peripheral region 203, and the removal from the first opening 423 is continued. A portion of the second dielectric layer 318 forms a via 428 on the memory cell array 202 and exposes a portion of the termination layer 316. The trench in the memory cell array 202 in FIG. 10C is parallel to the cross-sectional direction, such as the trench 127 shown in FIG. 6B in the first embodiment.

Thereafter, referring to FIG. 10D, the exposed portion of the termination layer 316 is removed to expose the first contact window plug 314, and the second dielectric layer 318 of the peripheral region 203 is also exposed. Next, a conductor layer 430 is formed in the trench, opening 427 and via 428, and the conductor layer 430 is in contact with the first contact plug 314. In addition, the patterned mask layer 426 may also be removed prior to forming the conductor layer 430. In the present embodiment, the conductor layer 430 extending in the cross-sectional direction on the memory cell array 202 is a bit line as a NAND flash memory, and the conductor layer 430 of the peripheral region 203 can serve as an interconnect.

Similarly, the fourth embodiment is to form a bit line and a via plug in contact with the contact plug by self-aligning the dual damascene process, thereby effectively reducing process complexity and avoiding alignment errors. In addition, in the fourth embodiment, since the bit lines and the interconnect lines of the NAND flash memory are fabricated using a uniform step, the process complexity is not increased, thereby saving process cost.

Further, in the method of fabricating the damascene structure of the NAND flash memory of the present invention, the second embodiment, the third embodiment, and the fourth embodiment can be selectively used in combination with respect to the circuit design of the peripheral region.

In summary, the NAND flash memory proposed by the above embodiments The manufacturing method of the damascene structure adopts a self-aligned dual damascene process to form a trench and a via window in one step, thereby forming a bit line and a via window plug in contact with the contact window plug, thereby effectively reducing the complexity of the process step And avoid misalignment. In addition, the manufacturing method of the NAND flash memory mosaic structure proposed in the above embodiment can use the consistent steps to create the bit line and the interconnect line of the NAND flash memory, thereby reducing the complexity of the process steps and the process cost. The resistance can be lowered by increasing the depth of the wiring within the peripheral area.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ base

102, 202‧‧‧ memory cell array

104, 204‧‧‧NAND strings

106, 206‧‧ ‧ character line

107, 207‧‧‧ Floating Gate

108, 208‧‧‧Selecting a crystal

109, 209‧‧‧ Inter-gate dielectric layer

110, 210‧‧ ‧ gate oxide layer

111, 211‧‧ ‧ spacer

112, 212‧‧‧ first dielectric layer

114, 214, 314, 315‧ ‧ contact window plug

116, 216, 316‧‧‧ termination layer

118, 218, 318‧‧‧ second dielectric layer

122, 222, 322, 422‧‧‧ patterned termination layer

123, 125, 223, 225, 231, 233, 227, 323, 325, 331, 333, 327, 423, 425, 433, 427‧‧

124, 224, 324, 424‧‧‧ third dielectric layer

126, 226, 326, 426‧‧‧ patterned mask layer

127‧‧‧ Ditch

128, 228a, 228b, 328a, 328b, 428‧‧

130, 230, 330, 430‧‧‧ conductor layers

203‧‧‧The surrounding area

205‧‧‧Optoelectronics

205a‧‧‧ gate

205b‧‧‧gate dielectric layer

1 to 7C are flowcharts showing the manufacture of a damascene structure of a NAND flash memory in accordance with a first embodiment of the present invention.

8A to 8G are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a second embodiment of the present invention.

9A to 9F are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a third embodiment of the present invention.

10A through 10D are cross-sectional views showing a manufacturing process of a damascene structure of a NAND flash memory in accordance with a fourth embodiment of the present invention.

100‧‧‧Base

106‧‧‧ character line

107‧‧‧Floating gate

108‧‧‧Selecting a crystal

109‧‧‧Interruptor dielectric layer

110‧‧‧ gate oxide layer

111‧‧‧ spacer

112‧‧‧First dielectric layer

114‧‧‧Contact window plug

116‧‧‧End layer

118‧‧‧Second dielectric layer

122‧‧‧patterned termination layer

123‧‧‧ openings

127‧‧‧ Ditch

128‧‧・Intermediate window

130‧‧‧Conductor layer

Claims (19)

A method of fabricating a damascene flash memory mosaic structure, comprising: providing a substrate having a memory cell array, the memory cell array including a plurality of NAND strings arranged in a direction, wherein the NAND strings are in the direction a plurality of word lines and a plurality of floating gates under the word lines, and two selection transistors positioned at opposite ends of the word lines; forming a first dielectric layer on the substrate The first dielectric layer covers the memory cell array; at least one contact window plug is formed between the adjacent NAND strings to contact the substrate; and a first dielectric layer and the contact window plug are formed on the first dielectric layer Forming a second dielectric layer on the termination layer; forming a patterned termination layer on the second dielectric layer, the patterned termination layer having at least one first opening corresponding to the window plug and Exposing the second dielectric layer; forming a third dielectric layer on the patterned termination layer and the first opening; forming a patterned mask layer on the third dielectric layer, corresponding to the first At least one second opening of the opening, the second opening extending along the direction Stretching and exposing the third dielectric layer; using the patterned mask layer as a mask, removing the third dielectric layer exposed from the second opening to form a trench, and continuing to remove from the first opening Exposing the second dielectric layer to form a via and exposing the termination layer; Removing the exposed termination layer to expose the contact plug; and forming a conductor layer in the trench and the via, the conductor layer being in contact with the contact plug. The method of fabricating a damascene structure of a NAND flash memory according to claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise a ruthenium oxide layer. The manufacturing method of the damascene structure of the NAND flash memory according to claim 1, wherein the material of the termination layer and the patterned termination layer comprises tantalum nitride. The method for fabricating a damascene flash memory in accordance with claim 1, wherein the step of forming the conductor layer comprises filling the via to form a via plug and filling the trench. Form a single line. The manufacturing method of the damascene structure of the NAND flash memory according to claim 1, wherein the step of forming the conductor layer further comprises removing the patterned mask layer. The manufacturing method of the damascene structure of the NAND flash memory according to claim 1, wherein before forming the first dielectric layer, further comprising forming a spacer on at least a sidewall of each of the selection transistors. The manufacturing method of the damascene structure of the NAND flash memory according to claim 6, wherein the spacer comprises a ruthenium oxide layer. A method for manufacturing a mosaic structure of a NAND flash memory, comprising: Providing a substrate having a memory cell array and a peripheral region, wherein the peripheral region includes at least one transistor, the memory cell array including a plurality of NAND strings arranged in one direction, and in the direction, each of the NAND strings includes a plurality of word lines and a plurality of floating gates under the word lines, and two selection transistors positioned at opposite ends of the word lines; forming a first dielectric layer on the substrate The first dielectric layer covers the memory cell array and the transistor of the peripheral region; forming at least one first contact window plug contacting the substrate between the adjacent NAND strings; and the first dielectric layer Forming a termination layer on the first contact window plug; forming a second dielectric layer on the termination layer; forming a patterned termination layer on the second dielectric layer, the patterned termination layer having corresponding At least one first opening of the first contact window plug and at least one second opening in the peripheral region, and exposing the second dielectric layer; on the patterned termination layer and the first opening and the second opening Forming a third dielectric layer; forming on the third dielectric layer a patterned mask layer having at least one third opening corresponding to the first opening and extending in the direction, and at least a fourth opening corresponding to the second opening, and exposing the third dielectric layer; The mask layer is a mask, the third dielectric layer exposed from the third opening and the fourth opening is removed to form a trench, and the removal of the first opening and the second opening is further removed. Forming a via window and exposing the termination layer; Removing the exposed termination layer, exposing the first contact window plug and exposing the first dielectric layer of the peripheral region; and forming a conductor layer in the trench and the via, the conductor layer The first contact window plug contacts. The method of fabricating a damascene structure of a NAND flash memory according to claim 8 wherein the step of forming the patterned stop layer comprises causing the second opening to correspond to the transistor of the peripheral region. The method of fabricating a damascene flash memory in accordance with claim 8 wherein the step of forming the first contact plug comprises forming contact with at least one side of the transistor in the peripheral region. At least one second contact window plug of the substrate. The method of fabricating a damascene structure of a NAND flash memory according to claim 10, wherein the step of forming the patterned termination layer comprises causing the patterned termination layer to have a second contact window in the peripheral region. At least one fifth opening of the plug. The method for manufacturing a damascene flash memory inlaid structure according to claim 11, wherein the step of forming the patterned mask layer comprises causing the patterned mask layer to have a fifth in the peripheral region. At least one sixth opening of the opening. The method of manufacturing a damascene flash memory inlaid structure according to claim 10, wherein the step of forming the patterned mask layer comprises causing the patterned mask layer to have a second portion in the peripheral region. Contacting at least a seventh opening of the window plug. NAND flash memory as described in claim 13 The manufacturing method of the mosaic structure of the body, wherein the patterned mask layer is used as a mask, and the third dielectric layer exposed from the seventh opening is removed to form a trench. The method for fabricating a damascene structure of a NAND flash memory according to claim 8, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer comprise a ruthenium oxide layer. The manufacturing method of the damascene structure of the NAND flash memory according to claim 8, wherein the material of the termination layer and the patterned termination layer comprises tantalum nitride. The manufacturing method of the damascene structure of the NAND flash memory according to claim 8, wherein the step of forming the conductor layer further comprises removing the patterned mask layer. The method for fabricating a damascene structure of a NAND flash memory according to claim 8, wherein before forming the first dielectric layer, further comprising forming at least on each of the selected transistors and sidewalls of the transistor a gap wall. The manufacturing method of the damascene structure of the NAND flash memory according to claim 18, wherein the spacer comprises a ruthenium oxide layer.