TWI467774B - Thin-film transistor structure and method for manufacturing the same - Google Patents

Description

Thin film transistor structure and manufacturing method thereof

The present invention relates to a thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure for a display and a method of fabricating the same.

The display mainly comprises a thin film transistor and other electronic components. In the structure of the thin film transistor, the material of the semiconductor layer is mainly amorphous germanium. However, with the development of technology, the material of the above semiconductor layer is gradually converted into a metal oxide, and indium gallium zinc oxide (IGZO) has a better electron mobility.

However, in the process of a thin film transistor using an indium gallium zinc oxide (IGZO) as a semiconductor layer, an etching solution in a wet etching process is generally used for the semiconductor layer material indium gallium zinc oxide (IGZO) and for source and germanium. The polarity selectivity of the pole material, such as metal molybdenum alloy, is extremely low, which is not conducive to the process.

In addition, in the process of fabricating a conventional structure of an indium gallium zinc oxide (IGZO) transistor, the source and the drain are in direct contact with the semiconductor layer, and if the source and drain etching processes are dry etched, the semiconductor will be in the semiconductor. The layer generates a back channel ion bombardment effect, which causes the indium gallium zinc oxide (IGZO) semiconductor layer of the thin film transistor element to cause deterioration problems after long-time driving, and even causes leakage and threshold voltage shift.

At the same time, since the indium gallium zinc oxide (IGZO) semiconductor layer directly contacts the source and the drain, it is also prone to hot carrier injection, resulting in a decrease in electron mobility.

Therefore, there is a need for a solution to avoid deterioration of the semiconductor layer of the indium gallium zinc oxide (IGZO) thin film transistor element due to long-time driving, and to improve its electron mobility.

One aspect of the present invention provides a thin film transistor structure. The thin film transistor structure includes a substrate, a gate, a gate insulating layer, a source connecting layer, a drain connecting layer, a source, a drain, and a semiconductor layer.

The gate system is disposed on the substrate. The gate insulating layer covers the gate and the substrate. The source connection layer and the drain connection layer are disposed on the gate insulating layer and are not in contact with each other. The source is disposed on the source connection layer and the gate insulation layer. The drain is provided on the drain connection layer and the gate insulation layer. The semiconductor layer is disposed on the gate insulating layer, and connects the source connection layer and the drain connection layer, and the semiconductor layer does not contact the source and the drain.

According to an embodiment of the invention, the aforementioned thin film transistor further comprises at least one protective layer. The protective layer is disposed between the source and the gate insulating layer, between the drain and the gate insulating layer, between the semiconductor layer and the gate insulating layer, or any combination thereof. The source connection layer connects the source and the semiconductor layer, and the drain connection layer connects the drain and the semiconductor layer.

According to an embodiment of the invention, the material of the protective layer comprises niobium nitride, tantalum oxide, polyimide or polysiloxane.

According to an embodiment of the invention, the material of the gate insulating layer comprises tantalum nitride, tantalum oxide, polyimine or polyoxyalkylene.

According to an embodiment of the invention, the material of the source connection layer and the drain connection layer comprises a metal or a metal oxide, wherein the metal oxide comprises Indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO) or zinc oxide (ZnO).

According to an embodiment of the invention, the semiconductor layer material is a metal oxide, wherein the metal oxide comprises indium gallium zinc oxide (IGZO).

According to an embodiment of the invention, the material of the source and the drain includes a metal or an alloy, wherein the metal alloy comprises a molybdenum chromium alloy.

According to an embodiment of the invention, the source connection layer and the drain connection layer respectively have an overlap distance for the gate, for example, less than or equal to 1 micrometer.

Another aspect of the present invention provides a method of fabricating a thin film transistor structure comprising the following steps. A substrate is provided and a gate is formed on the substrate. Covering the gate insulating layer on the gate and the substrate. A source connection layer and a drain connection layer are formed on the gate insulating layer and are not in contact with each other. A source is formed on the source connection layer and the gate insulation layer. A drain is formed on the drain connection layer and the gate insulating layer. A semiconductor layer is formed on the source connection layer, the drain connection layer, and the gate insulating layer, wherein the semiconductor layer does not contact the source and the drain.

According to an embodiment of the present invention, the method for fabricating the thin film transistor structure further includes forming at least one protective layer between the source and the gate insulating layer, between the semiconductor layer and the gate insulating layer, between the drain and the gate insulating layer, or Any combination. The source connection layer is connected to the source and the semiconductor layer, and the drain connection layer is connected to the drain and the semiconductor layer.

According to an embodiment of the invention, the step of forming the semiconductor layer comprises using an etching method, wherein the etching method comprises a wet acid etching process, a dry etching process or any combination thereof, and the etching solution of the wet acid etching process comprises PAN (Phosphoric) An -Acetic-Nitric acid etching solution comprising phosphoric acid, acetic acid, nitric acid or any combination thereof.

Figure 1 is a schematic cross-sectional view showing a conventional thin film transistor structure. In FIG. 1, a conventional thin film transistor structure 100 is composed of a substrate 110, a gate 120, a gate insulating layer 130, an indium gallium zinc oxide (IGZO) semiconductor layer 140, a source 150a, and a drain 150b. . It is worth noting that the indium gallium zinc oxide (IGZO) semiconductor layer 140 is in direct contact with the source 150a and the drain 150b, respectively. If the etching of the source 150a and the drain 150b is performed by a dry etching process, a back channel ion bombardment effect is generated in the semiconductor layer 140. This conventional thin film transistor structure causes indium gallium of the thin film transistor component after being driven for a long time. The zinc oxide (IGZO) semiconductor layer 140 is degraded, resulting in leakage and threshold voltage shift.

Meanwhile, since the indium gallium zinc oxide (IGZO) semiconductor layer 140 directly contacts the source 150a and the drain 150b, hot carrier injection is also likely to occur, resulting in a decrease in electron mobility.

Accordingly, an embodiment of the present invention provides a novel thin film transistor structure to solve the problems of degradation of the thin film transistor element and reduction in electron mobility caused by the prior art.

2A is a schematic cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present invention. According to an embodiment of the present invention, the thin film transistor structure of FIG. 2A can be applied to a liquid crystal display, an electrophoretic display, or the like, but is not limited thereto.

In FIG. 2A, the thin film transistor 200a includes a substrate 210, a gate 220, a gate insulating layer 230, a source connecting layer 240a and a drain connecting layer 240b, a source 250a and a drain 250b, and a semiconductor layer 260. The source connection layer 240a has an overlap distance d1 for the gate 220, and the drain connection Contact layer 240b has an overlap distance d2 for gate 220. Of particular note is that the semiconductor layer 260 is not in contact with the source 250a and the drain 250b.

According to an embodiment of the invention, the material of the gate insulating layer 230 comprises tantalum nitride, tantalum oxide, polyimine or polyoxyalkylene.

According to an embodiment of the invention, the material of the source connection layer 240a and the drain connection layer 240b comprises a metal or a metal oxide, wherein the metal oxide comprises indium tin oxide (ITO), aluminum zinc oxide (AZO), Indium zinc oxide (IZO) or zinc oxide (ZnO). .

According to an embodiment of the invention, the material of the source 250a and the drain 250b comprises a metal or a metal alloy, wherein the metal alloy comprises a molybdenum chrome alloy.

According to an embodiment of the invention, the material of the semiconductor layer 260 is a metal oxide, wherein the metal oxide comprises indium gallium zinc oxide (IGZO).

According to an embodiment of the invention, the overlap distance d1 of the source connection layer 240a for the gate 220 is less than or equal to 1 micron. According to another embodiment of the present invention, the overlap distance d2 of the drain connection layer 240b for the gate 220 is less than or equal to 1 micrometer.

2B is a cross-sectional view showing a process stage of a thin film transistor structure according to an embodiment of the present invention.

As shown in the cross-sectional structure 200b of FIG. 2B, a substrate 210 is first provided, and a gate 220 is formed on the substrate 210. Then, on the substrate 210 and the gate 220, the gate insulating layer 230 is covered. Next, on the gate insulating layer 230, a source connection layer 240a and a drain connection layer 240b are formed, and the source connection layer 240a and the drain connection layer 240b are not in contact with each other.

Then, as shown in FIG. 2A, the source electrode 250a is formed on the source connection layer 240a and the gate insulating layer 230, and the drain 250b is formed on the gate connection layer 240b and the gate insulating layer 230. Semiconductor layer 260 is formed The source connection layer 240a, the drain connection layer 240b, and the gate insulating layer 230. In one embodiment, after the source 250a and the drain 250b are formed, the semiconductor layer 260 is formed. In another embodiment, the semiconductor layer 260 may be formed first, and then the source 250a and the drain 250b may be formed.

It should be noted that the semiconductor layer 260 does not contact the source 250a and the drain 250b, and the semiconductor layer 260 is electrically connected to the source 250a and the drain 250b by the source connection layer 240a and the drain connection layer 240b, respectively.

According to an embodiment of the invention, the material of the semiconductor layer 260 is indium gallium zinc oxide (IGZO). In the prior art, since indium gallium zinc oxide (IGZO) directly contacts the source and the drain, it is easy to generate hot carrier injection, resulting in a decrease in electron mobility. Therefore, in one embodiment of the present invention, the semiconductor layer 260 is not in contact with the source 250a and the drain 250b, and the via is formed by the source connection layer 240a and the drain connection layer 240b to enhance the electron mobility of the thin film transistor.

According to an embodiment of the invention, the material of the source connection layer 240a and the drain connection layer 240b is indium tin oxide (ITO), which is indium tin oxide compared to the material of the semiconductor layer 260, indium gallium zinc oxide (IGZO). The material (ITO) has better conductivity and can also improve the hot carrier injection phenomenon to solve the problem of reduced electron mobility.

On the other hand, if the source and drain etching processes use the back channel ion bombardment effect caused by dry etching, the semiconductor layer degradation problem of the thin film transistor will be caused for a long time, thereby reducing the reliability of the thin film transistor. Therefore, in accordance with an embodiment of the present invention, the semiconductor layer 260 is electrically connected to the source 250a and the drain 250b via the source connection layer 240a and the drain connection layer 240b, respectively, wherein the semiconductor layer 260 is not connected to the source 250a and the drain 250b contact, so it can avoid the back channel ion bombardment in the source and drain dry etching process In order to solve the problem of deterioration of the semiconductor layer used for a long time in the use of the thin film transistor, the reliability of the thin film transistor can be improved.

In addition, since the etching ratio of the general etching liquid to the indium gallium zinc oxide (IGZO) semiconductor layer 260 and the metal molybdenum alloy for the source 250a and the drain 250b is extremely low, it is made of indium gallium zinc oxide (IGZO). When the semiconductor layer 260 is used, its process is difficult to control.

According to an embodiment of the present invention, when a semiconductor layer is formed of indium gallium zinc oxide (IGZO), a two-stage etching method (not shown) is employed. Wherein, the two-stage etching method first removes most of the source and drain materials by wet acid etching, wherein the etching solution uses PAN (Phosphoric-Acetic-Nitric) acid, and the PAN acid comprises phosphoric acid, acetic acid. In the case of a PAN (Phosphoric-Acetic-Nitric) acid etching process, the etching rate of the indium gallium zinc oxide (IGZO) semiconductor layer will be faster (about more than 20 nm/sec), which will cause indium. The gallium zinc oxide (IGZO) semiconductor layer has a large thickness difference between the source and the drain. The remaining source and drain materials are then removed by dry etching to shorten the thickness gap between the source and the drain of the semiconductor layer. However, the manufacturing method of the above semiconductor layer is merely an exemplary example, and is not limited thereto.

3A is a schematic cross-sectional view showing a structure of a thin film transistor according to another embodiment of the present invention. According to an embodiment of the present invention, the thin film transistor structure of FIG. 3A can be applied to a liquid crystal display, an electrophoretic display, or the like, but is not limited thereto.

In FIG. 3A, the thin film transistor 300a includes a substrate 210, a gate 220, a gate insulating layer 230, a source connecting layer 240a and a drain connecting layer 240b, a protective layer 310, a source 250a and a drain 250b, and a semiconductor. Layer 260. Wherein the source connection layer 240a has an overlap distance d3 for the gate 220, The drain connection layer 240b has an overlap distance d4 for the gate 220.

3A and 2A are cross-sectional structural views of a thin film transistor according to an embodiment of the present invention. However, the thin film transistor 300a illustrated in FIG. 3A is different from the thin film transistor 200a illustrated in FIG. 2A in that the thin film transistor 300a of FIG. 3A has the protective layer 310 at the source 250a and the gate insulating layer 230. Between the semiconductor layer 260 and the gate insulating layer 230 and between the drain 250b and the gate insulating layer 230. Further, the method of manufacturing the thin film transistor 300a of FIG. 3A further includes the step of forming the protective layer 310. Except for the protective layer 310 of Fig. 3A, the remaining components of Fig. 3A are the same as those of Fig. 2A.

According to an embodiment of the invention, the material of the protective layer 310 comprises tantalum nitride, tantalum oxide, polyimine or polyoxyalkylene.

According to an embodiment of the invention, the overlap distance d3 of the source connection layer 240a for the gate 220 is less than or equal to 1 micron. According to another embodiment of the present invention, the overlap distance d4 of the drain connection layer 240b for the gate 220 is less than or equal to 1 micrometer.

FIG. 3B is a cross-sectional view showing a process stage of a thin film transistor structure according to an embodiment of the present invention.

As shown in the cross-sectional structure 300b of FIG. 3B, the cross-sectional structure 200b of FIG. 2B is continued to cover the protective layer 310 on the source connection layer 240a, the drain connection layer 240b, and the gate insulating layer 230. The protective layer 310 exposes a portion of the source connection layer 240a and a portion of the drain connection layer 240b to facilitate subsequent processing.

As shown in the thin film transistor 300a of FIG. 3A, the source structure 250a is formed on the source connection layer 240a and the protective layer 310 in the cross-sectional structure 300b shown in FIG. 3B. On the drain connection layer 240b and the protective layer 310, the shape Into the bungee pole 250b. The semiconductor layer 260 is formed on the source connection layer 240a, the drain connection layer 240b, and the protection layer 310.

Similar to the thin film transistor 200a of FIG. 2A, the semiconductor layer 260 does not contact the source 250a and the drain 250b, and the semiconductor layer 260 is electrically connected to the source 250a via the source connection layer 240a and the drain connection layer 240b, respectively. Bungee 250b.

In the above embodiment, by separating the semiconductor layer, the source and the drain, and connecting the semiconductor layer, the source and the drain with the source connection layer and the drain connection layer, the following objectives can be achieved: (1) the semiconductor layer is not in contact with the source and the drain, but the source connection layer and the drain connection layer form a via to enhance the electron mobility of the thin film transistor; (2) By the path formed by the source connection layer and the drain connection layer, the ion bombardment effect of the back channel of the semiconductor layer generated in the dry etching process of the source and the drain is avoided to solve the long-term driving of the thin film transistor component. a problem that causes deterioration; (3) By the above two advantages, the element degradation of the thin film transistor is reduced, thereby improving the reliability of the thin film transistor.

Although the embodiments of the present invention are disclosed as described above, they are not intended to limit the scope of application of the present invention. Various modifications and changes can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is based on the scope of the patent application attached hereinafter.

100‧‧‧Thin-film crystal structure

110, 210‧‧‧ substrate

120, 220‧‧‧ gate

130, 230‧‧‧ gate insulation

140, 260‧‧‧ semiconductor layer

150a, 250a‧‧‧ source

150b, 250b‧‧‧ bungee

200a‧‧‧thin film transistor

200b‧‧‧ section structure

240a‧‧‧Source connection layer

240b‧‧‧汲 connection layer

300a‧‧‧thin film transistor

300b‧‧‧section structure

310‧‧‧Protective layer

D1, d2, d3, d4‧‧‧ overlap distance

Figure 1 is a schematic cross-sectional view showing a conventional thin film transistor structure.

2A is a schematic cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present invention.

2B is a cross-sectional view showing a process stage of a thin film transistor structure according to an embodiment of the present invention.

3A is a schematic cross-sectional view showing a structure of a thin film transistor according to an embodiment of the present invention.

FIG. 3B is a cross-sectional view showing a process stage of a thin film transistor structure according to an embodiment of the present invention.

200a‧‧‧thin film transistor

210‧‧‧Substrate

220‧‧‧ gate

230‧‧‧ gate insulation

240a‧‧‧Source connection layer

240b‧‧‧汲 connection layer

250a‧‧‧ source

250b‧‧‧汲polar

260‧‧‧Semiconductor layer

D1, d2‧‧‧ overlap distance

Claims (15)

A thin film transistor structure comprising: a substrate; a gate disposed on the substrate; a gate insulating layer covering the gate and the substrate; a source connection layer and a drain connection a layer disposed on the gate insulating layer and not in contact with each other, wherein the source connecting layer and the drain connecting layer are made of a conductive metal oxide; a source is disposed on the source connecting layer and the layer a gate insulating layer; a drain electrode disposed on the drain connection layer and the gate insulating layer; and a metal oxide semiconductor layer disposed on the gate insulating layer and connected to the source connection layer The drain is connected to the layer and does not contact the source and the drain. The thin film transistor structure of claim 1, further comprising: at least one protective layer disposed between the source and the gate insulating layer, between the metal oxide semiconductor layer and the gate insulating layer, the drain and the And a gate insulating layer or any combination thereof, wherein the source connecting layer connects the source and the metal oxide semiconductor layer, and the drain connecting layer connects the drain and the metal oxide semiconductor layer. The thin film transistor structure according to claim 2, wherein the material of the protective layer comprises niobium nitride, tantalum oxide, polyimine or polydecane. The thin film transistor structure of claim 1, wherein the material of the gate insulating layer comprises tantalum nitride, tantalum oxide, polyimine (PI) or polysiloxane. The thin film transistor structure according to claim 1, wherein the metal oxide comprises indium tin oxide (ITO), aluminum zinc oxide (AZO), indium zinc oxide (IZO) or zinc oxide (ZnO). The thin film transistor structure of claim 1, wherein the metal oxide semiconductor layer comprises indium gallium zinc oxide (IGZO). The thin film transistor structure of claim 1, wherein the source and the material of the drain include a metal or a metal alloy. The thin film transistor structure of claim 7, wherein the metal alloy comprises a molybdenum chromium alloy. The thin film transistor structure of claim 1, wherein the source connection layer and the drain connection layer respectively have an overlap distance for the gate. The thin film transistor structure of claim 9, wherein the overlap distance is less than or equal to 1 micrometer. A method for fabricating a thin film transistor structure, comprising: providing a substrate; forming a gate on the substrate; Covering a gate insulating layer on the gate and the substrate; forming a source connection layer and a drain connection layer on the gate insulating layer and not contacting each other, wherein the source connection layer and the drain The connecting layer is made of a conductive metal oxide; forming a source on the source connecting layer and the gate insulating layer; forming a drain on the drain connecting layer and the gate insulating layer; and forming A metal oxide semiconductor layer is on the source connection layer, the drain connection layer and the gate insulation layer, wherein the metal oxide semiconductor layer does not contact the source and the drain. The method for fabricating a thin film transistor structure according to claim 11, further comprising: forming at least one protective layer between the source and the gate insulating layer, between the metal oxide semiconductor layer and the gate insulating layer, and the drain And the gate insulating layer or any combination thereof; and connecting the source connecting layer to the source and the metal oxide semiconductor layer, and the drain connecting layer connects the drain and the metal oxide semiconductor layer. The manufacturing method according to claim 11, wherein the step of forming the metal oxide semiconductor layer comprises using an etching method. The manufacturing method of claim 13, wherein the etching method comprises a wet acid etching process, a dry etching process, or any combination of the above processes. The manufacturing method according to claim 14, wherein the etching solution of the wet acid etching process comprises phosphoric acid, acetic acid, nitric acid or any of the above etching solutions. combination.