TWI466085B - Display apparatus and pixel unit thereof - Google Patents

Description

Display device and its pixel unit

The present invention relates to a pixel unit, and more particularly to a pixel unit capable of compensating for leakage current.

In a display device having a plurality of pixels arranged in a matrix matrix type, each pixel includes a switching element disposed at a intersection of a data line (or source line) and a scan line (or gate line). Each of the pixels further includes a pixel electrode formed on the same substrate as the switching element and a common electrode formed on the substrate opposite the pixel electrode. The common electrode is electrically connected to a constant voltage source common to all pixels. The switching element is turned on according to a scan signal on a gate line to which the column of the pixel to which the switching element belongs is connected.

The period during which the switching element is turned on is generally referred to as the "scanning period". During the scanning period, the pixel electrode is electrically connected to the source line of the pixel column to which the pixel electrode belongs, via the switching element, and a signal voltage is applied to the pixel electrode. A potential difference is thus generated between the pixel electrode and the common electrode, and this potential difference drives the display element disposed between the pixel electrode and the common electrode. For example, when the display element is a liquid crystal, the alignment direction of the liquid crystal molecules changes with the potential difference between the pixel electrode and the common electrode, and the amount of transmitted or reflected light also changes, so that the display element can perform display.

In general, switching elements are constructed using thin film transistors (TFTs). However, when a thin film transistor is used, a leak of light caused by light irradiation becomes a problem. When the light is irradiated on the thin film transistor, although the thin film transistor is turned off, the charge stored in the liquid crystal display element and the storage capacitor disposed in parallel with the liquid crystal display element leaks through the thin film transistor to the letter. The line, thus causing crosstalk.

The embodiment of the invention provides a pixel unit, which includes a first switch circuit, a data display circuit and a second switch circuit. The first switch circuit is configured to receive the first switch signal and the data display signal, and determine an on or off state thereof according to the first switch signal, wherein the first switch circuit has a first channel voltage therein. The data display circuit is electrically connected to the first switch circuit, the first signal line and the second signal line, and the data display circuit is configured to receive the data display signal and store the pixel voltage. The second switch circuit is electrically connected to the data display circuit, and the second switch circuit is configured to receive the reference voltage and the switch control signal, and determine the on or off state according to the switch control signal, wherein the second switch circuit has a second channel voltage, And a compensation voltage is provided between the second switch circuit and the data display circuit. When the second switch circuit is turned on, the compensation voltage and the second channel voltage are reset. When the second switch circuit is turned off, the compensation voltage and the second channel voltage are moved to the voltage level of the reference voltage, and the second switch circuit is The compensation current is used to compensate the first leakage current of the first switching circuit so that the pixel voltage can be maintained at its voltage level. .

In one embodiment of the present invention, the pixel unit further includes a reference voltage generating circuit electrically connected to the second switching circuit, and the reference voltage generating circuit receives and determines the output according to the reference voltage control signal. The voltage level of the reference voltage.

In one embodiment of the invention, the first channel voltage is a predetermined fixed voltage, and the first channel voltage is less than the voltage level of the data display signal.

In one embodiment of the present invention, the first switching circuit includes a first transistor, and the control terminal of the first transistor receives the first switching signal, the first One end receives the data display signal, and the second end is electrically connected to the data display circuit, wherein the first channel voltage is the voltage of the channel between the first end and the second end of the first transistor.

In one embodiment of the present invention, the first switching circuit further includes a second transistor, and the control terminal receives the first switching signal, the first end of which receives the data display signal, and the second end of which is electrically connected to the data display circuit, wherein The first channel voltage is the voltage of the channel between the first end and the second end of the second transistor.

In one embodiment of the invention, the data display circuit includes a storage capacitor and a liquid crystal capacitor. The first end of the storage capacitor receives the data display signal, and the second end of the storage capacitor is electrically connected to the second signal line. The first end of the liquid crystal capacitor receives the data display signal, and the second end of the liquid crystal capacitor is electrically connected to the first signal line.

In one of the embodiments of the present invention, the second switching circuit includes a first compensation transistor. The control end of the first compensation transistor receives the switch control signal, the first end of the first compensation transistor is electrically connected to the second signal line, and the second end of the first compensation transistor receives the reference voltage, wherein the second channel voltage is A voltage of the channel between the first end and the second end of the compensation transistor, and a compensation voltage between the first end of the first compensation transistor and the storage capacitor.

In one of the embodiments of the present invention, the second switching circuit includes a second compensation transistor. The control end of the second compensation transistor receives the switch control signal, the first end of the second compensation transistor is electrically connected to the first signal line, and the second end of the second compensation transistor receives the reference voltage, wherein the second channel voltage is the first 2. Compensating for the voltage of the channel between the first end and the second end of the transistor, and having a compensation voltage between the first end of the second compensation transistor and the liquid crystal capacitor.

In one embodiment of the invention, the first signal line is a common electrode line The second signal line is a storage capacitor line. When the first frame period, the switch control signal and the first switch signal are at the same voltage level to synchronously turn on or off the first transistor and the compensation transistor, when the second figure During the frame period, the switch control signal is at a low voltage level to turn off the compensation transistor, wherein the compensation voltage is reset when the compensation transistor is turned on.

In one embodiment of the present invention, the first signal line is a common electrode line, and the second signal line is a scan line. When the first frame period and the second frame period, the switch control signal is a low voltage level, To turn off the compensation transistor.

In one embodiment of the present invention, the first signal line is a common electrode line, and the second signal line is a scan line. When the first frame period and the second frame period, the switch control signal is the same as the first switch signal. The voltage level is used to synchronously turn on or off the first transistor and the second compensation transistor, wherein the compensation voltage is reset when the second compensation transistor is turned on.

In one embodiment of the present invention, during the first frame period indicating the negative frame period, during the second frame period indicating the positive frame period, the first and second frames are continuously interactively switched, and displayed in a frame inversion manner. Picture material.

The embodiment of the invention further provides a display device, which comprises a display panel, a data driving circuit, a scan driving circuit, a reference voltage generating circuit and a control circuit. The display panel has a data line in a first direction and a scan line in a second direction, and the first direction and the second direction are substantially perpendicular to each other, wherein the display panel is configured with at least one pixel unit. The data driving circuit is electrically connected to the display panel, and the data driving circuit is configured to receive and transmit the data driving signal to the pixel unit via the data line according to the first control signal. The scan driving circuit is electrically connected to the display panel, and the scan driving circuit is configured to receive and provide the scan driving signal via the scan line according to the second control signal Transfer to the pixel unit. The reference voltage generating circuit is electrically connected to the pixel unit, and the reference voltage generating circuit receives the reference voltage control signal to determine the voltage level of the reference voltage of the output. The control circuit respectively transmits the first control signal, the second control signal and the reference voltage control signal to the data driving circuit, the scan driving circuit and the reference voltage generating circuit, so that the pixel unit generates a compensation current, wherein the compensation current is used to compensate the pixel unit The first leakage current inside.

In summary, the display device and the pixel unit thereof according to the embodiments of the present invention compensate the first leakage current of the first switching circuit by using the compensation current of the second switching unit, thereby effectively eliminating crosstalk ( Cross talk) and flicker.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. this Terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

[Embodiment of Display Device]

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a display device according to an embodiment of the invention. The display device 100 of the present embodiment includes a display panel 110, a data driving circuit 120, a scan driving circuit 130, a controller 140, and a reference voltage generating circuit 150. The display panel 110 has a plurality of data lines D1 to DM of the first direction DE1 and a plurality of scan lines S1 to SN of the second direction DE2, wherein the first direction DE1 and the second direction DE2 are substantially perpendicular to each other, and the display panel is configured At least one pixel unit 112 is present. The data driving circuit 120 is electrically connected to the display panel 110. The scan driving circuit 130 is electrically connected to the display panel 110. The control circuit 140 is electrically connected to the data driving circuit 120 and the scan driving circuit 130. The reference voltage generating circuit 150 is electrically connected to a plurality of pixel units (such as the pixel unit 112).

The data driving circuit 120 is configured to receive the control signal CS1, and provide a plurality of data driving signals DS1 to DSM according to the control signal CS1 to be transmitted to the display panel 110 via the plurality of data lines D1 to DM, thereby writing the grayscale data voltage into the drawing Prime unit 112.

The scan driving circuit 130 is configured to receive the control signal CS2, and provide a plurality of scan driving signals SS1 to SSN according to the control signal CS2 to be transmitted to the display panel 110 via the plurality of scan lines S1 to SN, thereby the pixels in the display panel 110. Unit 112 is turned on.

The control circuit 140 is configured to receive the original image data DATA and respectively transmit the first control signal CS1, the second control signal CS2, and the reference voltage control signal No. VCS to its corresponding data driving circuit 120, scan driving circuit 130 and reference voltage generating circuit 150. In the present embodiment, the control circuit 140 further transmits a switch control signal to the pixel unit 112, thereby combining the reference voltage VREF output by the reference voltage generating circuit 150 to the pixel unit 112 to cause the pixel unit 112 to generate a compensation current.

The reference voltage generating circuit 150 is configured to receive and determine the voltage level of the reference voltage VREF outputted by the reference voltage control signal VCS transmitted by the control circuit 140.

The scanning driving circuit 130 sequentially transmits the plurality of scanning driving signals SS1 SSSN to the plurality of pixel units of the display panel 110 according to the second control signal CS2 transmitted by the control circuit 140 (eg, The pixel unit 112) is configured to open the pixel unit of each column (the second direction DE2) to enable the grayscale data voltage to be written into the pixel unit, thereby displaying the original image data DATA. However, when the pixel unit is turned off, leakage current is inevitably generated and crosstalk and flickering are caused, thereby affecting the display screen. Therefore, the present disclosure utilizes another leakage current (ie, a compensation current) in the pixel unit to compensate for the original leakage current (ie, the first leakage current) that is originally unavoidable in the pixel unit, thereby effectively improving the display screen. The flickering phenomenon enhances the quality and comfort of the user viewing the display.

For convenience of description, the following will be an example of the implementation of the present disclosure by the pixel unit 112, and those skilled in the art should be able to analogize to the embodiment in which a plurality of pixel units are arranged on the display panel 110.

[An embodiment of a pixel unit]

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a pixel unit according to an embodiment of the present invention. As shown in FIG. 2, the pixel unit 112 includes a first switch circuit 1121, a material display circuit 1122, and a second switch circuit 1123. Data display circuit 1122 is electrically connected to the first switch circuit 1121, the first signal line SL1, and the second signal line SL2. The second switch circuit 1123 is electrically connected to the data display circuit 1122 and the second signal line SL2. In this embodiment, the pixel unit 112 further includes a reference voltage generating circuit 150, and the reference voltage generating circuit 150 is electrically connected to the second switching circuit 1123.

In the disclosure, the first switch circuit 1121 is configured to receive the first switch signal SP and the data display signal DP, wherein the first switch signal SP is one of the plurality of scan drive signals SS1 SSSN, and the data display signal DP is multiple One of the data drive signals DS1~DSM. Incidentally, the first switching circuit 1121 has a first channel voltage CV1, and the first channel voltage CV1 is a predetermined fixed voltage, and the designer can design a preset fixed voltage according to circuit design requirements or actual performance requirements. value. It should be noted that the first channel voltage CV1 in this embodiment is smaller than the voltage level of the data display signal DP.

The data display circuit 1122 is configured to receive the data display signal DP transmitted by the first switch circuit 1121, and store a pixel voltage, thereby displaying the picture data carried by the data display signal DP on the display panel.

The second switching circuit 1123 is configured to receive the reference voltage VREF and the switch control signal SCS, and determine an on or off state according to the switch control signal SCS, wherein the second switch circuit 1123 has a second channel voltage CV2. It is to be noted that the second switching circuit 1123 and the data display circuit 1122 have a compensation voltage FV. The compensation voltage FV is located on the second signal line SL2 in this embodiment, and is located in the first embodiment in another embodiment. The connection mode shown in the embodiment of FIG. 2 is only for convenience of description, and is not intended to limit the disclosure.

The reference voltage generating circuit 150 receives the parameters transmitted from the control circuit The voltage control signal VCS, and adjusts the voltage level of the reference voltage VREF to be output according to the reference voltage control signal VCS.

Next, the related actions of the pixel unit 112 in the present disclosure will be described.

When the first switch circuit 1121 is turned on according to the received first switch signal SP, the first switch circuit 1121 transmits the data display signal DP to the data display circuit 1122, that is, the data display circuit 1122 and the first switch circuit. The voltage between 1121 is a pixel voltage PV indicating the gray scale data voltage, and the data display circuit 1122 can display the pixel voltage PV of the corresponding original picture material. On the other hand, when the first switching circuit 1121 is turned off according to the received first switching signal SP, the pixel voltage PV should be maintained at its voltage level under ideal conditions, but in a non-ideal state at the practical application level. Next, the first switching circuit 1121 generates a first leakage current I1 to lower the voltage level of the pixel voltage PV. Therefore, the present disclosure utilizes the second switch circuit 1123 controlled by the switch control signal SCS to be turned off when the first switch circuit 1121 is turned off, so that the second switch circuit 1123 generates the compensation current I2, thereby compensating the first switch circuit. The first leakage current I1 of 1121 causes the pixel voltage PV to be maintained at its voltage level.

In an embodiment, the disclosure further designs a voltage difference between the pixel voltage PV and the first channel voltage CV1 to be substantially equal to a voltage difference between the compensation voltage FV and the reference voltage VREF, thereby making the compensation current I2 The size can compensate for the magnitude of the first leakage current I2. Briefly, the first leakage current I1 flowing from the data display circuit 1122 is compensated by the compensation current I2 supplied from the second switching circuit 1123 to the data display circuit 1122, thereby maintaining the pixel voltage PV to avoid display. The flickering occurs. It is worth noting that the size of the first channel voltage CV1 and the reference voltage VREF must be adapted by the designer. The design, and the enable period and the disable period of the switch control signal SCS must also be matched with the first switch signal SP, so that the compensation current I2 of the second switch circuit 1123 (when turned off) can compensate the first switch circuit 1121 ( The first leakage current I1 when turned off, and the pixel voltage PV can be maintained at its voltage level.

In order to explain in more detail the operational flow of the pixel unit 112 with compensated leakage current as described in the present disclosure, at least one of the following embodiments will be further described.

In the following various embodiments, portions different from the above-described embodiments of Figs. 1 and 2 will be described, and the remaining omitted portions are the same as those of the above-described embodiments of Figs. 1 and 2. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[An embodiment of a pixel unit]

Please refer to FIG. 3. FIG. 3 is a schematic diagram of a detailed circuit of a pixel unit according to an embodiment of the present invention. As shown in FIG. 3, the first switching unit 1121 includes a first transistor M1 and a second transistor M2. The data display circuit 1122 includes a storage capacitor CS and a liquid crystal capacitor CLC. The second switching circuit 1123 includes a compensation transistor M3. The control terminal of the first transistor M1 receives the first switch signal SP, the first end of the first transistor M1 receives the data display signal DP, and the second end of the first transistor M1 is electrically connected to the data display circuit 1122. The control terminal of the second transistor M2 receives the first switch signal SP, the first end of the second transistor M2 receives the data display signal DP, and the second end of the second transistor M2 is electrically connected to the data display circuit 1122.

It should be noted that the first switching unit 1121 in the disclosure is not limited to the two transistors M1 and M2. In another embodiment, the first switching unit may be a first transistor M1 or a second transistor M2, and in the embodiment, the second transistor is connected in series with the first transistor M1. The body M2 is exemplified, that is, the first transistor M1 transmits the received data display signal DP to the second transistor M2, and the second transistor M2 transmits the data display signal DP to the data display circuit 1122. . It should be understood by those skilled in the art that the voltage of the channel between the first end and the second end of the first transistor M1 is the first channel voltage CV1, and the first end and the second end of the second transistor M2. The voltage between the channels is the first channel voltage CV1.

The first end of the storage capacitor CS in the data display circuit 1122 receives the data display signal DP, and the second end of the storage capacitor CS is electrically connected to the second signal line SL2.

The first end of the liquid crystal capacitor CLC in the data display circuit 1122 receives the data display signal DP, and the second end of the liquid crystal capacitor CLC is electrically connected to the first signal line SL1.

The control terminal of the compensation transistor M3 receives the switch control signal SCS, the first end of the compensation transistor M3 is electrically connected to the second signal line SL2, and the second end of the compensation transistor M3 receives the reference voltage VREF, wherein the compensation transistor M3 is There is a compensation voltage FV between one end and the storage capacitor CS. It should be understood by those of ordinary skill in the art that the voltage of the channel between the first end and the second end of the compensation transistor M3 is the second channel voltage CV2.

For convenience of explaining the related actions of the embodiment of FIG. 3, please refer to FIG. 3 and FIG. 4 at the same time. 4 is a driving waveform diagram of a driving pixel unit according to an embodiment of the present invention. Before the following description is made, it should be noted that the first signal line SL1 of the present embodiment is a common electrode line, the second signal line SL2 is a storage capacitance line, and the first frame period F1 indicates a negative frame period. And the second frame period F2 indicates a positive frame period, and the first frame period F1 and the second frame period F2 are continuously interactively switched with each other, and the frame inversion manner is used to display the picture element. material. That is to say, the signal driving mechanism during the third frame is like the first frame period F1, and the signal driving mechanism during the fourth frame period is like the second frame period F2.

When the time interval T1 of the first frame period F1, the first transistor M1 and the second transistor M2 are turned on according to the received first switching signal SP, and the first transistor M1 displays the data signal. The DP transmits the second transistor M2, and then the second transistor M2 transmits the material display signal DP to the material display unit 1122 to write the liquid crystal capacitor CLC. Accordingly, the liquid crystal capacitor CLC generates a pixel voltage PV corresponding to the original picture material. At the same time, in the time interval T1, the switch control signal SCS can compensate the transistor M3 to turn on the compensation transistor M3, and then reset the second channel by using the reference voltage VREF of the voltage VL1 (such as 0 volt) of the low voltage level. The voltage CV2 and the compensation voltage FV are such that the voltage level of the second channel voltage CV2 and the compensation voltage FV is 0 volt, wherein the reference voltage generating circuit 150 adjusts the output reference voltage according to the reference voltage control signal VCS transmitted by the control circuit. VREF.

Then, when entering the time interval T2, the first switching signal SP disables the first and second transistors M1, M2 and the switch control signal SCS disables the compensation transistor M3 to turn off the compensation transistor, the second channel voltage CV2 and The compensation voltage FV is instantaneously reduced due to the feed through. Thereafter, since the reference voltage VREF is at a voltage level of 0 volts, the second channel voltage CV2 and the compensation voltage FV will move toward the voltage VL1 of the reference voltage VREF (ie, the voltage rises), and the transient in which the voltage rises In the process, the compensation transistor M3 generates a compensation current I2 to compensate for the first leakage current I1. Further, in the time interval T2, the first transistor M1 and the second transistor M2 may be between the pixel voltage PV and the first channel voltage CV1. Having a potential difference causes a first leakage current I1 to be generated between the liquid crystal capacitor CLC (or the storage capacitor CS) and the first transistor M1 and the second transistor M2, and the first leakage current I1 can be compensated by the compensation current I2 And the pixel voltage PV can be maintained at its voltage level.

When entering the time interval T3, the switch control signal SCS continues to disable the compensation transistor M3, since the second channel voltage CV2 of the compensation transistor M3 has risen to the same voltage level as the reference voltage VREF (ie 0 volts) And a potential difference between the second channel voltage CV2 and the compensation voltage FV, so the compensation transistor M3 generates a compensation current I2, and charges the storage capacitor CS, so that the compensation voltage FV rises until the voltage level of the compensation voltage FV is The voltage level of the second channel voltage CV2 is the same. Accordingly, the first leakage current I1 is compensated by the compensation current I2 generated by the compensation transistor M3. Incidentally, during the first frame period F1, the switch control signal SCS and the first switch signal SP are driving waveforms of the same voltage level, thereby synchronously turning on or off the first transistor M1 and the compensation transistor M3. .

When entering the time interval T4 of the second frame period F2, the first transistor M1 and the second transistor M2 are turned on again according to the received first switching signal SP. Similarly, the first transistor M1 will The data display signal DP transmits the second transistor M2, and then the second transistor M2 transmits the data display signal DP to the data display unit 1122 to write the liquid crystal capacitor CLC, according to which the liquid crystal capacitor CLC generates a corresponding data of the picture. Pixel voltage PV. Meanwhile, in the time interval T4, the switch control signal SCS continues to disable the compensation transistor M3 to turn off the compensation transistor M3, and it should be noted that the reference voltage generating circuit 150 receives and controls according to the reference voltage transmitted by the control circuit. The signal VCS switches the voltage level of the reference voltage VREF to the voltage VH1 of the high voltage level. Then, when the reference voltage VREF After the voltage level is switched to the voltage VH1 of the high voltage level, the second channel voltage CV2 and the compensation voltage FV will move to the voltage VH1. That is to say, in the time interval T4, the compensation transistor M3 generates a compensation current I2 to compensate the first leakage current I1 generated by the first transistor M1 and the second transistor M2, thereby stabilizing the pixel voltage PV, so that the The pixel voltage PV can be maintained at its voltage level, thereby improving the occurrence of flicker and crosstalk, and improving the quality and comfort of the user viewing the display screen.

It is worth mentioning that, in some time intervals, the voltage difference between the pixel voltage PV and the first channel voltage CV1 is substantially equal to the voltage difference between the compensation voltage FV and the second channel voltage CV2. The related technical feature further makes the number of first leakage currents close to the number of compensation currents, thereby further improving the flicker phenomenon of the display screen.

In short, it does not deviate from the use of the compensation current I2 generated by the second switching unit 1123 to compensate the first leakage current I1 generated by the first switching unit 1121, which is within the scope of the technical idea of the present invention.

In order to teach the operation of the pixel unit having the mechanism of compensating for leakage current as described in more detail, another embodiment will be further described below.

[Another embodiment of a pixel unit]

Please refer to FIG. 3 and FIG. 5 simultaneously. FIG. 5 is a driving waveform diagram of a driving pixel unit according to another embodiment of the present invention. Before the following description, it should be noted that the first signal line SL1 of the present embodiment is a common electrode line, the second signal line SL2 is a scan line, and the first frame period F1 indicates a negative frame period. The second frame period F2 indicates a positive frame period, and the first frame period F1 and the second frame period F2 are continuously interactively switched with each other, and the screen material is displayed in a frame inversion manner. That is, the signal during the third frame The driving mechanism is like the first frame period F1, and the signal driving mechanism during the fourth frame period is like the second frame period F2. It should be noted that the switch control signal SCS of the present embodiment is at a low voltage level during the first frame period F1 and the second frame period F2, that is, the compensation transistor M3 is always in the disabled state.

When the time interval T5 of the first frame period F1, the first transistor M1 and the second transistor M2 are turned on according to the received first switching signal SP, and the first transistor M1 displays the data signal. The DP transmits the second transistor M2, and then the second transistor M2 transmits the material display signal DP to the material display unit 1122 to write the liquid crystal capacitor CLC. Accordingly, the liquid crystal capacitor CLC generates a pixel voltage PV corresponding to the original picture material. Meanwhile, in the time interval T5, the switch control signal SCS disables the compensation transistor M3 to turn off the compensation transistor M3, and the reference voltage generation circuit 150 outputs the voltage VL2 according to the reference voltage control signal VCS transmitted by the control circuit. Reference voltage VREF.

Then, when entering the time interval T6, the first switching signal SP disables the first and second transistors M1, M2 and the switch control signal SCS continues to disable the compensation transistor M3. Then, since the first transistor M1 and the second transistor M2 have a potential difference between the pixel voltage PV and the first channel voltage CV1, the liquid crystal capacitor CLC (or the storage capacitor CS) and the first transistor M1 are A first leakage current I1 is generated between the second transistors M2. In this embodiment, at this time, the voltage level of the reference voltage VREF is the voltage VL2, so the second channel voltage CV2 and the compensation voltage FV will move toward the voltage VL2 of the reference voltage VREF (ie, the voltage rises), here During the transient process of voltage rise, the compensation transistor M3 generates a compensation current I2 to compensate for the first leakage current I1.

When entering the time interval T7, the switch control signal SCS continues to disable the compensation transistor M3 to turn off the compensation transistor M3. However, since the second signal line SL2 of the embodiment is a scan line, during the time interval T7, the scan line (ie, the second signal line SL2) sends a high voltage level enable signal to turn on the next column. Pixel elements. Therefore, the compensation voltage FV will rise to a higher voltage level than the voltage VL2, at which time the compensation transistor M3 does not generate the compensation current I2. It is to be noted that, in the present embodiment, the scanning line as the second signal line SL2 is not a signal line for transmitting the first switching signal SP in this embodiment.

When entering the time interval T8 of the second frame period F2, the first transistor M1 and the second transistor M2 are turned on again according to the received first switching signal SP. Similarly, the first transistor M1 will The data display signal DP transmits the second transistor M2, after which the second transistor M2 transmits the data display signal DP to the data display unit 1122 to write the liquid crystal capacitor CLC, according to which the liquid crystal capacitor CLC generates a corresponding original picture data. Pixel voltage PV. Meanwhile, during the time interval T8, the switch control signal SCS continues to disable the compensation transistor M3 to turn off the compensation transistor M3, and it should be noted that the reference voltage generating circuit 150 receives and controls according to the reference voltage transmitted by the control circuit. The signal VCS switches the voltage level of the reference voltage VREF to the voltage VH2 of the high voltage level. Then, after the voltage level of the reference voltage VREF is switched to the voltage VH2 of the high voltage level, the second channel voltage CV2 and the compensation voltage FV are moved to the voltage VH2 of the high voltage level. That is to say, in the time interval T8, the compensation transistor M3 generates the compensation current I2 to compensate the first leakage current I1 generated by the first transistor M1 and the second transistor M2, thereby stabilizing the pixel voltage PV, thereby improving Flashing and crosstalk occur.

When entering the time interval T9 of the second frame period F2, the switch control signal SCS continues to disable the compensation transistor M3 to turn off the compensation transistor M3. However, since the second signal line SL2 of the embodiment is a scan line, during the time interval T9, the scan line (ie, the second signal line SL2) sends a high voltage level enable signal to turn on the next column. Pixel elements. Therefore, the compensation voltage FV will rise to a higher voltage level than the voltage VH2, at which time the compensation transistor M3 does not generate the compensation current I2.

In the following various embodiments, portions different from the above-described embodiments of Figs. 1 to 5 will be described, and the remaining omitted portions are the same as those of the above-described embodiments of Figs. In addition, for the sake of convenience, like reference numerals or numerals indicate similar elements.

[Another embodiment of the pixel unit]

Please refer to FIG. 6. FIG. 6 is a schematic diagram of a pixel unit according to still another embodiment of the present invention. The second switch circuit 1123 of the present embodiment is electrically connected to the first signal line SL1 and the second switch circuit 1123 and the data display circuit, in addition to being electrically connected to the data display circuit 1122. There is a compensation voltage FV between 1122. The pixel unit operation of this embodiment is similar to the embodiment of FIG. 2, and is not a problem here. Next, another figure will be specifically described to further explain the detailed operation of the embodiment of Fig. 6.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of a detailed circuit of a pixel unit according to still another embodiment of the present invention. Different from the above embodiment of FIG. 3, the second switching unit 1123 includes a compensation transistor M4, and the control terminal of the compensation transistor M4 receives the switch control signal SCS, and the first end of the compensation transistor M4 is electrically connected to the first signal line. SL1, the second end of the compensation transistor M4 receives the reference voltage VREF, wherein the compensation transistor F4 has a compensation voltage FV between the first end and the liquid crystal capacitor CLC. Those with ordinary knowledge in the field should understand, make up The voltage of the channel between the first end and the second end of the compensating crystal M4 is the second channel voltage CV2.

For convenience of explaining the related actions of the embodiment of FIG. 7, please refer to FIG. 7 and FIG. 8 at the same time. FIG. 8 is a driving waveform diagram of a driving pixel unit according to still another embodiment of the present invention.

Before the following description, it should be noted that the first signal line SL1 of the present embodiment is a common electrode line, the second signal line SL2 is a scan line, and the first frame period F1 indicates a negative frame period. The second frame period F2 indicates a positive frame period, and the first frame period F1 and the second frame period F2 are continuously interactively switched with each other, and the screen material is displayed in a frame inversion manner.

When the time interval T10 of the first frame period F1, the first transistor M1 and the second transistor M2 are turned on according to the received first switching signal SP, and the first transistor M1 displays the data signal. The DP transmits the second transistor M2, after which the second transistor M2 transmits the material display signal DP to the material display unit 1122 to write the liquid crystal capacitor CLC. Accordingly, the liquid crystal capacitor CLC generates a pixel voltage PV corresponding to the original picture material. At the same time, in the time interval T10, the switch control signal SCS will enable the compensation of the transistor M3 to turn on the compensation transistor M3, and then use the voltage level of 0 volts to reset the two-channel voltage CV2 and the compensation voltage FV, so that the second The voltage level of the channel voltage CV2 and the compensation voltage FV is 0 volt, wherein the reference voltage generating circuit 150 adjusts the output reference voltage VREF according to the reference voltage control signal VCS transmitted by the control circuit.

Next, when entering the time interval T11, the first switching signal SP disables the first and second transistors M1, M2 and the switch control signal SCS disables the compensation transistor M3 to turn off the compensation transistor M3. At this time, since the reference voltage generating circuit 150 receives and controls according to the reference voltage transmitted by the control circuit The signal VCS is used to switch the reference voltage VREF to the voltage VL3 of the low voltage level, so the second channel voltage CV2 and the compensation voltage FV will move to the voltage VL3 of the reference voltage VREF. During this transient process, the compensation transistor M3 will A compensation current I2 is generated to compensate for the first leakage current I1. Further, in the time interval T11, the first transistor M1 and the second transistor M2 may have a liquid crystal capacitor CLC (or a storage capacitor CS) due to a potential difference between the pixel voltage PV and the first channel voltage CV1. A first leakage current I1 is generated between the first transistor M1 and the second transistor M2, and the first leakage current I1 can be compensated by the compensation current I2.

When entering the time interval T12, the compensation transistor M3 is turned on by the switch control signal SCS and the first transistor M1 and the second transistor M2 are turned on by the first switch signal, and then, first The transistor M1 transmits the data display signal DP to the second transistor M2, after which the second transistor M2 transmits the material display signal DP to the data display unit 1122 to write the liquid crystal capacitor CLC. At the same time, the reference voltage generating circuit 150 receives and switches the reference voltage VREF to a voltage having a voltage level of 0 volt according to the reference voltage control signal VCS transmitted by the control circuit to reset the second channel voltage CV2 and the compensation voltage FV.

Next, when entering the time interval T13, the first switching signal SP disables the first and second transistors M1, M2 and the switch control signal SCS disables the compensation transistor M3 to turn off the compensation transistor M3. The closing of the first transistor M1 and the second transistor M2 causes a potential difference between the pixel voltage PV and the first channel voltage CV1, thereby generating a first leakage current I1. Therefore, in the present embodiment, since the reference voltage generating circuit 150 receives and switches the reference voltage VREF to the high voltage level voltage VH3 according to the reference voltage control signal VCS transmitted by the control circuit, the second channel voltage CV2 and the compensation voltage FV will move to the voltage VL3 of the reference voltage VREF. During this transient process, the compensation transistor M3 will generate the compensation current I2 to compensate the first leakage current I1.

It is worth mentioning that during the first frame period F1 and the second frame period, the switch control signal SCS and the first switch signal SP are driving waveforms of the same voltage level to synchronously turn on or off the transistors M1, M2 and M4. When the time interval T10 and T12, the second channel voltage CV2 and the compensation voltage FV are reset, so that when entering the time intervals T11 and T13 respectively, the second channel voltage CV2 and the compensation voltage FV will be compared with the reference voltage VREF (eg There is a voltage difference between the voltages VL3 and VH3), so that the compensation transistor M4 in the off state generates the compensation current I2, thereby being able to compensate the first leakage current I1.

[Possible effects of the examples]

In summary, the display device and the pixel unit thereof provided by the embodiments of the present invention can compensate the first leakage generated by the first switching unit in the closed state by using the compensation current generated by the second switching unit in the off state. Current. Furthermore, the designer can design the voltage difference between the pixel voltage and the first channel voltage to be substantially equal to the compensation voltage FV and the second channel voltage in some time intervals according to the circuit design requirement and the actual performance requirement. The voltage difference between CV2, so that the number of first leakage currents is close to the number of compensation currents, and the pixel voltage PV can be maintained at its voltage level, thereby effectively improving crosstalk phenomenon and display. The flickering of the screen enhances the quality and comfort of the user viewing the display.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

100‧‧‧ display device

110‧‧‧ display panel

112‧‧‧ pixel unit

1121‧‧‧First switch circuit

1122‧‧‧Information display circuit

1123‧‧‧Second switch circuit

120‧‧‧Data Drive Circuit

130‧‧‧Scan drive circuit

140‧‧‧Control circuit

150‧‧‧reference voltage generation circuit

CS1‧‧‧First control signal

CS2‧‧‧second control signal

CV1‧‧‧first channel voltage

CV2‧‧‧second channel voltage

CS‧‧‧ Storage Capacitor

CLC‧‧‧Liquid Crystal Capacitor

D1~DM‧‧‧ data line

DATA‧‧‧ original image data

DE1‧‧‧ first direction

DE2‧‧‧ second direction

DP‧‧‧ data display signal

DS1~DSM‧‧‧ data drive signal

FV‧‧‧compensation voltage

F1‧‧‧The first frame period

F2‧‧‧The second frame period

I1‧‧‧First leakage current

I2‧‧‧Compensation current

M1, M2‧‧‧ transistor

M3, M4‧‧‧ compensation transistor

PV‧‧‧ pixel voltage

SCS‧‧‧ switch control signal

S1~SN‧‧‧ scan line

SL1‧‧‧first signal line

SL2‧‧‧second signal line

SP‧‧‧First switch signal

SS1~SSM‧‧‧ scan drive signal

T1~T13‧‧‧ time interval

VCS‧‧‧ reference voltage control signal

VREF‧‧‧reference voltage

VL1, VL2, VL3, VH1, VH2, VH3‧‧‧ voltage

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, in which FIG.

1 is a schematic diagram of a display device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a pixel unit in accordance with an embodiment of the present invention.

3 is a schematic diagram of a detailed circuit of a pixel unit in accordance with an embodiment of the present invention.

4 is a driving waveform diagram of a driving pixel unit according to an embodiment of the present invention.

FIG. 5 is a driving waveform diagram of a driving pixel unit according to another embodiment of the present invention.

6 is a schematic diagram of a pixel unit in accordance with still another embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of a pixel unit according to still another embodiment of the present invention.

FIG. 8 is a driving waveform diagram of a driving pixel unit according to still another embodiment of the present invention.

112‧‧‧ pixel unit

1121‧‧‧First switch circuit

1122‧‧‧Information display circuit

1123‧‧‧Second switch circuit

150‧‧‧reference voltage generation circuit

CV1‧‧‧first channel voltage

CV2‧‧‧second channel voltage

DP‧‧‧ data display signal

FV‧‧‧compensation voltage

I1‧‧‧First leakage current

I2‧‧‧Compensation current

PV‧‧‧ pixel voltage

SCS‧‧‧ switch control signal

SL1‧‧‧first signal line

SL2‧‧‧second signal line

SP‧‧‧First switch signal

VCS‧‧‧ reference voltage control signal

VREF‧‧‧reference voltage

Claims (13)

A pixel unit includes: a first switch circuit for receiving a first switch signal and a data display signal, and determining an on or off state according to the first switch signal, wherein the first switch circuit has a a first channel voltage, the first channel voltage is a predetermined fixed voltage, and the first channel voltage is less than a voltage level of the data display signal; a data display circuit electrically connecting the first switch circuit, a first a signal line and a second signal line, the data display circuit is configured to receive the data display signal and store a pixel voltage; and a second switch circuit electrically connected to the data display circuit, the second switch circuit is configured to receive a reference voltage and a switch control signal, and according to the switch control signal to determine an on or off state thereof, wherein the second switch circuit has a second channel voltage, and the second switch circuit and the data display circuit Having a compensation voltage; wherein, when the second switching circuit is turned on, resetting the compensation voltage and the second channel voltage when the second opening When the circuit is turned off, the compensation voltage and the voltage of the second channel are moved to the voltage level of the reference voltage, so that the second switching circuit generates a compensation current for compensating for a first leakage current generated by the first switching circuit. So that the pixel voltage can be maintained at its voltage level. The pixel unit of claim 1, further comprising: a reference voltage generating circuit electrically connected to the second switching circuit, the reference voltage generating circuit receiving and determining the output according to a reference voltage control signal The voltage level of the reference voltage. The pixel unit of claim 1, wherein the first switch power The circuit includes: at least one transistor, the control end receives the first switch signal, the first end thereof receives the data display signal, and the second end thereof is electrically connected to the data display circuit, wherein the first channel voltage is the transistor The voltage of the channel between the first end and the second end. The pixel unit of claim 3, wherein the first switching circuit cascades a plurality of transistors, and the control terminals of the transistors collectively receive the first switching signal, and one end receives the same The data display signal, and the other end is electrically connected to the data display circuit, wherein each of the electro-crystalline systems has the first channel voltage, and the first channel voltage is between the first end and the second end of each transistor The voltage of the channel. The pixel unit of claim 3, wherein the data display circuit comprises: a storage capacitor, the first end receives the data display signal, and the second end is electrically connected to the second signal line; and The liquid crystal capacitor has a first end receiving the data display signal and a second end electrically connected to the first signal line. The pixel unit of claim 5, wherein the second switching circuit comprises: a first compensation transistor, wherein the control terminal receives the switch control signal, and the first end thereof is electrically connected to the second signal line The second terminal receives the reference voltage, wherein the second channel voltage is a voltage of a channel between the first end and the second end of the first compensation transistor, and the first end of the first compensation transistor is The compensation capacitor has the compensation voltage. The pixel unit of claim 5, wherein the second switch circuit comprises: a second compensation transistor, the control terminal receives the switch control signal, the first end thereof is electrically connected to the first signal line, and the second end thereof receives the reference voltage, wherein the second channel voltage is the second compensation power a voltage of a channel between the first end and the second end of the crystal, and the compensation voltage is provided between the first end of the second compensation transistor and the liquid crystal capacitor. The pixel unit of claim 6, wherein the first signal line is a common electrode line, and the second signal line is a storage capacitor line. When a first frame period, the switch control signal is The first switching signal is at the same voltage level to synchronously turn on or off the first transistor and the first compensation transistor. When a second frame period, the switch control signal is at a low voltage level for The first compensation transistor is turned off, wherein the compensation voltage is reset when the first compensation transistor is turned on. The pixel unit of claim 6, wherein the first signal line is a common electrode line, and the second signal line is a scan line, when a first frame period and a second frame period The switch control signal is at a low voltage level for turning off the first compensation transistor. The pixel unit of claim 7, wherein the first signal line is a common electrode line, and the second signal line is a scan line, when a first frame period and a second frame period are The switch control signal and the first switch signal are at the same voltage level to synchronously turn on or off the first transistor and the second compensation transistor, wherein the compensation voltage is when the second compensation transistor is turned on Will be reset. The pixel unit of claim 8, wherein the first frame period indicates a negative frame period, and the second frame period indicates a positive frame period, the first and the During the second frame period, the interactive switching is continued, and the screen data is displayed in a frame inversion manner. A display device includes: a display panel having a plurality of data lines in a first direction and a plurality of scan lines in a second direction, wherein the first direction and the second direction are substantially perpendicular to each other, wherein the display panel Configuring at least one pixel unit; a data driving circuit electrically connected to the display panel, the data driving circuit is configured to receive and send a plurality of data driving signals to the picture via the data lines according to a first control signal a scanning unit, electrically connected to the display panel, the scan driving circuit is configured to receive and provide a plurality of scan driving signals to the pixel unit via the scan lines according to a second control signal; a reference voltage generating circuit electrically connected to the pixel unit, the reference voltage generating circuit receiving a reference voltage control signal to determine a voltage level of a reference voltage of the output thereof, and a control circuit for respectively transmitting the first control signal And the second control signal and the reference voltage control signal to the data driving circuit, the scan driving circuit and the reference voltage a circuit for causing the pixel unit to generate a compensation current, wherein the compensation current is used to compensate for a first leakage current in the pixel unit; wherein the pixel unit comprises: a first switching circuit for receiving a a first switching signal and a data display signal, and determining an on or off state thereof according to the first switching signal, wherein the first switching circuit has a first channel voltage, and the first channel voltage is a predetermined fixed voltage, And the first channel voltage is less than the voltage level of the data display signal; a data display circuit is electrically connected to the first switch circuit, a first signal line and a second signal line, and the data display circuit is configured to receive the a data display signal; and a second switch circuit electrically connected to the data display circuit, the second switch circuit is configured to receive the reference voltage, and determine a turn-on or turn-off state according to a switch control signal transmitted by the control circuit The second switch circuit has a second channel voltage, and the second switch circuit and the data display circuit have a compensation voltage, wherein the first switch signal is one of the scan drive signals, and the The data display signal is one of the data driving signals. The display device of claim 12, wherein when the second switch circuit is turned off, the compensation voltage and the second channel voltage are reset, and when the second switch circuit is turned on, the compensation voltage is And the voltage of the second channel is moved to a voltage level of the reference voltage, and the compensation current of the second switching circuit is used to compensate the first leakage current of the first switching circuit.