TWI463331B - Simulation system and method for soc - Google Patents

Description

System single chip simulation system and method

The present invention relates to analog systems and methods for system single wafers, and more particularly to analog systems and methods for system interruptable interrupted single wafers.

Due to the continuous evolution of the process and the increasing demand for system functions by the client, more and more Silicon Intellectual Property (IP) is integrated into the System on Chip (SoC), thus increasing the design. the complexity.

In the traditional chip design process, the system performance evaluation often needs to wait for the hardware prototype development board (such as the development board with Field Programmable Gate Array (FPGA)) to complete the integration verification of the system software. analysis. However, the verification cycle of the entire system is quite time consuming. In addition, hardware prototyping boards can only provide functional verification and do not provide true execution speed. Therefore, in the early stage of system design and planning, an electronic platform (Electroniuc Systrem Level) virtual platform capable of rapid simulation, convenient observation and analysis, and flexible adjustment of system architecture and specifications is needed, which can help system chip designers. Define a high-performance system architecture, avoid multiple repetitive designs, and provide a system-level software development environment to shorten the overall system design and development cycle.

In the chip design process, a register transfer level (RTL) or a Transaction Level Modeling (TLM) is generally used to establish a system single-chip analog system, in which a representative register is used. The transport hierarchy uses Verilog-HDL, and the representative handler hierarchy model uses the programming language System C. Compared to the scratchpad transport hierarchy, the handler level model provides a higher level of abstraction, which in turn reduces the complexity of system single-chip development. By processing the program level model technology, system designers can easily modify the system architecture, conduct experiments, and collect data during the architecture design phase to analyze and improve the system. In addition, with the help of the hardware platform developed by the processor level model technology, software engineers can use this platform to start writing applications after the architecture design phase.

In general, in an analog system composed of a handler level model, data transfer between different platforms is performed through a transaction. However, the interrupt between different platforms cannot be transmitted through the conversion method, so the processors of different platforms cannot be interrupted interactively, so that the analog system cannot be regarded as a complete system, that is, the system single chip cannot be simulated. The complete operation of the Lieutenant Intelligence Unit.

Therefore, there is a need for a simulation method that establishes an interaction interrupt in a hybrid system with a handler level model.

The present invention provides a system and method for simulating a single wafer of a system. A system single-chip simulation system provided by the present invention includes a processing program level model virtual platform and a scratchpad transmission level entity platform coupled to the processing program level model virtual platform. The processing program level model virtual platform includes: a virtual processor; a virtual design unit; and an interrupt agent for converting a virtual interrupt signal from the virtual design unit into a first interrupt data packet. The above-mentioned register transfer level entity platform includes: a physical design unit; an interrupt converter for generating a first interrupt corresponding to one of the virtual interrupt signals according to the first interrupt data packet; and an entity processor A first interrupt routine is executed in response to the first interrupt described above.

Furthermore, the present invention provides another system single-chip simulation system including a processing program level model virtual platform and a scratchpad transmission level entity platform coupled to the processing program level model virtual platform. The above-mentioned register transfer level physical platform includes: a physical design unit; and an interrupt converter for converting a physical interrupt signal from the physical design unit into an interrupt data packet. The processing program level model virtual platform includes a virtual design unit; an interrupt agent for generating an interrupt corresponding to the physical interrupt signal according to the interrupt data packet; and a virtual processor for controlling the virtual design unit And executing an interrupt program corresponding to the above interrupt.

Furthermore, the present invention provides a simulation method suitable for combining one of the processing program level model virtual platform and one of the system single chip simulation systems of the scratchpad transmission level physical platform. In the processing program level model virtual platform, a virtual interrupt signal from a virtual design unit is converted into a first interrupt data packet. Transmitting the first interrupt data packet from the processing program level model virtual platform to the scratchpad transport level entity platform according to a specific communication protocol. In the above-mentioned register transfer level entity platform, a first interrupt corresponding to one of the virtual interrupt signals is generated according to the first interrupt data packet. In the above-mentioned register transfer level entity platform, a first interrupt program is executed corresponding to the first interrupt.

Furthermore, the present invention provides another simulation method suitable for combining one of the processing program level model virtual platform and one of the system single chip simulation systems of the scratchpad transmission level physical platform. In the above-mentioned scratchpad transport level entity platform, a physical interrupt signal from a physical design unit is converted into an interrupt data packet. The interrupt data packet is transmitted to the processing program level model virtual platform according to a specific communication protocol. In the processing program level model virtual platform, an interrupt corresponding to one of the physical interrupt signals is generated according to the interrupt data packet. In the above-mentioned handler level model virtual platform, an interrupt program is executed corresponding to the above interrupt.

The above and other objects, features and advantages of the present invention will become more <RTIgt; A system single chip (SoC) simulation system 100 according to an embodiment of the invention. The simulation system 100 includes a handler level model (TLM) virtual platform 10 and a scratchpad transport level (RTL) entity platform 20. In this embodiment, the handler level model virtual platform 10 is implemented by a computer device equipped with a programming language System C engine, such as a computer with a Linux operating system, and the scratchpad transport level physical platform 20 has a field. The hardware platform of the program gate array (FPGA) is implemented, wherein the processor level model virtual platform 10 is coupled to the scratchpad transport level physical platform 20 via a Peripheral Component Interconnect (PCI) bus bar 30. In addition, the processor level model virtual platform 10 can be regarded as a cycle approximate (CX) platform, and the scratchpad transmission level physical platform 20 can be regarded as a cycle accurate (CA) platform. In other embodiments, the handler level model virtual platform 10 can also be connected to the scratchpad transport level entity platform 20 through other connection methods, such as a Universal Serial Bus (USB) or a network.

The handler level model virtual platform 10 includes an instruction set simulator (ISS) 110, a software entity to be verified 120A-120C, an interrupt agent 130, and a vectored interrupt controller (Vectored Interrupt Controller, The VIC) 140 and the driver 150, wherein the instruction set simulator 110 can be considered a virtual processor, and the software entity 120A-120C can be considered a virtual design unit that is intended to be integrated into a system single chip. The instruction set simulator 110 transmits data to the software entity 120A-120C through the bus bar 115, and controls the software entity 120A-120C. In addition, the data to be transmitted to the scratchpad transport level physical platform 20 is also transmitted to the bus bar agent (not shown) through the bus bar 115, and then transmitted to the scratchpad transport level entity platform via the driver 150 and the PCI bus bar 30. 20.

The scratchpad transport level physical platform 20 includes a processor 210, a hardware unit 220A-220C, a transactor 230, a vector interrupt controller 240, and a wafer level converter 250, wherein the hardware unit The 220A-220C can be programmed into a field programmable gate array (FPGA), which is a physical unit that has been developed or verified to be integrated into a single wafer of the system. Similarly, the processor 210 can perform data transfer with the hardware and smart unit 220A-220C through the bus bar 215. In addition, the data to be transmitted to the processor level model virtual platform 10 is also transmitted to the bus bar converter (not shown) through the bus bar 215, and then transmitted to the processor level model virtual via the chip level converter 250 and the PCI bus bar 30. Platform 10.

2 is a schematic diagram showing an interaction interrupt trigger path according to an embodiment of the present invention in FIG. 1 , which indicates that any software entity in the processing level model virtual platform 10 generates an interrupt and transmits to the temporary The processor transports the processor 210 within the hierarchical entity platform 20 for subsequent processing. Referring to FIG. 1 and FIG. 2 simultaneously, first, the software entity 120A, 120B or 120C provides the interrupt signal S _INT1 to the interrupt agent 130 via the bus bar 125. Next, the interrupt agent 130 determines whether the interrupt signal S _INT1 is to be transferred to the instruction set simulator 110 or to the processor 210 within the scratchpad transport level entity platform 20. When the interrupt signal S _INT1 is to be transferred to the processor 210 in the scratchpad transport level entity platform 20, the interrupt proxy 130 converts the interrupt signal S _INT1 into the interrupt data packet P1 and transfers it to the scratchpad transport level. The converter 230 is interrupted within the physical platform 20. In Fig. 2, the operation of the driver 150, the bus bar 30, and the wafer level converter 250 will be omitted and will be described later for simplicity of explanation. Then, after receiving the interrupt data packet P1, the interrupt converter 230 converts the interrupt data packet P1 back to the interrupt signal S _INT1 and transmits it to the vector interrupt controller 240. Next, vector interrupt controller 240 interrupts INT1 interrupt signal _INT1 is generated according to the S and the priority of their arrangement, so as to provide the processor 210 to interrupt INT1. Thus, upon receiving the interrupt INT1, the processor 210 can execute the interrupt routine corresponding to the interrupt INT1. On the other hand, when the interrupt signal S _INT1 is to be transferred to the instruction set simulator 110, the interrupt proxy 130 transmits the interrupt signal S _INT1 to the vector interrupt controller 140 (as indicated by the dashed line), such that the vector interrupt controller 140 The interrupt _INT1 can be generated to the instruction set simulator 110 according to the interrupt signal S _INT1 and its priority can be controlled. Thus, the instruction set simulator 110 can execute the interrupt routine corresponding to the interrupt INT1.

3 is a schematic diagram showing an interaction interrupt trigger path according to another embodiment of the present invention in FIG. 1 , which indicates that any hardware entity in the scratchpad transport level entity platform 20 generates an interrupt and The instruction set simulator 110 within the handler level model virtual platform 10 is passed for subsequent processing. Referring to FIG. 1 and FIG. 3 simultaneously, first, the hardware unit 220A, 220B or 220C provides the interrupt signal S _INT2 to the interrupt converter 230 via the bus bar 225. Next, the interrupt converter 230 determines whether the interrupt signal S _INT2 is to be transmitted to the processor 210 or to the instruction set simulator 110 within the handler level model virtual platform 10. When the interrupt signal S _INT2 is to be transferred to the instruction set simulator 110 in the handler level model virtual platform 10, the interrupt converter 230 converts the interrupt signal S _INT2 into the interrupt data packet P2 and transfers it to the handler level model. The interrupt agent 130 within the virtual platform 10. In FIG. 3, the operation of the driver 150, the bus bar 30, and the wafer level converter 250 will be omitted and will be described later for simplicity of explanation. Then, after receiving the interrupt data packet P2, the interrupt proxy 130 converts the interrupt data packet P2 back to the interrupt signal S _INT2 and transfers it to the vector interrupt controller 140. Next, the vectored interrupt controller 140 generates an interrupt INT2 based on the interrupt signal S _INT2 and prioritizes it to provide an interrupt INT2 to the instruction set simulator 110. Thus, after receiving the interrupt INT2, the instruction set simulator 110 can execute the interrupt routine corresponding to the interrupt INT2. On the other hand, when the interrupt signal S _INT2 is to be transmitted to the processor 210, the interrupt converter 230 transmits the interrupt signal S _INT2 to the vector interrupt controller 240 (as shown by the dashed line) so that the vector interrupt controller 240 can The interrupt signal S _INT2 generates an interrupt INT2 to the processor 210 and controls its priority. Thus, the processor 210 can execute the interrupt routine corresponding to the interrupt INT2.

It is worth noting that the interrupts in the handler level model virtual platform 10 and the scratchpad transport level physical platform 20 need to be set and configured before the interaction interruption is performed. Since the simulation system 100 composed of the handler level model virtual platform 10 and the scratchpad transport level physical platform 20 is used to simulate the operation of the same system single chip, the interrupt setting and configuration of the two platforms must consider the unity of the system.

4, 5, and 6 show an interrupt configuration packet 40, an interrupt type packet 50, and an inter-interruption packet 60, respectively, according to an embodiment of the invention. When there are multiple interrupt agent/interrupt converters, the field CHID is used to specify which interrupt agent/interrupt converter the packet corresponds to. The field LENGTH is used to indicate the length of the data of the packet. The field TYPE is used to indicate the type of the packet. For example, "00" indicates that the packet is the interrupt setting packet 40, "01" indicates that the packet is the interrupt type packet 50, and "10" indicates that the packet is the interactive interrupt packet 60.

Referring also to Figures 1 and 4, in the interrupt configuration packet 40, field 42 is used to indicate the source of the interrupt event in the scratchpad transport level entity platform 20, and field 44 is used to indicate the handler level model. The source of the interrupt event within virtual platform 10. For example, the simulation system 100 can simulate 32 interrupt events of a system single chip, wherein the source of each interrupt event can be the processor level virtual platform 10 or the scratchpad transport level entity platform 20 Provided by the unit. Moreover, as previously described, both field 42 and field 44 are 32 interrupt events representing the single wafer of the system. Therefore, the contents of field 42 and field 44 should be complementary values to avoid conflicts. For example, PP_VIC_SEL[0] in field 42 corresponds to the smart unit 220A in the scratchpad transport level entity platform 20. Therefore, PP_VIC_SEL[0] of field 42 should be set to "1" to indicate that the interrupt source for the bit is the smart asset unit 220A located in the scratchpad transport level entity platform 20. Simultaneously, VP_VIC_SEL[0] of field 44 should be set to "0" to indicate that the interrupt source for the bit is not located within the handler level model virtual platform 10.

Referring to Figure 5, in the interrupt type packet 50, fields 52, 54 and 56 represent the type of 32 interrupt events in the system single chip. For example, corresponding to fields 42 and 44 of the interrupt configuration packet 40, field 52 is used to indicate whether the interrupt event is a level trigger or an edge trigger. In addition, when the interrupt event is an edge trigger, the field 54 is used to indicate whether the interrupt event is a single edge trigger or a double edge trigger. Moreover, when the interrupt event is an edge trigger, the field 56 is used to indicate whether the interrupt event is a rising edge trigger or a falling edge trigger. In addition, when the interrupt event is a level trigger, field 56 is used to indicate whether the interrupt event is a high level trigger or a low level trigger. In addition, field 58 is used to indicate whether the interrupt event is enabled.

Referring to Figure 6, in the Interrupt Break Packet 60, field 62 indicates which interrupt events occurred in the 32 interrupt events of the system single chip. For example, when VIC_INTERRUPT[0] of field 62 is set to "1", it indicates that the interrupt event of the smart unit 220A has been triggered.

When the simulation is started, the simulation system 100 must first set the interrupt proxy 130 in the handler level model virtual platform 10 and the interrupt converter 230 in the scratchpad transport level physical platform through the interrupt configuration packet 40 and the interrupt type packet 50. And configuration, such that the interrupt agent 130 and the interrupt converter 230 can perform the corresponding conversion when receiving the interrupt data packet (eg, the inter-interrupt packet 60). Figure 7 is a diagram showing the transition between an interrupt signal and an interrupt data packet executed by the interrupt proxy 130/interrupt converter 230, in accordance with an embodiment of the present invention. In this embodiment, the interrupt agent 130/interrupt converter 230 is converted by a Finite State Machine (FSM). For example, as shown by the arrow A, when the interrupt data packet Pn, the interrupt data packet P(n+1), and the interrupt data packet P(n+2) are successively received, the interrupt agent 130/interrupt converter 230 is received. The finite state machine can convert the received interrupt data packet back to the interrupt signal (as indicated by the dashed line 70) according to the previously received interrupt configuration packet 40 and the interrupt type packet 50, wherein the interrupt data packet Pn corresponds to the interrupt signal S _INT1 and the interrupt. The data packet P(n+1) corresponds to the interrupt signal S _INT3 and the interrupt signal S _INT4 and the interrupt data packet P(n+2) corresponds to the interrupt signal S _INT2 . On the other hand, according to the clock signal CLK, the interrupt proxy 130/interrupt converter 230 can also convert the interrupt signal S _{INT1 -} S _INT4 into an interrupt data packet Pn, an interrupt data packet P(n+1), and an interrupt data packet P. (n+2), and sequentially transferred to the driver 150/wafer level converter 250 as indicated by arrow B.

Referring back to FIG. 1, in the simulation system 100, the data transfer between the handler level model virtual platform 10 and the scratchpad level physical platform 20 is in accordance with the format of the communication protocol of the bus 30. Therefore, the driver 150 and the wafer level converter 250 respectively convert the interrupt data packets from the interrupt proxy 130 and the interrupt converter 230 into a format conforming to the communication protocol of the bus bar 30, and transmit the same to the other platform through the bus bar 30. In addition, the wafer level converter 250 has a temporary storage unit that can store an interrupt data packet received from the processing level model virtual platform 10 or an interrupt data packet to be transmitted to the processing level model virtual platform 10. Specifically, the driver 150 can access the interrupt level data packet to the wafer level converter 250 through the bus bar 30.

By using interactive interrupts, different platforms within the simulation system 100 can be integrated into the same system for complex interrupt intensive software development, such as Real Time Operating System (RTOS). Therefore, the speed and accuracy of the overall simulation can be improved, thereby accelerating the development of the system single chip.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10. . . Handler level model virtual platform

100. . . Analog system

110. . . Instruction set simulator

120A-120C, 220A-220C. . .矽智财单位

130. . . Interrupt agent

140. . . Vector interrupt controller

150. . . driver

20. . . Scratchpad transport level entity platform

210. . . processor

230. . . Interrupt converter

240. . . Vector interrupt controller

250. . . Wafer level converter

30. . . Peripheral component interconnect bus

40. . . Interrupt configuration packet

42, 44, 52, 54, 56, 58, 62. . . Field

50. . . Interrupt type packet

60. . . Interrupt interrupt packet

CLK. . . Clock signal

INT1, INT2. . . Interrupt

P1, P2, Pn, P(n+1), P(n+2). . . Interrupt data packet

as well as

S _INT1 , S _INT2 , S _INT3 , S _INT4 . . . Interrupt signal

1 is a schematic diagram showing a system for simulating a system single chip according to an embodiment of the invention;

2 is a schematic diagram showing an interaction interrupt trigger path according to an embodiment of the present invention in FIG. 1;

3 is a schematic diagram showing an interaction interrupt trigger path according to another embodiment of the present invention in FIG. 1;

Figure 4 is a diagram showing an interrupt configuration packet according to an embodiment of the invention;

Figure 5 is a diagram showing an interrupt type packet according to an embodiment of the present invention;

Figure 6 is a diagram showing an inter-interruption packet according to an embodiment of the invention;

Figure 7 is a diagram showing a transition between an interrupt signal and an interrupt data packet executed by an interrupt agent/interrupt converter, in accordance with an embodiment of the present invention.

10. . . Handler level model virtual platform

100. . . Analog system

110. . . Instruction set simulator

120A-120C, 220A-220C. . .矽智财单位

130. . . Interrupt agent

140. . . Vector interrupt controller

150. . . driver

20. . . Scratchpad transport level entity platform

210. . . processor

230. . . Interrupt converter

240. . . Vector interrupt controller

250. . . Wafer level converter

as well as

30. . . Peripheral component interconnect bus

Claims (14)

A system single chip simulation system comprising: a processing program level model virtual platform, comprising: a virtual processor; a virtual design unit; and an interrupt agent for converting a virtual interrupt signal from the virtual design unit Forming a first interrupt data packet; and a scratchpad transport level entity platform coupled to the processing program level model virtual platform, comprising: a physical design unit; and an interrupt converter for packaging according to the first interrupt data packet, Generating a first interrupt corresponding to one of the virtual interrupt signals; and a physical processor configured to execute a first interrupt program corresponding to the first interrupt, wherein the scratchpad transport level physical platform is set to have a field The hardware development board of the program gate array and the processing program level model virtual platform are implemented by a specific operation system, wherein the virtual design unit and the physical design unit are respectively a software body to be integrated into the same system single chip. The smart money unit and a hardware unit. The analog system of claim 1, wherein the register transfer level physical platform further comprises: a vector interrupt controller coupled between the interrupt converter and the physical processor to control the above The priority of the first interrupt. The analog system of claim 1, wherein the interrupt converter of the above-mentioned register transfer level physical platform is further from the above Converting a physical interrupt signal of the physical design unit into a second interrupt data packet, and transmitting the second interrupt data packet to the processing program level model virtual platform, so that the interrupt agent of the processing program level model virtual platform is according to the foregoing The second interrupt data packet generates a second interrupt corresponding to one of the physical interrupt signals, and the virtual processor executes a second interrupt program corresponding to the second interrupt. The simulation system of claim 3, wherein the processing program level model virtual platform further comprises: a vector interrupt controller coupled between the interrupt agent and the virtual processor to control the foregoing The priority of the second interrupt. The analog system of claim 3, wherein the register transfer level physical platform further comprises: a wafer level converter for storing the first interrupt data packet and the second interrupt data packet, wherein The interrupt converter generates the first interrupt based on the first interrupt data packet stored in the wafer level converter. The simulation system of claim 5, wherein the processing program level model virtual platform further comprises: a driver for storing the first interrupt data packet from the interrupt agent to the foregoing according to a specific communication protocol And a chip level converter, and transmitting the second interrupt data packet stored in the chip level converter to the interrupt agent according to the specific communication protocol. The simulation system of claim 1, wherein the processing program level model virtual platform is a timing cycle approximation platform, and the scratchpad transmission level physical platform is a timing cycle precision platform. A system single chip simulation system includes: a scratchpad transmission level physical platform, comprising: a physical design unit; and an interrupt converter for converting a physical interrupt signal from the physical design unit into an interrupt data packet And a processing program level model virtual platform coupled to the temporary storage layer entity platform, comprising: a virtual design unit; and an interrupting agent, configured to generate, according to the interrupt data packet, a corresponding physical interrupt signal An interrupt; and a virtual processor for controlling the virtual design unit, and executing an interrupt program corresponding to the interrupt, wherein the scratchpad transport level physical platform is set in a hardware development with a field programmable gate array The board and the processing program level model virtual platform are implemented by a specific operating system, wherein the virtual design unit and the physical design unit are respectively a software entity and a hardware unit to be integrated into the same system single chip.矽智财单位. The simulation system of claim 8, wherein the processing program level model virtual platform further comprises: a vector interrupt controller coupled between the interrupt agent and the virtual processor to control the interrupt Priority. For example, in the simulation system described in claim 8, wherein the processing program level model virtual platform is a timing cycle approximation platform, and the scratchpad transmission level physical platform is a timing cycle precision platform. A simulation method suitable for combining a processing program hierarchy model The simulation platform and the one of the system single chip of the scratchpad transmission level physical platform, the simulation method comprises: converting a virtual interrupt signal from a virtual design unit into a first in the processing program level model virtual platform Interrupting the data packet; transmitting, according to a specific communication protocol, the first interrupt data packet from the processing program level model virtual platform to the temporary storage layer entity platform; and in the temporary storage layer entity platform, according to the foregoing An interrupt data packet generates a first interrupt corresponding to one of the virtual interrupt signals; and in the scratchpad transport level physical platform, a first interrupt program is executed corresponding to the first interrupt, wherein the scratchpad transport level The physical platform is disposed on a hardware development board having a field programmable gate array, and the processing program level model virtual platform is implemented by a specific operating system, wherein the virtual design unit and the physical design unit are respectively configured to be integrated One of the same system single chip software And a silicon intellectual property hardware unit. The simulation method of claim 11, further comprising: converting a physical interrupt signal from a physical design unit into a second interrupt data packet in the scratchpad transport level entity platform, and storing the data in a a chip level converter; transmitting the second interrupt data packet stored in the chip level converter to the processing program level model virtual platform according to the specific communication protocol; in the processing program level model virtual platform, according to the second Interrupting the data packet to generate a second interrupt corresponding to one of the physical interrupt signals; and executing a second interrupt program corresponding to the second interrupt in the processing program level model virtual platform. The method of claim 12, wherein the step of transmitting the first interrupt data packet from the processing program level model virtual platform to the temporary storage layer entity platform further comprises: The data packet is stored in the chip level converter of the scratchpad transport level physical platform, wherein the first interrupt is generated according to the first interrupt data packet stored in the chip level converter. An analog method, which is suitable for combining a processing program level model virtual platform and a system single chip simulation system of a scratchpad transmission level physical platform, wherein the simulation method comprises: in the above-mentioned scratchpad transmission level entity platform, Converting a physical interrupt signal of an entity design unit into an interrupt data packet; transmitting the interrupt data packet to the processing program level model virtual platform according to a specific communication protocol; and in the processing program level model virtual platform, according to the interrupt data Encapsulating to generate an interrupt corresponding to one of the physical interrupt signals; and executing, in the processing program level model virtual platform, an interrupt program corresponding to the interrupt, wherein the scratchpad transport level entity platform is set to have a field programmable The hardware development board of the gate array, and the processing program level model virtual platform are implemented by a specific operating system, wherein the processing program The virtual design unit of the hierarchical model virtual platform and the above-mentioned physical design unit of the above-mentioned scratchpad transport level physical platform are respectively a software entity and a hardware unit to be integrated into the same system single chip.