TWI462480B - High performance of fully-digitally controlled pwm converters - Google Patents

Description

High-performance digital position control conversion circuit and method thereof

The present invention relates to a conversion circuit, and more particularly to a high performance digital position conversion conversion circuit.

Today, digitally controlled conversion circuits are popular because of their many unique advantages, such as advanced control algorithms, strong communication capabilities, and high immunity to interference. The digital control conversion circuit includes quantization means such as an analog to digital converter (ADC) and a digital pulse width modulator (DPWM). As shown in Fig. 1, conventionally, if the resolution of the _DPWM N _{DPWM is} lower than the resolution of the _ADC N _ADC , that is, the voltage ΔV _DPWM generated by a Least Significant Bit (LSB) of the _{DPWM is} larger than that of the ADC. The voltage generated by an LSB is ΔV _ADC , and the difference between the output voltage V _o and the rated output voltage V _REF caused by one LSB of the DPWM will be greater than the minimum change value ΔV _ADC that the ADC can detect, which will make the system unable to lock. When the output voltage V _{o is stored} , the output voltage V _o will bounce around the rated output voltage V _REF and is always changed. This phenomenon is called "limit ring oscillation". It causes the output voltage V _o to oscillate greatly, making it difficult to analyze and compensate for the noise interference of the output voltage V _o and the electromagnetic interference (EMI) caused by the converter. That is to say, in the conventional digital control conversion circuit, the resolution of the _DPWM N _DPWM must be higher than the resolution of the _ADC N _ADC , otherwise the limit cycle oscillation will occur.

The traditional DPWM architecture is based on a counter. The resolution of this type of DPWM is related to the clock frequency of the system. Taking the counter-based DPWM in the buck converter as an example, the output voltage ΔV _o generated by one LSB of the DPWM is: ΔV _o =V _in . △ D = V _in . f _SW /f _clock (1) where V _in is the system input voltage, ΔD is the duty cycle resolution, f _SW is the switching frequency, and f _clock is the system clock frequency.

In practical applications, the switching frequency f _SW high-frequency trend is more and more obvious, generally greater than 500KHz, and the system clock frequency f _{clock is} greater than 200MHz, the cost will be greatly increased, so the system clock frequency f _clock used in the system is generally less than 200MHz, Therefore, the output voltage ΔV _o generated by one LSB of the DPWM is large, that is, the resolution of the _DPWM N _{DPWM is} low. For example, the switching frequency f _{SW is} taken as 500 kHz, the system clock frequency f _{clock is} taken as 200 MHz, and the system input voltage V _in is 12 V, the output voltage ΔV _o generated by one LSB of the DPWM is 30 mV. For a common digitally controlled conversion circuit, such an output voltage is large, and the corresponding DPWM resolution N _{DPWM is} low.

In order to improve the resolution of DPWM, many methods have been proposed in the prior art, such as a delay line structure, a hybrid method, a constant on-time method, a dither method, and the like. However, these methods are not only complicated, but also require replacement of hardware devices, which is not suitable for general application. In addition, these methods sometimes make the system transient response performance worse. Therefore, it is difficult to obtain a DPWM having a higher resolution in the prior art, and even if it can be obtained, the cost is very high. expensive.

In the prior art, in order to avoid limit cycle oscillation, the resolution of the ADC is lower than the resolution of the DPWM, and the resolution of the DPWM is lower, so the resolution of the ADC is correspondingly lower. The lower ADC resolution makes the system transient back strain poor and the accuracy of the output voltage becomes lower.

An object of the present invention is to solve the problem of reducing system performance in order to avoid limit ring oscillation in a conventional digitally controlled conversion circuit.

In order to solve the above problems, the present invention proposes a novel digital control conversion circuit. The novel digital control conversion circuit includes a conversion circuit that provides an output voltage, an analog to digital conversion circuit that receives the output voltage and a reference voltage, and the analog to digital conversion circuit is configured according to the output a voltage and the reference voltage generate a digital error signal; a digital control circuit, the digital control circuit determines a system state and generates a duty cycle signal according to a system state; a digital pulse width modulation circuit, the digital pulse width modulation circuit receiving station The duty cycle signal is generated and an analog duty cycle signal is generated based on the duty cycle signal to control the conversion circuit.

In order to solve the above problems, the present invention also proposes a method of controlling a conversion circuit by a digital control circuit. The method includes receiving an output voltage and a reference voltage and generating a digital error signal; determining a system state and generating a system status signal; employing a system control mode according to the system status signal and the digital error signal; and adjusting the output by using the system control mode Voltage.

The present invention adopts the circuit of the above structure and/or the method of the above steps, which adopts an analog to digital converter (analog to digital converter, The resolution of the ADC can be higher than that of the digital pulse width modulator (DPWM), the circuit is easy to implement, the system transient response performance and the output voltage accuracy are improved, and the output voltage is not generated. The limit cycle oscillates.

LSB‧‧ unit resolution

△V _DPWM /△V _ADC ‧‧‧ voltage

PID‧‧‧ two-order proportional integral differential

T _dt ‧‧‧ time

I _o ‧‧‧Output current

10‧‧‧Digital Control Conversion Circuit

101‧‧‧Transition circuit

103‧‧‧Digital Control Circuit

DPWM‧‧‧Digital Pulse Width Modulator

ADC‧‧·Analog Converter

V‧‧‧ voltage

V _o ‧‧‧output voltage

d(k)‧‧‧Digital duty cycle signal

e(k)‧‧‧ systematic error signal

s(k)‧‧‧ system status signal

e _A/D (k)‧‧‧ digital error signal

V _REF ‧‧‧rated output voltage

V _acc ‧‧‧Quantified reference signal

Fig. 1 is a diagram showing the waveform generated by the limit cycle oscillation in the conventional digital control conversion circuit.

FIG. 2 shows a novel digital control conversion circuit 10 in accordance with an embodiment of the present invention.

Fig. 3 shows a structure 20 of the duty ratio generator in the digital control conversion circuit 10 shown in Fig. 2.

Figure 4 shows a schematic diagram of the system unit step response in a digitally controlled conversion circuit.

Fig. 5 is a view showing the waveform of the output voltage and the state of the system state when the digital control conversion circuit 10 shown in Fig. 2 is operated.

Figure 6 is a flow chart showing the control of a conversion circuit by a digital control method in accordance with one embodiment of the present invention.

Fig. 7(a) is a diagram showing an experimental waveform of an output voltage using a conventional digitally controlled conversion circuit and its method.

Figure 7(b) is a diagram showing experimental waveforms of the output voltage of the digitally controlled conversion circuit in accordance with one embodiment of the present invention.

Figure 8 shows the system state transition and system control mode transition process.

Figure 9(a) shows a schematic diagram of the transient response of the output voltage using a conventional digitally controlled conversion circuit and its method.

Figure 9(b) illustrates digital control in accordance with one embodiment of the present invention A schematic diagram of the transient response of the output voltage of the conversion circuit.

Figure 10(a) is a diagram showing the waveform of an output voltage using a nonlinear controller in a conventional digitally controlled conversion circuit.

Fig. 10(b) is a diagram showing an output voltage waveform in which a nonlinear controller is employed in a digitally controlled conversion circuit according to an embodiment of the present invention.

The invention proposes a novel digital control conversion circuit and a method thereof. Compared with the conventional digital control conversion circuit, the analog to digital converter (ADC) adopted by the novel digital control conversion circuit proposed by the present invention can be compared with a digital pulse width modulator (DPWM). The resolution is high, the circuit is easy to implement, and the system transient response performance and output voltage accuracy are improved. At the same time, the output voltage does not cause limit cycle oscillation.

Figure 2 shows a digitally controlled conversion circuit 10 in accordance with one embodiment of the present invention. As shown in FIG. 2, the digital control conversion circuit 10 includes a conversion circuit 101 and a digital control circuit 103. The difference between the output voltage V _{o of the} conversion circuit 101 and the rated output voltage V _REF is sampled and converted by the ADC module to obtain a digital error signal e _A/D (k). The system state determiner receives the digital error signal e _A/D (k) and a quantized reference signal V _acc and determines the system state based on e _A/D (k) and V _acc to generate a system state signal s(k). In the present embodiment, s(k) = 0 when the system is in steady state and s(k) = 1 when the system is in motion. Those skilled in the art will appreciate that the system status signal s(k) may also take other values to indicate that the system is in steady state and dynamics, respectively. The system error generator receives the digital error signal e _A/D (k) and the system state signal s(k) and generates a systematic error signal e(k) according to e _A/D (k) and s(k), the system error signal e(k) controls the duty cycle generator to obtain a digital duty cycle signal d(k). Digital duty cycle signal d (k) obtained after conversion module DPWM duty cycle signal to control the analog conversion circuit 101, thereby adjusting the output voltage V _o.

When the circuit is in operation, the system state determiner first determines the system state and then changes the system control mode accordingly. When the system state determiner determines that the system is in a steady state, the system error signal e(k) generated by the system error generator is 0, that is, e(k)=0. At this point, the duty cycle generator will generate a duty cycle signal. Then, the system control mode is switched to the steady state control mode. At this time, the duty cycle signal is converted by the DPWM module to obtain a analog-like duty ratio signal to control the conversion circuit 101, so that the output voltage V _{o is} maintained near the rated output voltage V _REF , and the output voltage V _o and the rated output voltage V are The difference between the _REF and the quantized value quantized by the ADC module does not exceed the quantized reference signal V _acc , wherein the quantized reference signal V _acc should be a natural number less than the nominal error range of the system output voltage. In steady state, the system adopts the steady-state control mode. Regardless of the value of the digital error signal e _A/D (k), the difference between the system output voltage V _o and the rated output voltage V _REF is kept within V _acc , Limit cycle oscillations are generated.

When the system state determiner determines that the system is dynamic, the system error signal output by the system error generator is equal to the digital error signal e _A/D (k), ie e(k)=e _A/D (k), system control mode conversion For dynamic control mode. At this time, the duty ratio generator generates a duty ratio signal d(k). When the system is dynamic, once the output voltage V _o changes, the system will adjust the duty cycle signal d (k) for adjustment of the output voltage V _o. In the dynamic state, the system uses the dynamic control mode to adjust the output voltage in time, and does not generate limit cycle oscillation.

It can be seen that the system adjusts the output voltage V _o by judging the state of the system to correspondingly adopt steady state control or dynamic control, thereby avoiding the occurrence of limit cycle oscillation.

It should be noted that when the system is determined to be dynamic, the circuit control mode immediately transitions to the dynamic control mode, and when the system is determined to be in steady state, the duty cycle generator first generates a duty cycle signal at the duty cycle. After the signal is generated, the circuit control mode is converted to the steady state control mode.

Fig. 3 shows a structure 20 of the duty ratio generator in the digital control conversion circuit 10 shown in Fig. 2. As shown in the third embodiment, the duty cycle generator includes a DUTY module and a two-stage Proportion Integration Differentiation (PID) module. The system error generator first generates a system error signal e(k). When e(k)=0, that is, when the system is determined to be in a steady state, the DUTY module generates a certain value duty signal D to be supplied to the DPWM module; When e(k)=e _A/D (k), that is, when the system is judged to be dynamic, the PID module gives an instantaneous duty cycle signal d(k)=d(k-1)+ae(k) ) +be(k-1)+ce(k-2) is provided to the DPWM module. Where d(k-1) is the instantaneous duty cycle signal at time k-1, and e(k), e(k-1), and e(k-2) are k, k-1, and k-2 moments, respectively. The systematic error signals, a, b and c are the control parameters of the two-order PID. It should be noted that the system state will be latched once it is determined until the system is determined to enter another state.

The DUTY module generates a fixed duty cycle signal D by the following method. The DUTY module receives the instantaneous error signals e _A/D (k-2), e _A/D (k-1), e _A/D (k), and k-1 instants at k-2, ..., k. The duty cycle signal d(k-1), when the digital error signal generated by the ADC module satisfies the condition: e _A/D (k)=e _A/D (k-1)=e _A/D (k-2 When 0 (1), the obtained instantaneous duty cycle signal d(k-1) is the appropriate fixed duty duty signal D, that is, D = d(k-1).

Those skilled in the art will appreciate that in the embodiment illustrated in FIG. 3, the immediate duty cycle signal is generated by a two-stage proportional integral derivative circuit, while in other embodiments, the immediate duty cycle signal can also be derived from the order. The proportional integral derivative circuit generates, correspondingly, the instantaneous duty cycle signal is determined by the system error signal at time km, ..., k, and the instantaneous duty cycle signal at time K-1 and the control parameter of the m-th order proportional integral derivative circuit, and The condition for generating the duty cycle signal is e _A/D (k)=e _A/D (k-1)=...=e _A/D (km)=0.

It should also be understood by those skilled in the art that in the embodiment shown in FIG. 3, the immediate duty cycle signal is generated by the PID, while in other embodiments, the immediate duty cycle signal can also be used by other similar functions. The compensation network is generated, such as the n-zero n-pole network compensated in the Z domain.

In another embodiment, the duty cycle generator in digital control conversion circuit 10 shown in FIG. 2 includes a compensation network and does not include a DUTY module. The duty cycle signal is generated by the compensation network regardless of whether the system is determined to be steady state or dynamic. Taking the two-stage PID as the compensation network as an example, when the system is judged to be dynamic or steady state, the PID module gives an instantaneous duty cycle signal d(k)=d(k-1)+ae(k ) +be(k-1)+ce(k-2) is provided to the DPWM module.

In one embodiment, the system state determiner determines the system state as follows.

If the system is in a dynamic Initially, when the output voltage V _o T _dt holding a period of time within a certain range around the nominal output voltage V _REF, the system will be determined as steady state. Wherein, a certain range around the rated output voltage V _REF should be such that the difference between the system output voltage V _o and the rated output voltage V _REF is maintained by the digital error signal e _A/D (k) obtained after sampling by the ADC module - Between p and p, namely: -p≦e _A/D (k) ≦p (2) where p is a non-negative integer smaller than the quantized reference signal, and the value of p may depend on the accuracy of the system, such as p Is 1.

The period of time T _dt may be greater than the output voltage V _o for the period of the damped oscillation. For this system, the unit step input is the worst working condition. Therefore, as long as the period of time T _{dt is} greater than the period of the unit step response, the time T _dt will be greater than the period during which the output voltage V _o is damped under other input conditions. Figure 4 shows a schematic diagram of the system unit step response. As shown in Fig. 4, the period T _{dt is} much larger than the maximum values of T _d1 and T _d2 , namely: T _dt >>T _d1 (3)

T _dt >>T _d2 (4) As described above, the conditions under which the system enters a steady state are equations (2), (3), and (4).

If the system is initially in a steady state, the output voltage V _o appears disturbances once the system is determined to enter the dynamic. A disturbance judging method is when the difference quantized value of the output voltage V _o and the rated output voltage V _REF exceeds the range of V _acc , that is: | e _{A / D} (k) | ≧ V _acc (5) on the output voltage V _o There was a disturbance.

In another embodiment, if the difference between the output voltage V _o and the rated output voltage V _REF is sampled by the ADC module, the digital error signal e _A/D (k) is compared with the digital error signal e _A at the previous moment. _{The change of /D} (k-1) is greater than q, that is: |Δe _A/D (k)|>q (6), the disturbance occurs on the output voltage V _o , where q is a natural number.

Those skilled in the art will appreciate that the above determination of system status is merely exemplary. The determination of the system status can also be achieved by other conditions.

Fig. 5 is a view showing the waveform of the output voltage and the state of the system state when the digital control conversion circuit 10 shown in Fig. 2 is operated. As shown in FIG. 5, during the T1 period, the system is in a steady state, the system control mode is a steady state control mode, and the output voltage _{Vo is} within the quantized reference signal V _acc set near the rated output voltage V _REF . When entering the T2 period, the change value of the output voltage V _o exceeds the range of V _acc , that is, the output voltage V _o satisfies the condition of occurrence of disturbance | e _{A / D} (k) | ≧ V _acc , the system is determined to enter the dynamic, this When the system control mode is immediately converted to the dynamic control mode. After entering the T2 period, the output voltage V _{o changes} around the rated output voltage V _REF , and the difference between the output voltage V _o and the rated output voltage V _REF is sampled by the ADC module and the digital error signal e _A/D (k) The system is judged to enter a steady state for a period of time between -1 and 1, i.e., -1 ≦e _A/D (k) ≦1. During the T3 period, the system is again in steady state, and the output voltage V _{o is} within the quantized reference signal set near the rated output voltage V _REF . At this time, the duty ratio generator generates a duty cycle signal, and then the system control mode is converted to stable. State control mode.

Figure 6 shows the use of digital control in accordance with one embodiment of the present invention. The method controls the flow chart of the conversion circuit. As shown in Figure 6, when the system circuit starts to work, the duty cycle of the DPWM is given by the compensation network, and the system operates in the dynamic control mode. In an embodiment, the compensation network can be a PID. Next, the system error generator determines whether the system is in a steady state. If the system does not satisfy the steady state condition represented by the above formulas (2), (3), and (4) (where the q value is taken as 1), the system will still Working in the dynamic control mode; if the system satisfies the steady-state conditions (2), (3), (4), the DUTY module starts to find the fixed-value duty signal D, and if the DUTY module determines that the system does not satisfy the above formula ( 1) The specified duty cycle is generated, the DUTY module continues to find the fixed duty signal D. If the DUTY module determines that the system meets the set duty ratio (1), the DUTY module gives The duty cycle D is set. Thereafter, the system enters a steady state control mode. Thereafter, the system error generator determines whether the system enters the dynamics. If the system does not satisfy the dynamic conditions represented by the above formulas (5) and (6) (where the q value is taken as 1), the system still operates in the steady state control mode; When the system meets the dynamic condition (5) or (6), the system immediately enters the dynamic working mode. At this time, the duty cycle is given by the compensation network, and the system starts a new round of judgment.

It should be noted that the steady-state conditions (2), (3), (4), the dynamic conditions (5) and (6), and the constant duty duty generation condition (1) in the above embodiment are merely exemplary. According to the requirements of the system, it can also be judged by other conditions.

It should be noted that the digital control conversion circuit and method thereof proposed by the present invention can be applied to various conversion circuits such as a buck conversion circuit, a boost conversion circuit, and the like.

Figures 7-10 illustrate experimental results in accordance with an embodiment of the present invention. The experiment used a buck converter as a conversion circuit to program on the Xilinx Spantan3A FPGA. The system input voltage, output voltage and output current are: V _in =12V, V _o =3.3V, I _o =3A; the switching frequency, sampling frequency and system clock frequency are: f _sw =586kHz, f _s =586kHz, f _clock =150MHz; PID is used as the compensation network, its bandwidth is 50KHz, the proportional parameter KP=0.433, the integral parameter KI=2.033e4, the differential parameter KD=1.195e-5; the voltage generated by one LSB of DPWM and ADC respectively It is: ΔV _o =15mV, ΔV _ADC =5mV; the voltage range set by the output voltage V _o is: ΔV _acc =25mV.

Fig. 7(a) is a diagram showing an experimental waveform of an output voltage using a conventional digitally controlled conversion circuit and its method. Figure 7(b) is a diagram showing experimental waveforms of the output voltage of the digitally controlled conversion circuit in accordance with one embodiment of the present invention. It can be seen from the comparison of the 7(a) and 7(b) diagrams that the limit cycle oscillation generated in the conventional digital control conversion circuit is not generated in the novel digital control conversion circuit proposed by the present invention.

Figure 8 shows the system state transition and system control mode transition process. As shown in Figure 8, channel 1 is the output voltage waveform. Channel 2 is a control mode waveform, in which the high level is the steady state control mode and the low level is the dynamic control mode. Channel 3 is the system state waveform, where the high level is steady state and the low level is dynamic. As shown in Fig. 8, when the output voltage _Vo is disturbed, the system is judged to be dynamic, and the system control mode is immediately converted to the dynamic control mode. When the output voltage V _o is maintained for a period of time within a range set near the rated output voltage V _REF , the system is determined to be in a steady state. As can be seen from FIG. 8 , after the system is in a steady state for a period of time, the system control mode is converted to Steady state control mode.

Figure 9(a) shows the traditional digital control conversion circuit and its square A schematic diagram of the transient response of the output voltage of the method. Figure 9(b) is a diagram showing the transient response of the output voltage of the digitally controlled conversion circuit in accordance with one embodiment of the present invention. It can be seen from the comparison of the figures 9(a) and 10(b) that although the resolution of the DPWM used in the conventional digital control conversion circuit and the novel digital control conversion circuit proposed by the present invention is the same, the novel digital control proposed in the present invention The resolution of the ADC used in the conversion circuit is improved, and the transient response performance of the system output voltage is improved.

Figure 10(a) is a diagram showing the waveform of an output voltage using a nonlinear controller in a conventional digitally controlled conversion circuit. Fig. 10(b) is a diagram showing an output voltage waveform in which a nonlinear controller is employed in a digitally controlled conversion circuit according to an embodiment of the present invention. It can be seen from the comparison of Figures 10(a) and 10(b) that when the compensation network uses a nonlinear controller, the novel digital control conversion circuit and method thereof proposed by the present invention have higher resolution due to the adopted ADC. The nonlinear controller can detect smaller output voltage errors and the response of the nonlinear controller is more sensitive.

10‧‧‧Digital Control Conversion Circuit

101‧‧‧Transition circuit

103‧‧‧Digital Control Circuit

DPWM‧‧‧Digital Pulse Width Modulator

ADC‧‧·Analog Converter

V‧‧‧ voltage

V _o ‧‧‧output voltage

d(k)‧‧‧Digital duty cycle signal

e(k)‧‧‧ systematic error signal

s(k)‧‧‧ system status signal

e _A/D (k)‧‧‧ digital error signal

V _REF ‧‧‧rated output voltage

V _acc ‧‧‧Quantified reference signal

Claims (20)

A digital control conversion circuit, characterized in that the digital control conversion circuit comprises: a conversion circuit, the conversion circuit provides an output voltage; an analog to digital conversion circuit, the analog to digital conversion circuit receives the output voltage and a reference voltage and the The analog-to-digital conversion circuit generates a digital error signal according to the output voltage and the reference voltage; a digital control circuit that determines the system state and generates a duty cycle signal as a digital control signal according to the system state; a pulse width modulation circuit, the digital pulse width modulation circuit receives the duty cycle signal and generates an analog duty ratio signal according to the duty cycle signal to control the conversion circuit, wherein the digital control circuit comprises: a system state determination circuit, The system state judging circuit judges the state of the digital control conversion circuit and generates a system state signal; a system error generating circuit that receives the digital error signal and the system state signal and according to the digital error signal and the system The status signal produces a systematic error signal, wherein The system error signal is equal to zero when the system state signal is in steady state, and the system error signal is equal to the digital error signal when the system state signal is in motion; a duty cycle generating circuit that receives the system error signal and according to the system error The signal produces a duty cycle signal that is a digital control signal. The digital control conversion circuit of claim 1, wherein the system state determination circuit receives the digital error signal and a quantization parameter The test signal generates a steady state signal or a dynamic signal according to the digital error signal and the quantized reference signal, wherein the quantized reference signal is a natural number. The digital control conversion circuit of claim 2, wherein if the absolute value of the digital error signal is less than or equal to the first set value within a set time, the system state determining circuit generates a steady state signal, wherein The first set value is a non-negative integer less than the quantized reference signal. The digital control conversion circuit according to claim 2, wherein if the absolute value of the difference between the value of the digital error signal at time n and the value at time n+1 is greater than a second set value, The system state determination circuit generates a dynamic signal, wherein n and the second set value are both natural numbers. The digital control conversion circuit according to claim 2, wherein the system error generating circuit generates a dynamic signal if an absolute value of the digital error signal is greater than or equal to the quantized reference signal. The digital control conversion circuit according to claim 2, wherein the system error signal is 0 when the system state signal is a steady state signal, and the system error signal is the digital signal when the system state signal is a dynamic signal. Error signal. The digital control conversion circuit according to claim 6, wherein when the system error signal is 0, the duty cycle generating circuit generates a certain value duty cycle signal; when the system error signal is the digital error signal, The duty cycle generating circuit generates an immediate duty cycle signal. The digital control conversion circuit of claim 7, wherein the duty cycle generating circuit includes a compensation network for generating the The duty cycle signal and the fixed duty cycle generation circuit are operative to generate the fixed duty cycle signal, where m is a natural number. The digital control conversion circuit of claim 8, wherein the compensation network is a proportional integral derivative circuit. The digital control conversion circuit according to claim 8, wherein the fixed value duty generation circuit receives the digital error signal at time k, ..., k and the instantaneous duty signal at time k-1, if When the digital error signal is 0 at the time of km, ..., k, the fixed duty ratio generating circuit generates the fixed duty ratio signal at the time and the fixed duty signal at the time k is the instant of k-1 A duty cycle signal, where k is an integer greater than m. The digital control conversion circuit of claim 6, wherein the duty cycle generation circuit includes an m-th order compensation network for generating the duty cycle signal, wherein m is a natural number. The digital control conversion circuit according to claim 11, wherein the duty ratio generating circuit receives a system error signal at time k, ..., k and a duty signal at time k-1 and according to km, ..., The system error signal at time k and the duty signal at k-1 produce a duty cycle signal at time k, where k is an integer greater than m. A method for controlling a conversion circuit by a digital control circuit, the method comprising: receiving an output voltage and a reference voltage and generating a digital error signal; determining a system state and generating a system status signal; and determining the system status signal and the digital The error signal adopts a system control mode; the system control mode is used to adjust the output voltage; Applying the system control mode according to the system status signal and the digital error signal comprises: generating a system error signal according to the system status signal and the digital error signal, when the system status signal is in a steady state, the system error signal is equal to zero, and when the system The system error signal is equal to the digital error signal when the status signal is active; and the system control mode is employed based on the system error signal. The method of claim 13, wherein the determination of the system state and the generation of the system status signal are achieved by monitoring the digital error signal. The method of claim 14, wherein if the digital error signal is less than or equal to a first set value within a set time, the system is in a steady state and the system status signal is a steady state signal; The absolute value of the difference between the value of the digital error signal at time n and the value at time n+1 is greater than a second set value or the digital error signal is greater than or equal to a set quantized reference signal, then the system is dynamic and the system state The signal is a dynamic signal, wherein n, the quantized reference signal and the second set value are both natural numbers and the first set value is a non-negative integer smaller than the quantized reference signal. The method of claim 15, wherein if the system status signal is a steady state signal, a steady state control mode is employed, and if the system status signal is a dynamic signal, a dynamic control mode is employed. The method of claim 16, wherein if the steady state control mode is adopted, the system generates one of a certain value duty cycle signal or an immediate duty cycle signal to adjust the output voltage. control Mode, the system generates the instantaneous duty cycle signal to adjust the output voltage. The method of claim 17, wherein the immediate duty cycle signal is generated by an m-order compensation network, wherein m is a natural number. The method of claim 18, wherein the m-th order compensation network is a proportional-integral-derivative circuit. The method of claim 17, wherein the immediate duty cycle signal is generated by the m-th order compensation network, and the m-th order compensation network receives a system error signal at time k, ..., k and k-1 Instantaneous duty cycle signal at time and generating the instantaneous duty cycle signal at time k according to the system error signal at time k, ..., k and the instantaneous duty cycle signal at k-1; a certain value duty cycle generating circuit generates the system error signal at time k, ..., k and the duty signal at time k-1, and if the system error signal is at km, ..., the time k is 0, the fixed duty ratio generating circuit generates the fixed duty signal at time k and the fixed duty signal at the k time is the instantaneous duty ratio at time k-1 Signal, where m is a natural number and k is an integer greater than m.