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TWI462355B - 積體電路３ｄ相變記憶體陣列及製造方法 - Google Patents

積體電路３ｄ相變記憶體陣列及製造方法 Download PDF

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TWI462355B
TWI462355B TW098128907A TW98128907A TWI462355B TW I462355 B TWI462355 B TW I462355B TW 098128907 A TW098128907 A TW 098128907A TW 98128907 A TW98128907 A TW 98128907A TW I462355 B TWI462355 B TW I462355B
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Hsiang Lan Lung
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Description

積體電路3D相變記憶體陣列及製造方法
本發明是有關於高密度相變記憶體元件，且特別是有關於其中多個記憶體單元平面經配置以提供三維(three-dimensional，3D)陣列的記憶體元件。
可藉由以適於在積體電路中實施之位準施加電流來致使基於相變之記憶體材料(如基於硫族化物(chalcogenide-based)之材料及類似材料)在非晶狀態與結晶狀態之間變相。與大致為結晶狀態相比，大致為非晶狀態之特徵在於較高的電阻率，其可容易被感測以指示資料。此等特性已在使用可程式化電阻材料來形成非揮發性記憶體電路中引起關注，所述非揮發性記憶體電路可用隨機存取進行讀取及寫入。
隨著積體電路中之元件的關鍵尺寸縮減至一般記憶體單元技術之限值，設計者一直在尋找用於堆疊多個記憶體單元平面以達成較大儲存容量且達成每位元之較低成本的技術。在2008年5月1日公開之Haring-Bolivar等人的美國專利申請公開案第US 2008/0101109號中已提出多層相變元件(參見圖11a)。Haring-Bolivar等人之結構由以一者位於另一者上方之堆疊配置的若干2D相變記憶體單元陣列組成，其中以一者在另一者直接上方之方式配置的相變記憶體構件是由選擇電晶體藉由共同通路(vias)而致動並接觸的。
亦已開發多層製程以用於其他記憶體技術。舉例而言，在Lai等人之「A Multi-Layer Stackable Thin-Film Transistor(TFT)NAND-Type Flash Memory」(IEEE國際電子元件會議，2006年12月11日至13日)中；以及在Jung等人之「Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node」(IEEE國際電子元件會議，2006年12月11日至13日)中，將薄膜電晶體技術應用於電荷捕集記憶體技術。
而且，在Johnson等人的「512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells」(2003年11月的IEEE固態電路期刊第38卷11期(IEEE J. of Solid-State Circuits,vol. 38,no. 11))中，已將交叉點陣列(cross-point array)技術應用於反熔絲(anti-fuse)記憶體。在Johnson等人描述之設計中，提供多個字元線層及位元線層，其中在交叉點處具有記憶體構件。記憶體構件包括連接至字元線之p+多晶矽陽極，以及連接至位元線之n-多晶矽陰極，其中陽極與陰極藉由反熔絲材料而分離。
在Haring-Bolivar等人、Lai等人、Jung等人以及Johnson等人描述之製程中，針對每一記憶體層存在若干關鍵微影步驟。因此，製造元件所需之關鍵微影步驟的數目由所構建之層的數目倍增。關鍵微影步驟是昂貴的，且因此需在製造積體電路之過程中使關鍵微影步驟減至最少。因此，儘管使用3D陣列達成較高密度之益處，但較高製造成本限制所述技術之使用。
在Tanaka等人的「Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory」(2007 VLSI技術討論會技術論文彙編(2007 Symposium on VLSI Technology Digest of Technical Papers)；2007年6月12日至14日，第14至15頁)中描述另一結構，其在電荷捕集記憶體技術中提供垂直「反及」(NAND)單元。Tanaka等人描述之結構包含具有類似於NAND閘而操作之垂直通道的多閘極場效電晶體結構，其使用矽-氧化物-氮化物-氧化物-矽(silicon-oxide-nitride-oxide-silicon，SONOS)電荷捕集技術來在每一閘極/垂直通道界面處產生儲存位點。所述記憶體結構是基於配置為用於多閘極單元之垂直通道的半導體材料柱，其具有鄰近於基板之下部選擇閘極、位於頂部之上部選擇閘極。使用與所述柱相交之平面電極層來形成多個水平控制閘極。用於控制閘極之平面電極層不需要關鍵微影，且因此節省成本。然而，在上述垂直單元之每一者的頂部及底部需要關鍵微影步驟。而且，在可以此方式成層之控制閘極的數目上存在限制，所述數目由諸如垂直通道之傳導性、所使用之程式化及抹除過程等因素決定。
需要提供一種具有較低製造成本之用於三維積體電路記憶體的結構，其包含可靠的、非常小的記憶體構件。
一種3D記憶體元件是基於電極柱陣列及多個電極平面的，所述多個電極平面在界面區與所述電極柱相交，所述界面區包含相變記憶體構件。可使用二維解碼來選擇所述電極柱，且可使用第三維上之解碼來選擇所述多個電極平面。
描述一實施例，所述實施例包括積體電路基板，其具有記憶體單元存取層，所述記憶體單元存取層具有存取元件陣列及對應的位於頂面上之觸點陣列。多個導電層位於存取元件陣列上方或下方，藉由絕緣層彼此分離且與所述存取元件陣列分離。電極柱陣列延伸穿過所述多個導電層及絕緣層。電極柱(諸如)藉由接觸觸點陣列中之觸點而耦接至對應的存取元件。記憶體構件位於所述柱與所述導電層之間的界面區中，其中所述記憶體構件中之每一者包括與臨界值切換元件(諸如固體電解質層或穿隧介電質層)串聯之可程式化相變記憶體構件。
在替代例中，可使用薄膜電晶體或相關技術在導電層上或之間形成存取元件陣列。
列解碼電路及行解碼電路耦接至存取元件陣列，且用以回應於位址而選擇電極柱。平面解碼電路耦接至多個導電層，且用以回應於位址而選擇導電層。而且，平面解碼電路用以在選定導電層之界面區中使臨界值切換元件偏置至導電狀態，且在未選定導電層之界面區中使臨界值切換元件偏置至非導電狀態。
描述電極柱，其包含呈導電材料芯之形式的接觸觸點陣列中之對應觸點的導體，以及位於所述芯與所述多個導電層之間的記憶體材料層及臨界值切換材料層。記憶體構件中之可程式化構件包括界面區之記憶體材料層中的主動區。記憶體構件中之可程式化構件包括芯與導電層之間的界面區之記憶體材料層中的主動區。
記憶體單元存取層中之存取元件在本文所述之各種實施例中包括垂直電晶體或水平電晶體，其中位元線及字元線耦接至所述電晶體之汲極及閘極。
使用毯覆式沈積製程序列來形成所述多個導電層，其中進行圖案化以組態所述層之周邊以便與平面解碼電路接觸。可使用漸縮蝕刻(tapered etching)製程來圖案化導電層，使得連續層在錐體(taper)上後退以形成突出部分(ledges)，且沿所述錐體形成接觸所述層之突出部分的觸點。
在另一實施例中，導電層具有沿周邊之翼片，所述翼片經組態以與解碼電路接觸。積體電路包含上覆於所述多個導電層上之佈線層，其包含將所述多個導電層耦接至解碼電路的導體。導電插塞接觸所述多個導電層上之翼片，且向上延伸至佈線層。在一實施例中，翼片以交錯方式配置，其減少平面解碼電路之佔據面積。交錯翼片用以使得耦接至兩個或兩個以上導電層上之交錯翼片的導電插塞以列配置，所述列在由所述交錯翼片界定之方向上延伸。
描述一種記憶體元件之製造方法，其包含：形成記憶體單元存取層或另外形成存取元件陣列；形成上覆於所述記憶體單元存取層中之存取元件陣列上的多個導電層；形成延伸穿過所述多個導電層之電極柱陣列，其具有在所述多個導電層中之電極柱之間的界面區中的記憶體構件。用於形成所述多個導電層之技術包含：在存取層之頂面上沈積層間介電質之後，針對每一導電層，執行形成毯覆式導電材料層之步驟以及在所述毯覆式導電材料層上形成毯覆式絕緣材料層的步驟。用於形成電極柱陣列中之電極柱的技術包含：在提供所述多個導電層之後，界定在觸點陣列中之觸點中的一個觸點上方穿過所述多個導電層的電極通路。接下來，在所述電極通路之側壁上形成諸如固體電解質材料或穿隧介電質的臨界值切換材料層。接著，在臨界值切換材料層上形成相變記憶體材料層。最後，使用一或多層導電材料(諸如類似鎢之金屬，或類似氮化鈦之金屬氮化物)，以電極材料填充記憶體材料層上之電極通路。
在本文所述之一製程中，用於在毯覆式導電材料層上界定周邊之技術包含圖案化所述周邊之多個部分，使得所述部分包含經組態以與解碼電路接觸的翼片。在形成多個導電層之後形成多個導電插塞，其接觸所述多個導電層上之相應翼片，且向上延伸至上覆於所述多個導電層上之佈線平面。所述翼片可以交錯方式配置，使得耦接至不同導電層上之交錯翼片的導電插塞以列配置，所述列在由所述交錯翼片界定之方向上延伸。
描述一種新穎的三維相變記憶體單元結構。在一個實例中，使用字元線及位元線來驅動存取電晶體。存取電晶體連接至電極柱。電極柱包含相變材料層，以及位於所述相變材料層上之臨界值切換層。電極柱之側壁由多個導電材料層接觸。每一導電層與電極柱之周邊之間的界面區提供一記憶體單元。
藉由啟用耦接至用於選定柱之存取電晶體的一個字元線及一個位元線來對記憶體單元進行程式化。柱與選定導電層之間的偏壓將使臨界值切換材料偏置於導電狀態，且對界面區中之相變材料之主動區進行程式化。藉由感測選定位元線上或導電層中與選定記憶體單元耦接之一者上的電流來讀出資訊。
在審閱所附之圖式、詳細描述及申請專利範圍後可見本發明之其他態樣及優點。
參看圖1至圖16而提供本發明之實施例的詳細描述。
圖1為多層級記憶體單元之剖面。所述記憶體單元形成於積體電路基板上，所述積體電路基板在此實例中包含半導體主體10，其具有以列形式圖案化於表面上的溝渠隔離結構12。在溝渠隔離結構12之間，沈積植入物以形成埋入式擴散位元線11。繪示用於單個記憶體單元柱之存取元件，其由具有由閘極介電層29圍繞之汲極13、通道14以及源極15的垂直FET電晶體組成。絕緣層16上覆於半導體主體10上。字元線17橫穿陣列，且圍繞垂直FET之通道14。在此實例中，絕緣層18上覆於字元線上。矽化物層19形成於源極15之頂部。在此實例中，在矽化物層19上界定並圖案化鎢接觸焊墊20。在此實例中包含層21及層22之絕緣層上覆於接觸焊墊20上。圖中所示結構之自接觸焊墊20至半導體主體10(例如，塊體矽)的部分為包含記憶體單元存取層100之積體電路基板的部分。
多個導電層23-1至23-n上覆於接觸焊墊20以及絕緣層22上。絕緣層24-1至24-(n-1)使導電層23-1至23-n彼此分離。導電層23-1至23-n可包括耐火金屬(諸如W)或其他材料(例如TiN或TaN)。或者，導電層23-1至23-n可包括(例如)來自Ti、Mo、Al、Ta、Cu、Pt、Ir、La、Ni、N、O及Ru之族群的一或多個元素。在其他實施例中，導電層23-1至23-n可包括摻雜多晶矽、其他摻雜半導體材料。
絕緣層24-n覆蓋頂部導電層23-n。在替代實施例中，可使用(例如)薄膜電晶體技術來在所述多個導電層上或導電層之間形成存取元件陣列。
用於多層級記憶體之電極柱由包含中央導電芯25之導體組成，所述中央導電芯25例如由鎢或其他合適電極材料製成，且由相變記憶體材料層26及位於相變記憶體材料層26上之臨界值(threshold)切換材料層27圍繞，其中所述臨界值切換材料接觸所述多個導電層，或以其他方式與所述多個導電層電流連通。
所述多個導電層23-1至23-n與柱之間的界面區(諸如區30)包含相變記憶體構件，其包括與如下文參看圖3更詳細地闡釋之臨界值切換構件串聯的可程式化構件。
層26包含基於相變之記憶體材料，諸如基於硫族化物之材料及其他材料。硫族化物包含形成週期表之第VIA族之部分的四個元素氧(O)、硫(S)、硒(Se)及碲(Te)中之任一者。硫族化物包括硫族元素與更具電正性之元素或自由基之化合物。硫族化物合金包括硫族化物與其他材料(諸如過渡金屬)之組合。硫族化物合金通常含有來自元素週期表之第IVA族之一或多個元素，諸如鍺(Ge)及錫(Sn)。通常，硫族化物合金包含包括銻(Sb)、鎵(Ga)、銦(In)及銀(Ag)中之一或多者的組合。技術文獻中已描述了許多基於相變之記憶體材料，包含以下各項之合金：Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te及Te/Ge/Sb/S。在Ge/Sb/Te合金族中，較廣範圍之合金組合物可起作用。可將所述組合物表徵為Tea Geb Sb100-(a+b) 。一位研究者已將最有用之合金描述為在所沈積材料中具有大大低於70%之Te平均濃度，典型地低於約60%且通常在自低至約23%至多達約58%之範圍內變動之Te，最佳為約48%至58%之Te。Ge之濃度為高於約5%，且在材料中自約8%之低值至約30%之平均值的範圍內變動，保持於大致為低於50%。最佳的是，Ge之濃度在自約8%至約40%之範圍內變動。此組合物中之主要組成元素之其餘部分為Sb。此等百分比為原子百分比，其總計為組成元素之原子的100%。(Ovshinsky之5,687,112專利第10至11行)。另一研究者評估之特定合金包含Ge2 Sb2 Te5 、GeSb2 Te4 及GeSb4 Te7 (Noboru Yamada，「Potential of Ge-Sb-Te Phase-Change Optical Disks forHigh-Data-Rate Recording」，SPIE v.3109，第28至37頁(1997))。更一般而言，諸如鉻(Cr)、鐵(Fe)、鎳(Ni)、鈮(Nb)、鈀(Pd)、鉑(Pt)及其混合物或合金的過渡金屬可與Ge/Sb/Te組合，以形成具有可程式化電阻特性之相變合金。Ovshinsky之‘112中在第11至13行處給出可使用之記憶體材料之特定實例，所述實例以引用之方式併入本文中。
在一些實施例中，用雜質來摻雜硫族化物及其他相變材料，以使用經摻雜之硫族化物來改變記憶體構件之導電性、轉變溫度、熔化溫度以及其他特性。用於摻雜硫族化物之代表性雜質包含氮、矽、氧、二氧化矽、氮化矽、銅、銀、金、鋁、氧化鋁、鉭、氧化鉭、氮化鉭、鈦以及氧化鈦。
相變合金能夠以第一結構狀態及第二結構狀態在單元之主動通道區中作局部次序的切換，在第一結構狀態下，材料處於大致為非晶固相，且在第二結構狀態下，材料處於大致為結晶固相。此等合金至少為雙穩態的(bistable)。術語「非晶」用於指代相對較低次序的結構，較單晶體無序，其具有可偵測特徵，諸如比結晶相較高之電阻率。術語「結晶」用於指代相對較高次序的結構，較非晶結構有序，其具有可偵測特徵，諸如比非晶相更低之電阻率。通常，相變材料可在於完全非晶狀態與完全結晶狀態之間的範圍(spectrum)內具有局部次序之不同的可偵測狀態之間的電切換。受非晶相與結晶相之間的改變影響之其他材料特徵包含原子次序、自由電子密度及活化能量。材料可切換至不同固相中或兩個或兩個以上固相之混合物中，從而提供完全非晶狀態與完全結晶狀態之間的灰階(gray scale)。材料中之電特性可相應地改變。
相變合金可藉由電脈衝之施加而自一個相態改變至另一相態。已觀察到，較短、較高振幅之脈衝趨於使相變材料改變至大致為非晶狀態。較長、較低振幅之脈衝趨於使相變材料改變至大致為結晶狀態。較短、較高振幅之脈衝中之能量足夠高以允許斷開結晶結構之鍵結，且足夠短以防止原子重排序(realigning)為結晶狀態。可以決定適當的脈衝剖面，不需要過度(undue)的實驗，特別適用於特定相變合金。在本揭露案之以下部分中，將相變材料稱為GST，且將理解，可使用其他類型之相變材料。對實施本文所述之PCRAM有用的材料為Ge2 Sb2 Te5 。
用於形成硫族化物材料之例示性方法使用PVD濺鍍或磁控管濺鍍方法，其中源氣體為在1毫托至100毫托之壓力下的Ar、N2 及/或He等。沈積通常在室溫下完成。可使用具有1至5之縱橫比的準直儀(collimator)來改良填充效能。為改良填充效能，亦使用幾十伏至幾百伏之DC偏壓。另一方面，可同時使用DC偏壓與準直儀之組合。
用於形成硫族化物材料之另一例示性方法使用化學氣相沈積(chemical vapor deposition，CVD)，諸如標題為「Chemical Vapor Deposition of Chalcogenide Materials」之美國公開案第2006/0172067。號中所揭露之CVD，所述美國公開案以引用之方式併入本文中。
選擇性地在真空或N2 環境中執行沈積後退火處理(post-deposition annealing treatment)，以改良硫族化物材料之結晶狀態。退火溫度典型地在自100℃至400℃之範圍內變動，其中退火時間小於30分鐘。
圖2繪示包含導電芯25、相變材料層26以及臨界值切換材料層27之電極柱的俯視圖佈局。位元線11佈設於第一方向上，且字元線17佈設於正交的方向上。電極柱由環形臨界值切換材料層27圍繞。柱中之臨界值切換材料層與所述導電材料層中之每一者之間的環形界面界定包含記憶體構件之界面區。
圖3繪示包含導電層23-2、相變材料層26、導電芯25以及臨界值切換材料層27之記憶體構件(諸如在界面區30中)的一部分。在原生狀態下，相變材料層26可具有大約5至50奈米之厚度。主動區鄰近於每一導電層而形成，其回應於在如下文參看圖16而描述之晶片上控制電路(on-chip control circuit)之控制下所施加的設定及重設脈衝而改變電阻。讀取脈衝可包括在如下文參看圖16而描述之晶片上控制電路之控制下所施加的1至2伏之脈衝，其具有取決於組態之脈衝寬度。讀取脈衝可比程式化脈衝短得多。
層27中所使用之臨界值切換材料之特徵在於，在柱上之未選定單元所受到(encounter)之相對較低的電壓下具有較低導電性，且在柱上之選定單元所受到之用於讀取、設定及重設之操作電壓下具有相對較高的導電性。可使用諸如固體電解質(例如矽化鍺)之材料或其他合適材料來構建臨界值切換層27。對於其他代表性固體電解質材料，請參見Gopalakrishnan之美國專利第7,382,647號。或者，可將諸如具有大約10至50奈米之厚度之二氧化矽層的穿隧介電層用作臨界值切換材料，其中低電場允許可忽略之穿隧電流，且在較高電場下允許如讀取、設定及重設記憶體材料中之主動區所需的較大穿隧電流。
圖4為圖1之結構的示意性說明。電極柱40耦接至存取電晶體41，使用位元線42及字元線43來選擇存取電晶體41。多個記憶體構件44-1至44-n連接至柱40。所述記憶體構件中之每一者包含與臨界值切換構件49串聯之可程式化構件48。此串聯電路示意圖表示圖3中所示之結構。可程式化構件48由常用於指示可程式化電阻之符號表示。
記憶體構件44-1至44-n中之每一者耦接至對應的電極平面45-1至45-n，其中電極平面由本文所述之導電材料層提供。電極平面45-1至45-n耦接至平面解碼器46，其回應於位址而將諸如接地47之電壓施加至選定電極平面，使得記憶體構件中之臨界值切換構件導電，且將電壓施加至未選定電極平面或使未選定電極平面浮置，使得記憶體構件中之臨界值切換構件不導電。
圖5提供2個字元線×2個位元線×n個平面之三維3D記憶體陣列的示意性表示。所述陣列包含字元線60及61，其與位元線62及63相交。存取元件64、65、66及67位於位元線與字元線之間的交叉點處。每一存取元件耦接至對應的電極柱68、69、70、71。每一電極柱包含深度為數目「n」個平面之記憶體構件堆疊。因此，柱68耦接至記憶體構件72-1至72-n。柱69耦接至記憶體構件73-1至73-n。柱70耦接至記憶體構件74-1至74-n。柱71耦接至記憶體構件75-1至75-n。圖5中未說明導電層以避免使圖變得擁擠。圖5所示之2×2×n陣列可擴展至具有任一數目之平面的數千字元線乘以數千位元線的陣列。在代表性實施例中，平面之數目n可為2的冪以促進二進制解碼，諸如4、8、16、32、64、128等。
圖6為具有水平FET存取元件之多層級記憶體單元的剖面。所述記憶體單元形成於積體電路基板上，所述基板在此實例中包含半導體主體80。選擇性之溝渠隔離結構(未圖示)可形成於表面上以隔離元件之區。沈積植入物以形成用於所述存取元件之源極81及汲極82。字元線83形成於閘極介電質上位於源極81與汲極82之間。層間介電質95上覆於半導體主體80中之字元線上。插塞84及插塞86形成於層間介電質95中。插塞84延伸至包含位元線BL之經圖案化的金屬層。插塞86延伸至層間介電質95之表面，且提供上面形成有電極柱的觸點(contact)。因此，如圖6之實施例中之括號所識別的記憶體單元存取層101包含自層間介電質95之表面至半導體主體80的構件。
在此實例中，多個導電層93-1至93-4上覆於絕緣層92上，絕緣層92形成於記憶體單元存取層101之頂面上。絕緣層94-1至94-3分離所述多個導電層。絕緣層94-4上覆於導電層93-4上。
多層級電極柱由導電芯組成，所述導電芯包含由相變記憶體材料層88圍繞之中央導電芯87。臨界值切換材料層89形成於相變記憶體材料層88與多個導電層93-1至93-4之間，從而在界面區中提供記憶體構件(例如，構件90)。
圖7繪示使用類似於圖6所示之水平FET之存取元件而製成之陣列的佈局圖。所述陣列包含用於電極柱之接觸插塞86以及用於位元線之接觸插塞84。位元線85-1至85-4以對角線方式配置。字元線83-1至83-2在此佈局中以垂直方式配置。用於存取元件之主動區96經如圖所示圖案化，使得其本質上與字元線83-1、83-2正交。溝渠隔離結構(未圖示)可選擇性地在鄰近存取電晶體中之接觸插塞86之行與接觸插塞84之行之間，與字元線83-1、83-2平行形成。
圖8A、圖8B以及圖8C說明用於界定導電材料層之周邊以便與個別層形成接觸以用於解碼的製程中的階段。在圖8A中，說明一堆疊，其包含交替之導電層147、148、149及150以及絕緣層165、166、167、168及169。導電層及絕緣層是以交替毯覆式沈積而沈積，其可覆蓋積體電路上之整個記憶體區域，如圖中之虛線所指示。為圖案化導電層之周邊，形成罩幕160。罩幕160具有漸縮側邊(tapered sides)170。為製作罩幕，可在結構上沈積諸如氮化矽之硬罩幕材料層。接著可圖案化一光阻層，且對其進行蝕刻以在光阻上界定漸縮側邊。接著蝕刻所得結構，其中光阻層中之錐體(taper)被轉移至硬罩幕160上之對應錐體170。
如圖8B所說明，接著以類似方式使用漸縮硬罩幕160。應用諸如反應性離子蝕刻(reactive ion etch，RIE)之蝕刻製程，使得硬罩幕上之錐體170被轉移至導電層堆疊中之對應錐體175。在一些實施例中，可能省略硬罩幕，且在堆疊之錐體蝕刻期間使用漸縮光阻構件。導電層150至147之邊緣是參差的(staggered)，以形成圍繞其周邊之架。由每一層之間的參差產生之架的寬度可由導電層之間的絕緣層之厚度以及錐體175之斜率決定。
用於在硬罩幕上界定錐體170以及在導電層堆疊上界定錐體175的蝕刻製程可為一連續蝕刻製程。或者，可使用第一製程在硬罩幕160上界定錐體170，且使用第二蝕刻製程在導電層堆疊上界定錐體175。
圖8C說明所述製程中之下一階段。在形成錐體175之後，沈積絕緣填充物176，且在導電層150至147之堆疊上進行平坦化。接著，使用微影步驟來界定通路(vias)，所述微影步驟同時圖案化用於所有層的所有通路。應用一蝕刻製程，其相對於填充層176，對導電層150至147中之導電材料具有高度選擇性。以此方式，所述通路中之每一者內的蝕刻製程在對應的導電層上停止。接著在記憶體陣列區域之周邊之一側上用插塞177、178、179、180且在記憶體陣列區域之周邊之另一側上用插塞181、182、183、184來填充所述通路。因此，導電層之周邊被圖案化，且僅使用用以界定硬罩幕160之一個微影步驟以及用以界定用於接觸插塞177至184之通路的位置的一個微影步驟來形成觸點通路。而且，僅應用兩個(或可能三個)蝕刻製程來形成圖8C所示之結構。
圖9為陣列之一部分的簡化佈局圖，其繪示用於將導電層堆疊連接至平面解碼電路之上覆內連件。在圖9中，說明頂部介電層150。電極柱(例如，柱151)陣列穿透介電層150。
與圖8C中之插塞177至184對應之接觸插塞(諸如插塞152)沿導電層之周邊配置。位於沿層150之邊緣之一列中的接觸插塞耦接至上覆於導電層堆疊上之內連線153。
導電層149延伸至內連線153之右方，且位於沿層149之邊緣之一列中的接觸插塞耦接至內連線154。導電層148延伸至內連線154之右方，且位於沿層148之邊緣之一列中的接觸插塞耦接至內連線155。導電層147延伸至內連線155之右方，且位於沿層147之邊緣之一列中的接觸插塞耦接至內連線156。
上覆於陣列上之內連佈線153至156之簡化視圖意欲說明將記憶體陣列中之多個導電層耦接至內連佈線的方式。所述內連佈線接著可在必要時路由至(route)平面解碼電路。而且，內連佈線可用以在陣列區域上更均勻地分佈施加至導電材料層之偏壓。
圖10及圖11共同繪示包含3D相變記憶體陣列之積體電路之一部分以及包含多個金屬化層及周邊電路之記憶體單元存取結構的剖面。而且，可在下文參看圖12A至圖12B陳述之製造方法的描述期間參考圖10及圖11。
圖10繪示形成於基板200上之記憶體陣列的一部分。水平FET由基板200中之源極區163、265及汲極區164、266界定。溝渠隔離結構161及162隔離基板中之區。字元線267及268提供用於存取元件之閘極。層間介電質269上覆於字元線267、268及基板上。接觸插塞270、271、272及273延伸穿過層間介電質269到達具有介電填充物278之上覆金屬化平面，所述介電填充物278包含耦接至觸點271及273之位元線275及274。接觸焊墊277及276延伸穿過介電填充物278到達上覆觸點281及280，觸點281及280延伸穿過另一層間介電質279。具有介電填充物284之另一金屬化平面上覆於介電層279上。接觸焊墊282及283耦接至下伏觸點280及281，從而提供到達下方存取元件之連接。在此實施例中，記憶體單元存取層185包含自接觸焊墊282、283穿過存取電晶體的組件，所述存取電晶體包含位於基板200中之源極區及汲極區163、164、265、266。基板200可包括位於此項技術中已知之用於支撐積體電路之絕緣層或其他結構上的塊體矽或矽層。
多個電極柱配置於記憶體單元存取層185之頂部。在此圖中，說明包含導電芯192、相變材料層193及臨界值切換材料層194之第一電極柱，以及包含導電芯189、相變材料層190及臨界值切換材料層191之第二電極柱。第一電極柱耦接至焊墊282。第二電極柱耦接至焊墊283。絕緣層186-1上覆於記憶體單元存取層185上。導電層187-1上覆於絕緣層186-1上。交替的導電層187-2至187-4以及絕緣層186-2至186-4形成於導電層187-1之頂部。介電填充物188上覆於所述結構上，且具有平面頂面。
圖11繪示所述元件至周邊區中之延續，在周邊區中形成支援電路，且形成與所述多個導電層之接觸。在圖11中，說明包含導電芯189、相變材料層190及臨界值切換材料層191之電極柱，且應用與圖10中所使用之參考標號相同的參考標號。如圖11所示，周邊元件包含由源極204、閘極207以及汲極203形成之電晶體。圖中說明溝渠隔離結構201。在周邊中構建許多種元件，以支援積體電路上之解碼邏輯及其他電路。在周邊電路中使用多個金屬化平面以用於佈線內連。因此，接觸插塞210自汲極203延伸至上部層中之導線217。插塞218自導線217延伸至另一層中之導線219。
導電層187-1至187-4耦接至對應的接觸插塞223、222、221、220。內連線224至227耦接至所述插塞，且提供所述多個導電層與元件周邊中之解碼電路之間的內連。
圖12A及圖12B包含可應用於製作圖10及圖11所示之結構的製造方法的流程圖。出於此應用之目的，第一步驟300涉及形成包含位元線、字元線、存取元件(包含垂直或水平電晶體)以及觸點的記憶體單元存取層。在此階段，積體電路基板上之周邊電路亦如圖11所示而形成。由於此製程，元件之記憶體區中之記憶體單元存取層的頂面具有觸點陣列，其包含圖10之觸點282、283。在此階段，已應用標準製造技術，包含形成周邊電路及存取元件所需之所有必要的圖案化及蝕刻步驟。應使用耐火金屬(諸如鎢)來製作記憶體單元存取層中所涉及之觸點及內連件，使得大量導電材料層之沈積中所涉及之熱預算不會干擾下伏內連件。
接下來，在記憶體單元存取層上沈積層間介電質(例如，186-1)(301)。所述層間介電質可為二氧化矽、氮氧化矽、氮化矽或其他層間介電質材料。接下來，執行導電層與介電層之交替毯覆式沈積(302)。此等毯覆式沈積提供充當電極平面之多個導電層(例如，187-1至187-4)。所述導電層之典型厚度可為大約50奈米。所述介電層在導電層之間形成絕緣。在一個實例中，絕緣層之厚度亦可為大約50奈米。其他實例將包含如特定實施方案所要或所需之導體材料以及介電層的較大或較小厚度。在下一階段中，應用微影圖案來界定並打通用於記憶體單元柱之通路，所述通路穿過所述多個導體平面到達記憶體單元存取層上之對應觸點(303)。可應用反應性離子蝕刻製程來形成穿過二氧化矽及導體層之較深的高縱橫比孔，以提供用於電極柱之通路。
在打通所述通路之後，在電極柱通路之側壁上沈積臨界值切換材料層(304)。可使用原子層沈積或化學氣相沈積技術來沈積臨界值切換材料。
在形成臨界值切換層之後，在電極柱通路之側壁上之臨界值切換材料上沈積相變材料層(305)。接下來，在相變材料層上沈積薄電極材料層，以在後續蝕刻期間保護相變層(306)。
對臨界值切換材料、薄膜電極材料及相變材料之所得層進行各向異性(anisotropic)蝕刻以打通電極柱通路之底部，從而暴露下伏觸點(307)。在下一步驟中，在電極柱通路內沈積中央電極材料(308)。中央電極材料可與用於步驟306中所形成之薄膜的電極材料相同或不同。在沈積中央電極材料之後，使用化學機械拋光製程或其他平坦化製程來回蝕且平坦化所得結構。
接下來，在所述結構上沈積層間介電質(步驟309)。
在形成所述多個導電層之後，使用上文參看圖8A至圖8C而描述之錐體蝕刻製程在導電層之周邊上界定觸點區域(310)。可使用替代技術在所述多個導電層上界定觸點區域。替代技術可涉及所述製程中之其他階段處的微影步驟，如根據所應用之技術將理解。在圖案化導電層之周邊之後，在結構上沈積絕緣填充物並使其平坦化。接著，打通穿過絕緣填充物到達導電層之周邊上之觸點的通路(311)。
使用鎢或其他觸點材料來填充所述通路，且應用金屬化製程來在到達元件上之導電層及平面解碼電路的觸點之間提供內連(312)。最後，應用線BEOL製程之後端來完成積體電路(313)。
圖13A及圖13B說明用於所述多個導電層中之導電層的圖案，其可應用於在包含交錯翼片(tabs)之平面的周邊上建立內連觸點。因此，圖13A繪示平面A，且圖13B繪示平面B。翼片250A至253A沿平面A之周邊而定位。翼片251B至253B沿平面B之周邊而定位。將所述翼片定位成使得當所述平面如圖14所示而重疊時，觸點(例如，觸點255)交錯，且界定一平行於所述平面之周邊的列。因此，用於平面A之內連線以及用於平面B之內連線可平行路由至所述翼片。此技術顯著減少與所述多個導電層形成接觸所需之面積。交錯可涉及2個以上平面，諸如8個或16個平面或更多，以便顯著節省元件上之更多面積。然而，此技術涉及具有導電材料之每一毯覆式沈積的非關鍵圖案步驟。
圖15說明一種用於擴展可應用於單個電極柱中之導電層之數目，同時維持相對較小之通路佔據面積(footprint)的技術。圖15所示之結構包含一堆疊，其包含若干導電層組400-402。第一導電層組400是藉由使絕緣體層423-1至423-4及導電層424-1至424-4在層422上交替而形成。其他組401及402包括類似結構。所述製程涉及首先製作第一導電層組400，界定穿過所述第一組之電極柱通路，以及形成電極柱之第一部分。電極柱接觸焊墊420之第一部分耦接至存取元件419。接下來，在所述第一組上界定第二導電層組401。穿過第二組401界定電極柱通路，其打通到達電極柱之第一部分的通路。在穿過第二導電層組401之通路內形成電極柱之第二部分。
如圖中所示，電極柱之第二部分可與第一部分稍微失對準(misaligned)，因為用於界定通路之微影製程中涉及對準容許度。選擇性地，可藉由微影步驟在層之間形成接觸焊墊431，以在需要時在微影製程中提供較佳之對準容許度。最後，穿過第三導電層組402界定電極柱通路，其打通到達電極柱之第二部分的通路。在第三導電層組402內形成電極柱之第三部分。圖式亦繪示電極柱之第二部分與第三部分之間的選擇性接觸焊墊432。儘管圖式繪示每組四個導電層，但所述技術之實施例可涉及使用較大數目之平面(諸如16個、32個、64個或更多)，其接觸電極柱之每一堆疊部分。
圖16為根據本發明實施例之積體電路的簡化方塊圖。積體電路475包含位於半導體基板上之如本文所述而構建之3D記憶體陣列460。列解碼器461耦接至多個字元線462，且沿記憶體陣列460中之列而配置。行解碼器463耦接至沿記憶體陣列460中之行而配置之多個位元線464，以用於自陣列460中之記憶體單元讀取資料並對其進行程式化。平面解碼器458在線459上耦接至記憶體陣列460中之多個電極平面。位址在匯流排465上供應至行解碼器463、列解碼器461以及平面解碼器458。區塊466中之感測放大器及資料輸入結構在此實例中經由資料匯流排467耦接至行解碼器463。資料經由資料輸入線471自積體電路475上之輸入/輸出埠或自積體電路475內部或外部之其他資料源供應至區塊466中之資料輸入結構。在所說明之實施例中，積體電路上包含其他電路474，諸如通用處理器或特殊應用電路，或提供由薄膜熔絲相變記憶體單元陣列支援之晶片上系統(system-on-a-chip)功能性之模組的組合。資料經由資料輸出線472自區塊466中之感測放大器供應至積體電路475上之輸入/輸出埠，或供應至積體電路475內部或外部之其他資料目的地。
在此實例中使用偏壓配置狀態機469構建之控制器控制經由區塊468中之電壓源產生或提供之偏壓配置供電電壓(諸如讀取及程式化電壓)的施加。可使用此項技術中已知之特殊用途邏輯電路來構建所述控制器。在替代實施例中，控制器包括可在同一積體電路上構建之通用處理器，其執行電腦程式以控制元件之操作。在又一些實施例中，特殊用途邏輯電路與通用處理器之組合可用於構建所述控制器。
雖然藉由參考上文詳細描述之較佳實施例及實例而揭露本發明，但應理解，此等實例意欲具有說明性而非限制性意義。預期熟習此項技術者將容易想到修改及組合，所述修改及組合將在本發明之精神以及隨附申請專利範圍之範疇內。
10、80．．．半導體主體
11、42、62、63、85-1、85-2、85-3、85-4、274、275、464．．．位元線
12、161、162、201．．．溝渠隔離結構
13、82、164、203、266．．．汲極/汲極區
14．．．通道
15、81、163、204、265．．．源極/源極區
16、18、21、22、24-1、24-2、24-3、24-(n-2)、24-(n-1)、24-n、92、94-1、94-2、94-3、94-4、95、165~169、186-1、186-2、186-3、186-4、269、279、422、423-1、423-2、423-3、423-4．．．絕緣層/層/層間介電質/介電層/絕緣體層
17、43、60、61、83、83-1、83-2、267、268、462．．．字元線
19．．．矽化物層
20、276、277、282、283、420、431~432．．．接觸焊墊
23-1、23-2、23-3、23-(n-1)、23-n、93-1、93-2、93-3、93-4、147~150、187-1、187-2、187-3、187-4、424-1、424-2、424-3、424-4．．．導電層
25、87、189、192．．．中央導電芯
26、88、190、193．．．相變記憶體材料層/相變材料層/層
27、89、191、194．．．臨界值切換材料層/臨界值切換層/層
29．．．閘極介電層
30．．．界面區/區
40、68~71、151．．．電極柱/柱
41．．．存取電晶體
44-1、44-2、44-3、44-n、72-1、72-2、72-3、72-n、73-1、73-2、73-3、73-n、74-1、74-2、74-3、74-n、75-1、75-2、75-3、75-n、90．．．記憶體構件/構件
45-1、45-2、45-3、45-n．．．電極平面
46．．．平面解碼器
47．．．接地
48．．．可程式化構件
49．．．臨界值切換構件
64~67、419．．．存取元件
84、86、152、177~184、210、218、220~223、270~273、255、280、281．．．插塞/接觸插塞/觸點
96．．．主動區
100、101、185．．．記憶體單元存取層
153~156、224~227．．．內連線/內連佈線
160．．．罩幕/硬罩幕
170．．．漸縮側邊/錐體
175．．．錐體
176．．．絕緣填充物/填充層
188、278、284．．．介電填充物
200．．．基板
207．．．閘極
217、219．．．導線
250A、251A、252A、253A、251B、252B、253B．．．翼片
400~402．．．導電層組
458．．．平面解碼器
459．．．線
460．．．3D記憶體陣列/記憶體陣列
461．．．列解碼器
463．．．行解碼器
465、467‧‧‧匯流排
466、468‧‧‧區塊
469‧‧‧偏壓配置狀態機
471‧‧‧資料輸入線
472‧‧‧資料輸出線
474‧‧‧其他電路
475‧‧‧積體電路
BL‧‧‧位元線
WL‧‧‧字元線
圖1為垂直FET存取元件以及包含用於如本文所述之元件之多個記憶體構件之多層級電極柱的剖面。
圖2為已移除導電層之多層級電極柱的俯視圖。
圖3說明包含記憶體構件及臨界值切換構件之多層級電極柱上的界面區。
圖4為諸如圖1所示之存取元件及多層級電極柱的示意圖。
圖5為由多層級電極柱組成之記憶體陣列之2×2×n部分的示意圖。
圖6為包含用於如本文所述之元件之多個記憶體構件的多層級電極柱中之水平FET存取元件的剖面。
圖7為繪示用於如圖6所示而構建之記憶體陣列之字元線及位元線的佈局圖。
圖8A至圖8C說明用於基於漸縮蝕刻而圖案化導電層之周邊的製程中的階段。
圖9為導電層及用於將導電層連接至平面解碼電路之內連佈線的佈局圖。
圖10為包含水平FET存取元件之記憶體陣列之一部分的剖面。
圖11為記憶體陣列之另一部分的剖面，所述部分包含水平FET存取元件以及導電層之周邊上的內連插塞及通路。
圖12A至圖12B為用於製造如本文所述之記憶體陣列之方法的流程圖。
圖13A至圖13B說明包含經配置以用於與內連通路及插塞形成接觸之交錯翼片的導電層之佈局。
圖14繪示包含交錯翼片以及用於與解碼電路內連之上覆佈線的導電層的俯視圖。
圖15為說明可用於極大數目之記憶體平面之電極柱堆疊的剖面圖。
圖16為包含具有列解碼電路、行解碼電路及平面解碼電路之3D記憶體陣列之積體電路的示意圖。
10．．．半導體主體
11．．．位元線
12．．．溝渠隔離結構
13．．．汲極
14．．．通道
15．．．源極
16、18、21、22、24-1、24-2、24-3、24-(n-2)、24-(n-1)、24-n．．．層/絕緣層
17．．．字元線
19．．．矽化物層
20．．．接觸焊墊
23-1、23-2、23-3、23-(n-1)、23-n．．．導電層
25．．．中央導電芯
26．．．相變記憶體材料層/相變材料層/層
27．．．臨界值切換材料層/臨界值切換層/層
29．．．閘極介電層
30．．．界面區/區
100．．．記憶體單元存取層
BL．．．位元線
WL．．．字元線

Claims (19)

  1. 一種記憶體元件，包括：積體電路基板，包含存取元件陣列；多個導電層，藉由絕緣層而彼此分離且與所述存取元件陣列分離；電極柱陣列，延伸穿過所述多個導電層，所述電極柱陣列中之所述電極柱接觸所述存取元件陣列中的對應存取元件，且界定所述電極柱的側邊與所述多個導電層中之導電層之間的界面區；以及所述界面區中之記憶體構件，所述記憶體構件中之每一者包括可程式化相變記憶體構件及臨界值切換構件。
  2. 一種記憶體元件，包含：積體電路基板，包含存取元件陣列；多個導電層，藉由絕緣層而彼此分離且與所述存取元件陣列分離；電極柱陣列，延伸穿過所述多個導電層，所述電極柱陣列中之所述電極柱接觸所述存取元件陣列中的對應存取元件，且界定所述電極柱與所述多個導電層中之導電層之間的界面區；所述界面區中之記憶體構件，所述記憶體構件中之每一者包括可程式化相變記憶體構件及臨界值切換構件；耦接至所述存取元件陣列之列解碼電路及行解碼電路，用以選擇所述電極柱陣列中之電極柱；以及耦接至所述多個導電層之平面解碼電路，用以在選定 導電層中之所述界面區中使所述臨界值切換構件偏置至導電狀態，且在未選定導電層中之界面區中使所述臨界值切換構件偏置至非導電狀態。
  3. 如申請專利範圍第1項所述之記憶體元件，其中所述電極柱陣列中之電極柱包括與對應存取元件電連通之導體，以及所述導體與所述多個導電層之間的相變記憶體材料層，其中所述記憶體構件中之每一者中之所述可程式化相變構件包括所述界面區之所述相變記憶體材料層中之主動區。
  4. 如申請專利範圍第1項所述之記憶體元件，其中所述存取元件陣列中之存取元件包括：電晶體，具有閘極、第一端子及第二端子；以及所述存取元件陣列包含耦接至所述第一端子之位元線、耦接至所述閘極之字元線，且其中所述第二端子耦接至所述電極柱陣列中之對應電極柱。
  5. 如申請專利範圍第1項所述之記憶體元件，其中所述存取元件陣列中之存取元件包括垂直電晶體。
  6. 如申請專利範圍第1項所述之記憶體元件，其中所述多個導電層具有周邊，且所述周邊之相應部分經組態以與解碼電路接觸。
  7. 如申請專利範圍第1項所述之記憶體元件，其中所述多個導電層具有周邊，且所述周邊之相應部分包含經組態以與解碼電路接觸之翼片，且所述記憶體元件包含：上覆於所述多個導電層上之佈線層，包含將所述多個 導電層耦接至解碼電路的導體；以及導電插塞，接觸所述翼片且向上延伸至所述佈線層。
  8. 如申請專利範圍第7項所述之記憶體元件，其中所述翼片以交錯方式配置，使得所述多個導電插塞中耦接至所述多個導電層中之不同導電層上之交錯翼片的導電插塞以列配置，所述列在由所述交錯翼片界定之方向上延伸。
  9. 如申請專利範圍第1項所述之記憶體元件，其中所述存取元件陣列下伏於所述多個導電層下。
  10. 如申請專利範圍第1項所述之記憶體元件，其中所述電極柱陣列中之電極柱包括與對應存取元件電連通之中央芯導體，以及位於所述中央芯導體上之相變記憶體材料層、位於所述相變記憶體材料層上且接觸所述多個導電層之臨界值切換材料層，其中所述相變記憶體構件中之每一者包括位於所述中央芯導體與所述臨界值切換材料層之間的所述界面區之所述相變記憶體材料層中之主動區。
  11. 如申請專利範圍第1項所述之記憶體元件，其中所述電極柱包括電極部分之相應堆疊，其中每一部分延伸穿過一組對應的所述多個導電層。
  12. 一種記憶體元件之製造方法，包括：形成存取元件陣列；在所述存取元件陣列下方或上方形成多個導電層，所述多個導電層藉由絕緣層而彼此分離且與所述存取元件陣列分離；形成延伸穿過所述多個導電層之電極柱陣列，所述電 極柱陣列中之所述電極柱接觸所述存取元件陣列中的對應存取元件，且界定所述柱與所述多個導電層中之導電層之間的界面區；以及在所述界面區中形成記憶體構件，所述記憶體構件中之每一者包括可程式化相變記憶體構件以及臨界值切換構件。
  13. 如申請專利範圍第12項所述之記憶體元件之製造方法，其中所述形成多個導電層的步驟包含導體材料之毯覆式沈積。
  14. 如申請專利範圍第13項所述之記憶體元件之製造方法，其中所述形成多個導電層的步驟包含：形成多個毯覆式導體材料層；以及在所述毯覆式導體材料層之間形成毯覆式絕緣材料層。
  15. 如申請專利範圍第12項所述之記憶體元件之製造方法，其中所述形成電極柱陣列的步驟包含：界定穿過所述多個導電層之電極通路；在所述電極通路之側壁上沈積臨界值切換材料層以及記憶體材料層；以及用電極材料填充所述記憶體材料層上之所述電極通路。
  16. 如申請專利範圍第12項所述之記憶體元件之製造方法，其中所述相變記憶體材料包括硫族化物。
  17. 如申請專利範圍第12項所述之記憶體元件之製 造方法，其中所述形成電極柱陣列的步驟包含：在所述多個導電層內界定電極通路；在所述電極通路之側壁上沈積臨界值切換材料層；在所述臨界值切換材料層上形成相變記憶體材料層；以及用電極材料填充所述相變材料層上之所述電極通路。
  18. 如申請專利範圍第17項所述之記憶體元件之製造方法，其中所述電極材料填充所述相變材料層上之所述電極通路的步驟包含：在所述相變材料層上形成電極材料薄膜，進行各向異性蝕刻以在所述電極通路中形成開口，所述開口暴露所述對應存取元件之觸點，以及所述電極材料填充所述通路及所述所得開口。
  19. 一種記憶體元件，包括：積體電路基板，其包含電極柱陣列以及在界面區與所述電極柱相交之多個電極平面；位於所述界面區中之相變記憶體構件，包括可程式化構件及臨界值切換構件；列解碼電路及行解碼電路，用以選擇所述電極柱陣列中之電極柱；以及平面解碼電路，用以在選定電極平面內之所述界面區中使所述臨界值切換構件偏置至導電狀態，且在未選定電極平面內之界面區中使所述臨界值切換構件偏置至非導電狀態。
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