TWI462279B - Non-volatile memory cell - Google Patents

Description

Non-volatile memory unit

The invention relates to a non-volatile memory unit with multiple time programming (MTP), in particular to a logic type multi-programmable memory unit which is completely compatible with a general complementary MOS process.

In the trend of integrating different circuit blocks into a single integrated circuit, non-volatile memory blocks are also moving toward integration into logic functional blocks. However, many non-volatile memory systems require stacked gate structures and cannot be integrated into a general logic process. For example, a typical semiconductor process requires only a single polysilicon layer and no special charge trapping structure.

The structures of various constituent memory cells are taught in U.S. Patent Nos. 7,382,658, 7,391,647, 7,263, 001, 7, 423, 903 and 7, 209, 392. U.S. Patent No. 7,382,658 teaches a P-type access transistor having a gate shared with one of the N-type MOS capacitors. U.S. Patent No. 7,391,647 teaches a P-type access transistor having a gate shared with one of the N-type MOS capacitors, and the gate of the P-type access transistor is one of a P-type MOS capacitor. The electrodes are shared. U.S. Patent No. 7,263,001 teaches a P-type access transistor whose gate is shared with one of two P-type MOS capacitors. U.S. Patent No. 7,423,903 teaches a P-type field effect transistor that performs a write operation through channel hot electron injection and an N-type. The field effect transistor is used for erasing through Fowler-Nordheim tunneling. U.S. Patent No. 7,209,392 teaches an N-type MOS field effect transistor which shares a gate with a P-type MOS field effect transistor and each transistor is connected to a respective access transistor.

Please refer to Fig. 1, which is a schematic diagram of a non-volatile memory unit in U.S. Patent No. 7,209,392. The non-volatile memory unit includes a first P-type MOS transistor T ₁ , a second P-type MOS transistor T ₂ , a first N-type MOS transistor T ₃ and a second N-type Metal oxide semiconductor transistor T ₄ . The first P-type MOS transistor T ₁ and the first N-type MOS transistor T ₃ are respectively a second P-type MOS transistor T ₂ and a second N-type MOS transistor T ₄ . The access transistor, the first P-type MOS transistor T ₁ and the first N-type MOS transistor T ₃ are controlled by a control voltage V _SG . The input end of the first P-type MOS transistor T ₁ and the first N-type MOS transistor T ₃ is a receiving select line voltage V _SL , and the input end of the second P-type MOS transistor T ₂ is receiving The first bit line voltage V _BL1 , the input end of the second N-type _MOS transistor T ₄ receives the second bit line voltage V _BL2 . The second N-type MOS transistor T ₄ shares a floating gate with the second P-type MOS transistor T ₂ .

An embodiment of the invention provides a non-volatile memory unit. The non-volatile memory unit includes a coupling device and a first selection transistor. The coupling device is formed in a first conductive region; the first selection transistor is connected in series to a first floating gate transistor and a The second selection transistor, wherein the first selection transistor, the first floating gate transistor and the second selection transistor are both formed in a second conductive region. The electrode of the coupling device and the gate of the first floating gate transistor are integrally formed floating gates; wherein the first conductive region and the second conductive region are both formed in a third conductive region; wherein the first A conductive region, the second conductive region, and the third conductive region are all doped wells.

The present invention provides a non-volatile memory unit. The non-volatile memory cell is fully compatible with typical complementary MOS processes and requires only a small layout area and exhibits good write and erase speed, durability and data retention without reducing cycle speed.

Please refer to FIG. 2 and FIG. 3, FIG. 2 is a schematic diagram showing a non-volatile memory unit 20 according to an embodiment of the present invention, and FIG. 3 is a circuit diagram for explaining the non-volatile memory unit 20 in FIG. Schematic diagram. As shown in Fig. 2, the non-volatile memory unit 20 is formed on a P-type or N-type substrate. The non-volatile memory unit 20 includes a floating gate (FG) 200, a control line (CL), a word line (WL) 290, a first source line (SL1), and a first bit line (BL1). ), a second source line (SL2), and a second bit line (BL2). Taking a P-type substrate as an example, the control line of the non-volatile memory unit 20 includes a first diffusion region 221 and a second diffusion region 222, wherein the first diffusion region 221 and the second diffusion region 222 are formed on the first conductive region. A type of first conductive region (eg, on an N-well (NW)). The third, fourth, and fifth diffusion regions 261, 271, 281 of the non-volatile memory cell 20 are formed in a second conductive region of the second conductivity type (eg, a P-well (PW) on). The sixth, seventh, and eighth diffusion regions 262, 272, 282 of the non-volatile memory cell 20 are formed in a third conductive region of the first conductivity type (e.g., another N-type well (NW)). The P-type well (PW) is placed between two N-type wells (NW). As shown in FIG. 2, the first conductive region is of a first conductivity type, and the second conductive region is disposed between the first and third conductive regions. In another embodiment of the invention, the first conductive region is of a second conductivity type and the third conductive region is disposed between the first and second conductive regions. The floating gate 200 includes a first gate portion 201 formed between the first diffusion region 221 and the second diffusion region 222, and a second gate portion 202 formed in the fourth diffusion region 271 and the fifth diffusion region. Between 281, and formed between the seventh diffusion region 272 and the eighth diffusion region 282. The first gate portion 201 and the second gate portion 202 are formed of the same polysilicon layer and are connected to each other. The gate area of the first gate portion 201 is larger than the gate area of the second gate portion 202. The word line 290 can be formed in the same polysilicon layer as the floating gate 200. The word line 290 is formed between the third diffusion region 261 and the fourth diffusion region 271, and is also formed between the sixth diffusion region 262 and the seventh diffusion region 272. The first, second, third, fourth, and fifth diffusion regions 221, 222, 261, 271, and 281 are N+ type diffusion regions, and the sixth, seventh, and eighth diffusion regions 262, 272, and 282 are P+ diffusion. Area. The non-volatile memory cell 20 is formed by a single-layer polysilicon germanium complementary MOS process.

Referring to FIGS. 2 and 3, the first gate portion 201 and the control line (CL) form a coupling device 300 formed of a MOS capacitor or a MOS field effect transistor. The second gate portion 202 and the fourth and fifth N+ type diffusion regions 271, 281 form a first N-type MOS transistor 310, and the second gate portion 202 and the seventh and eighth type diffusion regions 272, 282 forms a first P-type MOS transistor 320. Word line 290 Forming a second N-type MOS transistor 330 with the third and fourth type diffusion regions 261, 271, and a second P-type gold formed by the word line 290 and the sixth and seventh type diffusion regions 262, 272 Oxygen semiconductor transistor 340. The first source line SL1 is electrically connected to the third diffusion region 261 and is a source diffusion region of the second N-type MOS transistor 330. The first bit line BL1 is electrically connected to the fifth diffusion region 281 and is a drain diffusion region of the first N-type MOS transistor 310. The second source line SL2 is electrically connected to the sixth diffusion region 262 and is a source diffusion region of the second P-type MOS transistor 340. The second bit line BL2 is electrically connected to the eighth diffusion region 282 and is a drain diffusion region of the first P-type MOS transistor 320. The fourth diffusion region 271 serves as both the source diffusion region of the first N-type MOS transistor 310 and the drain diffusion region of the second N-type MOS transistor 330. The seventh diffusion region 272 serves as both the source diffusion region of the first P-type MOS transistor 320 and the drain diffusion region of the second P-type MOS transistor 340. The first N-type MOS transistor 310 and the first P-type MOS transistor 320 are first and second floating gate transistors, respectively, and the second N-type MOS transistor 330 and the second P-type gold The oxygen semiconductor transistors 340 are first and second selection transistors, respectively.

Please refer to FIG. 4 and FIG. 5. FIG. 4 is a schematic diagram showing a non-volatile memory unit 40 according to another embodiment of the present invention, wherein when the memory cells of the non-volatile memory unit 40 are written, non-volatile The memory unit 40 can improve the write rejection. FIG. 5 is a schematic diagram showing the circuit diagram of the non-volatile memory unit 40 in FIG. As shown in FIG. 4, the non-volatile memory unit 40 can be formed on a P-type or N-type substrate. The non-volatile memory unit 40 includes a floating gate (FG) 400, a word line (WL) 471, a selection gate (SG) 472, a control line (CL), and a source line (SL). Bit line (BL) and a erase line (EL). Taking a P-type substrate as an example, the non-volatile memory unit 40 further includes a first diffusion region 421 and a second diffusion region 422, wherein the first diffusion region 421 and the second diffusion region 422 are formed on the first conductivity type. The first conductive region (for example, an N-type well (NW)). The third, fourth, fifth, and sixth diffusion regions 461, 462, 463, 464 of the non-volatile memory unit 40 are formed in a second conductive region of the second conductivity type (eg, on a P-well (PW)) . The seventh and eighth diffusion regions 481, 482 of the non-volatile memory unit 40 are formed in a third conductive region of the first conductivity type (e.g., another N-type well (NW)). The P-type well (PW) is disposed between the two N-type wells (NW), the first conductive region belongs to the first conductivity type, and the second conductive region is disposed between the first and third conductive regions. In another embodiment, the first conductive region is of a second conductivity type and the third conductive region is disposed between the first and second conductive regions. The floating gate (FG) 400 includes a first gate portion 401 formed between the first diffusion region 421 and the second diffusion region 422, and a second gate portion 402 formed in the fourth diffusion region 462 and The five diffusion regions 463 are formed between the seventh diffusion region 481 and the eighth diffusion region 482. The first gate portion 401 and the second gate portion 402 are formed of the same polysilicon layer and are connected to each other. The gate area of the first gate portion 401 is larger than the gate area of the second gate portion 402. The word line 471, the selection gate (SG) 472, and the floating gate (FG) 400 may be formed in the same polysilicon layer. The word line (WL) 471 is formed between the third diffusion region 461 and the fourth diffusion region 462, and the selection gate (SG) 472 is formed between the fifth diffusion region 463 and the sixth diffusion region 464, first The second diffusion regions 421 and 422 are N+ type diffusion regions, and the third, fourth, fifth, and sixth diffusion regions 461, 462, 463, and 464 are N+ type diffusion regions. The seventh and eighth diffusion regions 481, 482 are P+ type diffusion regions. The non-volatile memory unit 40 is formed by a single-layer polysilicon germanium complementary MOS process.

Referring to FIG. 4 and FIG. 5, the first gate portion 401 and the control line (CL) form a coupling device 500 which is composed of a metal-oxide-semiconductor capacitor or a metal oxide half field effect. A metal-oxide-semiconductor field effect transistor is formed. The second gate portion 402 and the fourth and fifth type diffusion regions 462, 463 form a first N-type MOS transistor 510, and the second gate portion 402 and the seventh and eighth diffusion regions 481, 482 are formed. A first P-type MOS transistor 520. The word line 471 and the third and fourth type diffusion regions 461, 462 form a second N-type MOS transistor 530. Select gate (SG) 472 and fifth and sixth type diffusion regions 463, 464 form a third N-type MOS transistor 540. The source line SL is electrically connected to the third diffusion region 461 and is a source diffusion region of the second N-type MOS transistor 530. The bit line BL is electrically connected to the sixth diffusion region 464 and is a drain diffusion region of the third N-type MOS transistor 540. The erase line EL is electrically connected to the seventh and eighth diffusion regions 481, 482 of the first P-type MOS transistor 520. The fourth diffusion region 462 can serve as both the source diffusion region of the first N-type MOS transistor 510 and the drain diffusion region of the second N-type MOS transistor 530. The fifth diffusion region 463 can serve as both the drain diffusion region of the first N-type MOS transistor 510 and the source diffusion region of the third N-type MOS transistor 540. The first N-type MOS transistor 510 and the first P-type MOS transistor 520 are a first floating gate transistor and a second floating gate transistor, respectively, and a second N-type MOS transistor The 530 and the third N-type MOS transistor 540 are a first selection transistor and a second selection transistor, respectively. In another embodiment of the invention, the second floating gate transistor is formed of a MOS capacitor.

Please refer to FIG. 6. FIG. 6 is a schematic diagram showing an embodiment of writing, erasing and reading voltages of the non-volatile memory cells 20 of FIGS. 2 and 3. In the first write operation, a control line voltage lower than a write voltage (VPP) by a threshold voltage (Vth) is applied to the control line (CL), wherein the write voltage (VPP) is between 5V and 8V. The threshold voltage (Vth) is approximately 1V. Therefore, the control line voltage applied to the control line (CL) is between 4V and 7V. The word line voltage applied to the word line (WL) 290 is between 0V and 7V, the first source line (SL1), the first bit line (BL1), and the second bit line (BL2) and The P-well (PW) is grounded. However, the first bit line (BL1) can also be floating, and the write voltage (VPP) is applied to the second source line (SL2) and the N-type well. In the first write operation, the control line voltage may be coupled to the floating gate 200 through the MOS capacitor 300 in accordance with the area ratio of the MOS semiconductor capacitor 300 to the first P-type MOS transistor 320. For example, if the control line voltage is equal to 6V, the area ratio of the MOS capacitor 300 to the first P-type MOS transistor 320 is 9:1, then the potential of the floating gate 200 is 5.4V (6V X 0.9). ). In the first writing operation, the first P-type MOS transistor 320 undergoes channel hot electron injection, and the electrons from the source diffusion region of the first P-type MOS transistor 320 The floating gate 200 is injected through a cut-off channel, wherein the cut-off channel is a threshold voltage between the floating gate 200 and the source diffusion region of the first P-type MOS transistor 320, and the first P-type MOS semiconductor A write voltage (VPP) between the source diffusion region and the drain diffusion region of the crystal 320 is formed. In an erase operation (ERS), when the erase voltage (VEE) is applied to the second source line (SL2) and the N-type well (NW), the first P-type MOS transistor 320 will be Fule- Fowler-Nordheim (FN) electron tunneling phenomenon. Applied in the first The voltage of the two bit line (BL2) is 0V or the second bit line (BL2) is floating, and the word line voltage applied to the word line (WL) 290 is between 0V and 20V. The control line (CL), the first source line (SL1), the first bit line (BL1), and the P-type well (PW) are all grounded, and the first bit line (BL1) may also be floating, applied to the The erase voltage (VEE) of the two source lines (SL2) and the N type well (NW) is between 5V and 20V. As such, electrons injected into the floating gate 200 are emitted by the floating gate 200.

In the second write operation, the control line voltage is the first write voltage (VPP1) applied to the control line (CL), wherein the first write voltage (VPP1) is between 5V and 12V. The first source line (SL1), the second source line (SL2), the first bit line (BL1), and the P-type well (PW) are both grounded, but the first bit line (BL1) may also be floating. . A second write voltage (VPP2) between 5V and 8V is applied to the N-well (NW), a third write voltage (VPP3) below 0V is applied to the word line (WL), and second The bit line (BL2) is floating. In the second writing operation, the first P-type MOS transistor 320 undergoes band-to-band tunneling-induced hot electron (BBHE) implantation. In an erase operation, when the erase voltage (VEE) is applied to the second source line (SL2) and the N-type well (NW), the first P-type MOS transistor 320 occurs in the Fuller-Nordheim Fowler-Nordheim electron tunneling ejection. The voltage applied to the word line (WL) 290 is between 0V and 20V, and the control line (CL), the first source line (SL1), and the P-type well (PW) are both grounded and applied in the first place. The voltage of the line (BL1) is 0V or the first bit line (BL1) is floating, the voltage applied to the second bit line (BL2) is 0V or the second bit line (BL2) is floating. The erase voltage (VEE) applied to the second source line (SL2) and the N-type well (NW) is between 5V and 20V. Such as Thus, electrons injected into the floating gate 200 are emitted by the floating gate 200.

In the third write operation, the control line voltage applied to the control line (CL) is between 5V and 12V, and the voltage applied to the word line (WL) 290 is between 5V and 8V, the second The source line (SL2) is floating, and the voltage applied to the N-well (NW) is between 5V and 8V, the first bit line (BL1), the first source line (SL1), and the P-type well. Both (PW) and the second bit line (BL2) are grounded. However, the first bit line (BL1) can also be floating. In the third writing operation, the first P-type MOS transistor 320 undergoes band-to-band enthalpy-induced hot electron injection. In an erase operation, when the erase voltage (VEE) is applied to the second source line (SL2) and the N-type well (NW), the first P-type MOS transistor 320 occurs in the Fuller-Nordheim The electrons are tunneled out. The word line voltage applied to the word line (WL) 290 is between 0V and 20V, and the control line (CL), the first source line (SL1) and the P-type well (PW) are both grounded and applied to The voltage of the first bit line (BL1) is 0V or the first bit line (BL1) is floating, and the voltage applied to the second bit line (BL2) is 0V or the second bit line (BL2) It is floating, and the erase voltage (VEE) applied to the second source line (SL2) and the N-type well (NW) is between 5V and 20V. As such, electrons injected into the floating gate 200 are emitted by the floating gate 200.

In a read operation, a first voltage (VCC1) is applied to the control line (CL) and the word line (WL), and a second voltage (VCC2) is applied to the second source line (SL2) and N. A well (NW), a read voltage (VRR) is applied to the first bit line (BL1), the first voltage (VCC1) and the read voltage (VRR) are between 1V and 5V, and the second voltage (VCC2) is between 0V and 5V, and the voltage applied to the second bit line (BL2) is 0V or The second bit line (BL2) is floating, and the first source line (SL1) and the P-type well (PW) are both grounded. A capacitive coupling of the P-type MOS capacitor 300 causes a portion (eg, 9/10) of the first voltage (VCC1) to be coupled to the floating gate 200. When the non-volatile memory cell 20 is erased, the potential of the floating gate 200 is sufficient to turn on the first N-type MOS transistor 310. Since the read voltage (VRR) is applied to the first bit line (BL1) and the first source line (SL1) is grounded, the read current flows through the first N-type MOS transistor 310 to indicate a Positive logic state. When the non-volatile memory cell 20 is written, the electrons injected into the floating gate 200 will be sufficient to compensate or be significantly lower than the first voltage (VCC1) partially coupled to the floating gate 200, so that the first N-type MOS The transistor 310 remains off or slightly turned on, so that the read current is lower than the read current detectable by the non-volatile memory unit 20 in the erased state. As such, detecting a lower read current will indicate a negative logic state. The use of a higher read current to indicate a positive logic state and the use of a lower read current to indicate a negative logic state is merely an example and is not intended to limit the scope of this embodiment. For example, the present implementation can also use a higher read current to indicate a negative logic state and a lower read current to indicate a positive logic state.

Please refer to FIG. 7. FIG. 7 is a schematic diagram showing an embodiment of the write, erase, read voltage and write suppression operations of the nonvolatile memory unit 40 of FIGS. 4 and 5. In the write operation, the control line voltage between 5V and 20V is applied to the control line (CL) and the erase line (EL), and the first voltage (VCC1) between 1V and 5V is applied to the select gate. The pole (SG), the voltage applied to the word line (WL) is between 0V and 5V, and the source line (SL), the bit line (BL) and the P-type well (PW) are both grounded. In the write operation, the control line voltage can be based on the MOS capacitor 500 and the first N-type MOS transistor The area ratio of 510 is coupled to floating gate 400 through MOS capacitor 500. For example, if the control line voltage is equal to 6V and the area ratio of the MOS capacitor 500 to the first N-type MOS transistor 510 is 9:1, the potential of the floating gate 400 is approximately 5.4V (0.9 X). 6V). In the write operation, the first N-type MOS transistor 510 will undergo a Fuller-Nordheim electron tunneling implant. In an erase operation, when the erase voltage (VEE) is applied to the erase line (EL), and the control line (CL), the source line (SL), the bit line (BL), and the P-type well (PW) When grounded, the first P-type MOS transistor 520 will undergo a Fuller-Nordheim electron tunneling. In the erase operation, the voltage applied to the word line (WL) and the select gate (SG) is between 0V and 5V, and the erase voltage (VEE) is between 5V and 20V. The electrons injected into the floating gate 400 during writing are emitted by the floating gate 400 at the time of erasing.

In a read operation, a first voltage (VCC1) is applied to the control line (CL) and the erase line (EL), and a second voltage (VCC2) is applied to the word line (WL) and the select gate. (SG), a read voltage (VRR) is applied to the bit line (BL), the second voltage (VCC2) and the read voltage (VRR) are between 1V and 5V, and the first voltage (VCC1) is Between 0V and 5V, the source line (SL) and the P-type well (PW) are grounded, capacitively coupled through the MOS capacitor 500, and a partial potential of the first voltage (VCC1) (eg, 9/10) ) will be coupled to the floating gate 400. When the non-volatile memory cell 40 is erased, the potential of the floating gate 400 will be sufficient to turn on the first N-type MOS transistor 510. Since the read voltage (VRR) is applied to the bit line (BL) and the source line (SL) is grounded, the read current flows through the first N-type MOS transistor 510, thereby detecting a positive Logic state. When the non-volatile memory unit 40 is written, the electrons injected into the floating gate 400 will be sufficient to compensate Or significantly lower than a portion of the first voltage (VCC1) coupled to the floating gate 400 such that the first N-type MOS transistor 510 can remain off, or slightly open so that the read current is lower than the non-volatile memory unit 40 The read current that can be detected by the erase operation. As such, detecting a lower read current will indicate a negative logic state. In other embodiments of the invention, a higher read current can also be used to indicate a negative logic state, while a lower read current can also be used to indicate a positive logic state.

Please refer to FIG. 8. FIG. 8 is a waveform diagram for explaining the write suppression operation of the non-volatile memory unit 40 of FIGS. 4 and 5. The waveform diagram of Fig. 8 shows the control line voltage applied to the control line (CL), the word line voltage applied to the word line (WL), the selected gate voltage applied to the selection gate (SG), and applied to the wipe. The erase line voltage except the line (EL), the bit line voltage applied to the bit line (BL), the source line voltage applied to the source line (SL), and the P type applied to the P-type well (PW) The well voltage is a channel voltage of the first N-type MOS transistor 510, wherein the channel voltage is boosted from a third time (t3) to a fourth time (t4) of the write suppression operation. As shown in Fig. 8, the channel voltage reaches the sixth voltage (V6) from the second time (t2) to the third time (t3). From the third time (t3) to the fourth time (t4), the control line voltage is at a first voltage (V1), the selection gate voltage is at a second voltage (V2), and the erase line voltage is in a The third voltage (V3), the bit line voltage is at a fourth voltage (V4) and the channel voltage is at a fifth voltage (V5). In the write suppression operation, the first voltage V1 to the sixth voltage V6 are set to V1 V3>V5>V4 V2>V6. In the write operation, the first voltage V1 to the sixth voltage V6 are set to V1 V3 V2>V4=V5=V6 0V. For example, as shown in Figure 7, in the write suppression operation, the control line voltage is between 5V and 20V, the word line voltage is between 0V and 5V, and the gate voltage is selected. Between 1V and 5V, the erase line voltage is between 5V and 20V, the bit line voltage is between 1V and 5V, the source line voltage is between 0V and 5V, and the P-well voltage is It is 0V.

Referring to FIG. 9 and FIG. 10, FIG. 9 is a schematic diagram showing a non-volatile memory unit 90 according to another embodiment of the present invention, and FIG. 10 is a circuit diagram for explaining the non-volatile memory unit 90 in FIG. Schematic diagram. As shown in FIG. 9, the non-volatile memory unit 90 includes a floating gate (FG) 900, a word line (WL) 971, a selection gate (SG) 972, a control line (CL), and a source. Line (SL), one bit line (BL), and one erase line (EL), wherein when the memory cells of the non-volatile memory unit 90 are written, the select gate (SG) 972 can be used for writing. The ability to suppress. Taking a P-type (a first conductivity type) substrate as an example, the non-volatile memory unit 90 is formed in an N-type well 930 (a third conductive type of a second conductivity type), wherein the N-type well 930 is formed in P-type substrate. The non-volatile memory unit 90 further includes a first diffusion region 921 and a second diffusion region 922, wherein the first diffusion region 921 and the second diffusion region 922 are formed in a first conductive region (PW1) of the first conductivity type. The third, fourth, fifth, and sixth diffusion regions 961, 962, 963, and 964 of the non-volatile memory unit 90 are formed in a second conductive region (PW2) of the first conductivity type. The seventh and eighth diffusion regions 981, 982 of the non-volatile memory cell 90 are a fourth conductive region (PW3) formed of the first conductivity type. As shown in FIG. 9, the second conductive region (PW2) is interposed between the first conductive region (PW1) and the fourth conductive region (PW3). The floating gate (FG) 900 includes a first gate portion 901 formed between the first diffusion region 921 and the second diffusion region 922, and a second gate portion 902 formed in the fourth diffusion region. Between 962 and fifth diffusion region 963, and formed between the seventh diffusion region 981 and the eighth diffusion region 982. The first gate portion 901 and the second gate portion 902 are formed of the same polysilicon layer and are connected to each other. The gate area of the first gate portion 901 is larger than the gate area of the second gate portion 902. The word line (WL) 971 and the selection gate (SG) 972 may be formed in the same polysilicon layer as the floating gate (FG) 900. A word line (WL) 971 is formed between the third diffusion region 961 and the fourth diffusion region 962, and a selection gate (SG) 972 is formed between the fifth diffusion region 963 and the sixth diffusion region 964. The first and second diffusion regions 921, 922 are third conductivity types, non-volatile memory cells 90, third, fourth, fifth, and sixth diffusion regions 961, 962, 963, 964 also belong to the second conductivity type. And the seventh and eighth diffusion regions 981, 982 of the non-volatile memory unit 90 also belong to the second conductivity type. The non-volatile memory unit 90 is formed by a single-layer polysilicon germanium complementary MOS process. However, in another embodiment of the invention, the first conductivity type is an N-type and the second conductivity type is a P-type.

Referring to FIGS. 9 and 10, the first gate portion 901 and the control line (CL) form a coupling device 1000 which is formed by a MOS capacitor or a MOS field effect transistor. The second gate portion 902 can form an n-type metal-oxide-semiconductor transistor (NMOS) transistor 1010 and a second gate portion 902 with the fourth and fifth type diffusion regions 962 and 963. A second floating gate (NMOS) transistor 1020 can be formed with the seventh and eighth diffusion regions 981, 982 of the non-volatile memory cell 90. The word line (WL) 971 can form a first select (NMOS) transistor 1030 with the third and fourth type diffusion regions 961, 962. Select gate (SG) 972 can form a second select (NMOS) transistor 1040 with fifth and sixth type diffusion regions 963, 964. Source line (SL) can be connected It is connected to the third diffusion region 961 and is a source diffusion region of the first selection transistor 1030. The bit line (BL) may be electrically connected to the sixth diffusion region 964 and is a drain diffusion region of the second selection transistor 1040. The erase line EL can be electrically connected to the seventh and eighth diffusion regions 981, 982 of the second floating gate transistor 1020. The fourth diffusion region 962 can serve as both the source diffusion region of the first floating gate transistor 1010 and the drain diffusion region of the first selection transistor 1030. The fifth diffusion region 963 can serve as both the drain diffusion region of the first floating gate transistor 1010 and the source diffusion region of the second selection transistor 1040. In another embodiment of the invention, the second floating gate transistor 1020 can be formed from a MOS capacitor.

Please refer to FIG. 11. FIG. 11 is a schematic diagram showing an embodiment of writing, erasing, reading and writing suppression voltages of the non-volatile memory unit 90 of FIGS. 9 and 10. In a write operation, a control line voltage applied to the control line (CL) and the first conductive region (PW1) is between 5V and 20V. The source line (SL), the bit line (BL), and the second conductive area (PW2) are grounded. The word line voltage applied to the word line (WL) is between 0V and 5V. A erase line voltage applied to the erase line (EL) and the fourth conductive region (PW3) is between 5V and 20V. A select gate voltage applied to the select gate (SG) is between 1V and 5V. In addition, a second well voltage applied to the N-well 930 (third conductive region) is between 5V and 20V to prevent the first conductive region (PW1), the second conductive region (PW2), and the fourth conductive region. A forward bias is generated between the zone (PW3) and the N-well 930. In a write operation, the control line voltage can be coupled to the floating gate 900 through the coupling device 1000 in accordance with the area ratio of the coupling device 1000 to the first floating gate transistor 1010. For example, if the control line voltage is equal to 10V, the area ratio of the coupling device 1000 to the first floating gate transistor 1010 is 9:1, then the potential of the floating gate 900 It is 9V (10V X 0.9). In the write operation, Fowler-Nordheim tunneling injection occurs in the first floating gate transistor 1010. Therefore, electrons are injected from the first floating gate transistor 1010 to the floating gate 900.

In a erase operation, the word line voltage applied to the word line (WL) is between 0V and 5V. The control line (CL), the first conductive region (PW1), the source line (SL), the bit line (BL), and the second conductive region (PW2) are grounded. A select gate voltage applied to the select gate (SG) is between 0V and 5V. A erase line voltage applied to the erase line (EL) and the fourth conductive region (PW3) is between 5V and 20V. In addition, a second well voltage applied to the N-well 930 (third conductive region) is between 5V and 20V to prevent the first conductive region (PW1), the second conductive region (PW2), and the fourth conductive region. A forward bias is generated between the zone (PW3) and the N-well 930. In the erase operation, when the erase line voltage is applied to the erase line (EL) and the fourth conductive region (PW3), the Fuller-Nordheim electron tunneling occurs at the second floating gate transistor 1020. Shoot out. As such, the electrons stored in the floating gate 900 are emitted by the floating gate 900.

In a read operation, a control line voltage applied to the control line (CL) and the first conductive region (PW1) is between 0V and 5V. The word line voltage applied to the word line (WL) is between 1V and 5V, and a select gate voltage applied to the select gate (SG) is between 1V and 5V, and is applied in place. The one-line voltage of the line (BL) is between 1V and 5V. The source line (SL) and the second conductive area (PW2) are grounded. A erase line voltage applied to the erase line (EL) and the fourth conductive region (PW3) is between 0V and 5V. In addition, a second well voltage applied to the N-well 930 (the third conductive region) is Between 0V and 5V to prevent a forward bias between the first conductive region (PW1), the second conductive region (PW2), the fourth conductive region (PW3), and the N-well 930. A portion of the potential (eg, 9/10) of the control line voltage is coupled to the floating gate 900 by capacitive coupling of the coupling device 1000. When the non-volatile memory cell 90 is erased, the potential of the floating gate 900 will be sufficient to turn on the first floating gate transistor 1010. Since the bit line voltage is applied to the bit line (BL), and the source line (SL) and the second conductive area (PW2) are grounded, the read current flows through the first floating gate transistor 1010, whereby the read current flows through the first floating gate transistor 1010. A positive logic state is detected. When the non-volatile memory cell 90 is written, the electrons injected into the floating gate 900 will be sufficient to compensate or significantly lower the voltage of the control line coupled to the floating gate 900, so the first floating gate transistor 1010 can remain off. Or a slight turn-on causes the read current to be lower than the read current detectable by the non-volatile memory unit 90 during the erase operation. As such, detecting a lower read current will indicate a negative logic state. However, the invention is not limited to a higher read current indicating a positive logic state and a lower read current indicating a negative logic state. In other embodiments of the invention, a higher read current can also be used to indicate a negative logic state, while a lower read current can also be used to indicate a positive logic state.

Referring to Fig. 12, Fig. 12 is a waveform diagram for explaining the write suppression operation of the nonvolatile memory unit 90 of Figs. 9 and 10. The waveform diagram of Fig. 12 shows a control line voltage applied to the control line (CL) and the first conductive region (PW1), a word line voltage applied to the word line (WL), and applied to the selection gate (SG). a select gate voltage, a erase line voltage applied to the erase line (EL) and the fourth conductive region (PW3), a bit line voltage applied to the bit line (BL), applied to the source line a source line voltage of (SL), a first well voltage applied to the second conductive region (PW2), a second well voltage applied to the N-well 930, and a channel of the first floating gate transistor 1010 A (Channel) voltage in which a channel voltage is boosted from a third time (t3) to a fourth time (t4) of the write suppression operation. As shown in Fig. 12, the channel voltage reaches the sixth voltage (V6) from the second time (t2) to the third time (t3). From the third time (t3) to the fourth time (t4), the control line voltage is at a first voltage (V1), the selection gate voltage is at a second voltage (V2), and the erase line voltage is in a The third voltage (V3), the bit line voltage is at a fourth voltage (V4) and the channel voltage is at a fifth voltage (V5). In the write suppression operation, the first voltage V1 to the sixth voltage V6 are set to V1 V3>V5>V4 V2>V6. In the write operation, the first voltage V1 to the sixth voltage V6 are set to V1 V3 V2>V4=V5=V6 0V. For example, as shown in Figure 11, in the write suppression operation, the control line voltage is between 5V and 20V, the word line voltage is between 0V and 5V, and the gate voltage is selected. Between 1V and 5V, the erase line voltage is between 5V and 20V, the bit line voltage is between 1V and 5V, the source line voltage is between 0V and 5V, and the second well voltage is Between 5V and 20V and the first well voltage is 0V.

Please refer to Figure 13 and Figure 14. Fig. 13 is a view showing a non-volatile memory unit 130 according to another embodiment of the present invention, and Fig. 14 is a view showing a circuit diagram of the non-volatile memory unit 130 in Fig. 13. As shown in FIG. 13, the non-volatile memory unit 130 includes a floating gate (FG) 1300, a word line (WL) 1371, a select gate (SG) 1372, a control line (CL), and a source. A line (SL) and a bit line (BL), wherein when the memory cells of the non-volatile memory unit 130 are written, the selection gate (SG) 1372 is used to achieve write rejection. Take a P type (a first conductivity type) The substrate is exemplified, that is, the non-volatile memory unit 130 is formed in an N-type well 1330 (a third conductive region of a second conductivity type), wherein the N-type well 1330 is formed on the P-type substrate. The non-volatile memory unit 130 further includes first, second, third, fourth, fifth, and sixth diffusion regions 1321, 1322, 1361, 1362, 1363, and 1364. The floating gate (FG) 1300 includes a first gate portion 1301 formed between the first diffusion region 1321 and the second diffusion region 1322, and a second gate portion 1302 formed in the fourth diffusion region 1362 and the fifth Between the diffusion regions 1363. As shown in FIG. 13, the non-volatile memory unit 130 differs from the non-volatile memory unit 90 in that the non-volatile memory unit 130 does not include the second floating gate transistor 1020 and the fourth conductive region (PW3). In addition, the remaining architecture of the non-volatile memory unit 130 is the same as that of the non-volatile memory unit 90, and details are not described herein again.

Referring to FIGS. 13 and 14, the first gate portion 1301 and the control line (CL) form a coupling device 1400. The second gate portion 1302 can form a first floating gate transistor 1410 with the fourth and fifth type diffusion regions 1362, 1363. The word line (WL) 1371 can form a first selection transistor 1430 with the third and fourth type diffusion regions 1361, 1362. Select gate (SG) 1372 can form a second select transistor 1440 with fifth and sixth type diffusion regions 1363, 1364. The source line (SL) is electrically connectable to the third diffusion region 1361 and is a source diffusion region of the first selection transistor 1430. The bit line (BL) may be electrically connected to the sixth diffusion region 1364 and is a drain diffusion region of the second selection transistor 1440. The fourth diffusion region 1362 can serve as both the source diffusion region of the first floating gate transistor 1410 and the drain diffusion region of the first selection transistor 1430. The fifth diffusion region 1363 can serve as both the drain diffusion region of the first floating gate transistor 1410 and the source diffusion region of the second selection transistor 1440.

Please refer to FIG. 15. FIG. 15 is a schematic diagram showing an embodiment of the writing, erasing, reading and writing suppressing operations of the non-volatile memory unit 130 of FIGS. 13 and 14. In a write operation, a control line voltage applied to the control line (CL) and the first conductive region (PW1) is between 5V and 20V. The source line (SL), the bit line (BL), and the second conductive area (PW2) are grounded. The word line voltage applied to the word line (WL) is between 0V and 5V. A select gate voltage applied to the select gate (SG) is between 1V and 5V. In addition, a second well voltage applied to the N-type well 1330 (third conductive region) is between 5V and 20V to prevent the first conductive region (PW1), the second conductive region (PW2), and the N-well. A forward bias is generated between 1330. In a write operation, the control line voltage can be coupled to the floating gate 1300 through the coupling device 1400 according to the area ratio of the coupling device 1400 to the first floating gate transistor 1410. For example, if the control line voltage is equal to 10V and the area ratio of the coupling device 1400 to the first floating gate transistor 1410 is 9:1, the potential of the floating gate 1300 is 9V (10V X 0.9). In the write operation, the first floating gate transistor 1410 undergoes a Fuller-Nordheim tunneling implant.

In a erase operation, a word line voltage applied to the word line (WL), a selected gate voltage applied to the selection gate (SG), and a source line voltage applied to the source line (SL) The one-bit line voltage applied to the bit line (BL) and a first well voltage applied to the second conductive region (PW2) are between 5V and 20V. The control line (CL) and the first conductive area (PW1) are grounded. In addition, a second well voltage applied to the N-type well 1330 (third conductive region) is between 5V and 20V to prevent the first conductive region (PW1), the second conductive region (PW2), and the N-well. A forward bias is generated between 1330. In the erase operation, when controlling When the line (CL) and the first conductive region (PW1) are grounded, a Fuller-Nordheim electron tunneling occurs at the first floating gate transistor 1410. As such, electrons stored in the floating gate 1300 are emitted by the floating gate 1300.

In a read operation, a control line voltage applied to the control line (CL) and the first conductive region (PW1) is between 0V and 5V, and a word line voltage applied to the word line (WL) Is between 1V and 5V, a select gate voltage applied to the select gate (SG) is between 1V and 5V and a bit line voltage applied to the bit line (BL) is between 1V Between 5V and 5V. The source line (SL) and the second conductive area (PW2) are grounded. In addition, a second well voltage applied to the N-type well 1330 (third conductive region) is between 0 V and 5 V to prevent the first conductive region (PW1), the second conductive region (PW2), and the N-type well. A forward bias is generated between 1330. A portion of the potential (eg, 9/10) of the control line voltage is coupled to the floating gate 1300 by capacitive coupling of the coupling device 1400. When the non-volatile memory cell 130 is erased, the potential of the floating gate 1300 will be sufficient to turn on the first floating gate transistor 1410. Since the bit line voltage is applied to the bit line (BL), and the source line (SL) and the second conductive area (PW2) are grounded, the read current flows through the first floating gate transistor 1410. A positive logic state is detected. When the non-volatile memory cell 130 is written, the electrons injected into the floating gate 1300 will be sufficient to compensate or significantly lower the voltage of the control line coupled to the floating gate 1300, so the first floating gate transistor 1410 can remain off. Or a slight turn-on causes the read current to be lower than the read current detectable by the non-volatile memory unit 130 during the erase operation. As such, detecting a lower read current will indicate a negative logic state.

Referring to Fig. 16, Fig. 16 is a waveform diagram for explaining the write suppression operation of the nonvolatile memory unit 130 of Figs. 13 and 14. The waveform diagram of Fig. 16 shows a control line voltage applied to the control line (CL) and the first conductive region (PW1), a word line voltage applied to the word line (WL), and applied to the selection gate (SG). a select gate voltage, a bit line voltage applied to the bit line (BL), a source line voltage applied to the source line (SL), and a first applied to the second conductive region (PW2) a well voltage, a second well voltage applied to the N-well 1330, and a channel voltage of the first floating gate transistor 1410, wherein the channel voltage is at a third time of the write suppression operation ( The t3) to fourth time (t4) is raised. As shown in Fig. 15, the channel voltage reaches the sixth voltage (V6) from the second time (t2) to the third time (t3). From the third time (t3) to the fourth time (t4), the control line voltage is at a first voltage (V1), the selection gate voltage is at a second voltage (V2), and the bit line voltage is in a The fourth voltage (V4) and the channel voltage are at a fifth voltage (V5). In the write suppression operation, the first voltage V1 to the sixth voltage V6 are set to V1>V5>V4 V2>V6. In the write operation, the first voltage V1 to the sixth voltage V6 are set to V1 V2>V4=V5=V6 0V. For example, as shown in Figure 15, in the write suppression operation, the control line voltage is between 5V and 20V, the word line voltage is between 0V and 5V, and the select gate voltage is between Between 1V and 5V, the bit line voltage is between 1V and 5V, the source line voltage is between 0V and 5V, the second well voltage is between 5V and 20V, and the first well voltage is It is 0V.

In summary, the above non-volatile memory cells 20, 40, 90 and 130 are completely compatible with the general complementary MOS process, and only require a small layout area, and can not fall. Good write and erase speed, durability and data retention at low cycle times.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

20, 40, 90, 130‧‧‧ non-volatile memory cells

200, FG, 400, 900, 1300‧‧‧ floating gate

201, 401, 901, 1301‧‧‧ first gate

202, 402, 902, 1302‧‧‧ second gate

221, 421, 921, 1321‧‧‧ first diffusion zone

222, 422, 922, 1322‧‧‧ second diffusion zone

261, 461, 961, 1361‧‧‧ third diffusion zone

262, 464, 964, 1364‧‧‧ sixth diffusion zone

271, 462, 962, 1362‧‧‧ fourth diffusion zone

272, 481, 981‧‧‧ seventh diffusion zone

281, 463, 963, 1363 ‧ ‧ fifth diffusion zone

282, 482, 982‧‧‧ eighth diffusion zone

290, WL, 471, 971, 1371‧‧ ‧ character lines

300, 500, 1000, 1400‧‧‧ coupling devices

310, 510‧‧‧First N-type MOS transistor

320, 520‧‧‧ First P-type MOS transistor

330, 530‧‧‧Second N-type MOS transistor

340‧‧‧Second P-type MOS transistor

472, SG, 972, 1372‧‧‧ select gate

540‧‧‧ Third N-type MOS transistor

1010, 1410‧‧‧ first floating gate transistor

1020‧‧‧Second floating gate transistor

1030, 1430‧‧‧ first choice of crystal

1040, 1440‧‧‧ second choice transistor

BL‧‧‧ bit line

BL1‧‧‧ first bit line

BL2‧‧‧ second bit line

CL‧‧‧ control line

Channel‧‧‧ channel

EL‧‧‧ erasing line

NW, 930, 1330‧‧‧N well

PW‧‧‧P type well

PW1‧‧‧First Conductive Zone

PW2‧‧‧Second conductive area

PW3‧‧‧4th conductive zone

SL1‧‧‧first source line

SL2‧‧‧Second source line

SL‧‧‧ source line

T ₁ ‧‧‧First P-type MOS transistor

T ₂ ‧‧‧Second P-type MOS transistor

T ₃ ‧‧‧First N-type MOS transistor

T ₄ ‧‧‧Second N-type MOS transistor

First time t1‧‧‧

T2‧‧‧ second time

T3‧‧‧ third time

T4‧‧‧ fourth time

T5‧‧‧ fifth time

T6‧‧‧ sixth time

V _SG ‧‧‧Control voltage

V _SL ‧‧‧Select line voltage

V _BL1 ‧‧‧first bit line voltage

V _BL2 ‧‧‧second bit line voltage

V1‧‧‧ first voltage

V2‧‧‧second voltage

V3‧‧‧ third voltage

V4‧‧‧fourth voltage

V5‧‧‧ fifth voltage

V6‧‧‧ sixth voltage

Figure 1 is a schematic illustration of a non-volatile memory unit in U.S. Patent No. 7,209,392.

Fig. 2 is a schematic view showing a non-volatile memory unit according to an embodiment of the present invention.

Fig. 3 is a schematic view showing a circuit diagram of the nonvolatile memory unit in Fig. 2.

Figure 4 is a schematic diagram showing a non-volatile memory unit according to another embodiment of the present invention.

Fig. 5 is a schematic view showing a circuit diagram of the non-volatile memory unit in Fig. 4.

Fig. 6 is a view showing an embodiment of writing, erasing and reading voltages of the nonvolatile memory cells of Figs. 2 and 3;

Fig. 7 is a view showing an embodiment of writing, erasing, reading voltage and write suppressing operations of the nonvolatile memory cells of Figs. 4 and 5.

Fig. 8 is a waveform diagram for explaining a write suppression operation of the nonvolatile memory unit of Figs. 4 and 5.

Figure 9 is a schematic diagram showing a non-volatile memory unit according to another embodiment of the present invention.

Figure 10 is a schematic diagram showing the circuit diagram of the non-volatile memory unit in Figure 9.

Fig. 11 is a view showing an embodiment of the writing, erasing, reading and writing suppressing operations of the nonvolatile memory unit of Figs. 9 and 10.

Figure 12 is a diagram showing the write suppression operation of the non-volatile memory unit of Figs. 9 and 10. A schematic diagram of the waveform.

Figure 13 is a schematic diagram showing a non-volatile memory unit according to another embodiment of the present invention.

Fig. 14 is a schematic view showing a circuit diagram of the non-volatile memory unit in Fig. 13.

Fig. 15 is a view showing an embodiment of the writing, erasing, reading and writing suppressing operations of the nonvolatile memory unit of Figs. 13 and 14.

Fig. 16 is a waveform diagram for explaining the write suppression operation of the nonvolatile memory unit of Figs. 13 and 14.

90‧‧‧Non-volatile memory unit

900, FG‧‧‧ floating gate

901‧‧‧First Gate

902‧‧‧Second Gate

921‧‧‧First Diffusion Zone

922‧‧‧Second diffusion zone

930‧‧‧N type well

961‧‧ Third diffusion zone

962‧‧‧4th Diffusion Zone

963‧‧‧ fifth diffusion zone

964‧‧‧ sixth diffusion zone

971, WL‧‧‧ character line

972, SG‧‧‧Selected gate

981‧‧‧ seventh diffusion zone

982‧‧‧ eighth diffusion zone

BL‧‧‧ bit line

CL‧‧‧ control line

EL‧‧‧ erasing line

PW1‧‧‧First Conductive Zone

PW2‧‧‧Second conductive area

PW3‧‧‧4th conductive area

SL‧‧‧ source line

Claims (22)

A non-volatile memory unit includes: a coupling device formed in a first conductive region; and a first selection transistor connected in series to a first floating gate transistor and a second selection transistor, wherein the first The selection transistor, the first floating gate transistor and the second selection transistor are both formed in a second conductive region; wherein the electrode of the coupling device and the gate of the first floating gate transistor are integrally formed The floating gate; wherein the first conductive region and the second conductive region are all formed in a third conductive region; wherein the first conductive region, the second conductive region and the third conductive region are all doped wells. The non-volatile memory unit of claim 1, wherein the first conductive region and the second conductive region belong to a first conductivity type, and the third conductive region belongs to a second conductivity type. The non-volatile memory unit of claim 1, wherein the floating gate comprises: a first gate portion for forming the coupling device; and a second gate portion for forming the first floating gate a transistor; wherein a gate area of the first gate portion is greater than a gate area of the second gate portion. The non-volatile memory unit of claim 1, wherein the coupling device is formed by a MOS capacitor or a MOS field effect transistor. The non-volatile memory unit of claim 1, wherein the first floating gate transistor is between the first selection transistor and the second selection transistor. The non-volatile memory unit of claim 1, further comprising: a control line electrically connected to the coupling device; a word line electrically connected to the gate of the first selection transistor; and a selection gate, electricity a gate connected to the second selection transistor; a bit line electrically connected to the drain region of the second selection transistor; and a source line electrically connected to the source region of the first selection transistor . The non-volatile memory unit of claim 6, wherein a control line voltage applied to the control line, a word line voltage applied to the word line, and a selection gate are applied in a read operation a select gate voltage, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductive region, and a voltage applied thereto A second well voltage of the third conductive region is configured to detect a current flowing through the first selection transistor, the first floating gate transistor, and the second selection transistor connected in series. The non-volatile memory unit of claim 6, wherein a control line voltage applied to the control line, a word line voltage applied to the word line, and a selection gate are applied in a write operation a select gate voltage, a bit line voltage applied to the bit line, a source line voltage applied to the source line, applied to the gate A first well voltage of the second conductive region and a second well voltage applied to the third conductive region are configured to induce a Fourer-Nordham tunneling injection at the first floating gate transistor (Fowler -Nordheim tunneling injection). The non-volatile memory unit according to claim 6, wherein a control line voltage applied to the control line, a word line voltage applied to the word line, and a selection gate are applied in a write suppression operation. a gate select voltage, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductive region, and a voltage applied to A second well voltage of the third conductive region is configured to initiate channel boosting at the first floating gate transistor. The non-volatile memory unit of claim 6, wherein in an erasing operation, a control line voltage applied to the control line, a word line voltage applied to the word line, and a gate applied to the select gate Selecting a gate voltage, a bit line voltage applied to the bit line, a source line voltage applied to the source line, a first well voltage applied to the second conductive region, and applying to the first A second well voltage of the three conductive regions is configured to initiate a Fowler-Nordheim tunneling ejection at the first floating gate transistor. The non-volatile memory unit of claim 1, further comprising: a second floating gate transistor formed in a fourth conductive region, wherein the fourth conductive region is formed in the third conductive region, and the first Two floating gate transistors The gate, the electrode of the coupling device, and the gate of the first floating gate transistor are the integrally formed floating gates. The non-volatile memory unit of claim 11, wherein the first conductive region, the second conductive region, and the fourth conductive region belong to a first conductivity type, and the third conductive region belongs to a second conductive region. Types of. The non-volatile memory unit of claim 11, wherein the floating gate comprises: a first gate portion for forming the coupling device; and a second gate portion for forming the first floating gate a transistor and the second floating gate transistor; wherein a gate area of the first gate portion is greater than a gate area of the second gate portion. The non-volatile memory unit of claim 11, wherein the second floating gate transistor is formed by a MOS field effect transistor or a MOS capacitor. The non-volatile memory unit of claim 11, wherein the second conductive region is between the first conductive region and the fourth conductive region. The non-volatile memory unit of claim 11, wherein the fourth conductive region is between the first conductive region and the second conductive region. The non-volatile memory unit of claim 11, wherein the first floating gate transistor is between the first selection transistor and the second selection transistor. The non-volatile memory unit of claim 17, further comprising: a control line electrically connected to the coupling device; a word line electrically connected to the gate of the first selection transistor; and a selection gate, electricity a gate connected to the second selection transistor; a erase line electrically connected to the diffusion region of the second floating gate transistor and the fourth conductive region; and a bit line electrically connected to the second selection a drain region of the crystal; and a source line electrically connected to the source region of the first selection transistor. The non-volatile memory unit of claim 18, wherein in a read operation, a control line voltage applied to the control line, a word line voltage applied to the word line, applied to the select gate a select gate voltage, a wipe line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, applied to the second a first well voltage of the conductive region and a second well voltage applied to the third conductive region are configured to detect the first selected transistor flowing through the series connection, the first floating gate transistor And the current of the second selected transistor. The non-volatile memory unit of claim 18, wherein in a write operation, a control line voltage applied to the control line, a word line line applied to the word line Pressing, a select gate voltage applied to the select gate, a erase line voltage applied to the erase line, a bit line voltage applied to the bit line, and a source applied to the source line a line voltage, a first well voltage applied to the second conductive region, and a second well voltage applied to the third conductive region are configured to initiate a Fourier-Novo at the first floating gate transistor Dehan tunneled into the tunnel. The non-volatile memory unit of claim 18, wherein in a write suppression operation, a control line voltage applied to the control line, a word line voltage applied to the word line, is applied to the select gate a gate selection voltage, a erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, and applied to the first A first well voltage of the second conductive region and a second well voltage applied to the third conductive region are configured to initiate channel boosting at the first floating gate transistor. The non-volatile memory unit of claim 18, wherein in an erasing operation, a control line voltage applied to the control line, a word line voltage applied to the word line, and a gate applied to the select gate Selecting a gate voltage, a erase line voltage applied to the erase line, a bit line voltage applied to the bit line, a source line voltage applied to the source line, and applying to the second conductive A first well voltage of the zone and a second well voltage applied to the third conductive zone are configured to initiate a Fourer-Nordham tunneling exit at the second floating gate transistor.