TWI460766B - Method to compensate optical proximity correction - Google Patents

Description

Optical proximity correction compensation method

The present invention relates to an optical proximity correction (OPC), and more particularly to a method of compensating for optical proximity correction.

The integrated circuit design pattern often includes an active region, a shallow trench isolation region outside the active region, and an ion implantation region overlapping with a portion of the shallow trench isolation region and a portion of the active region. Before performing the ion implantation process on the ion implantation region, a photolithography process is first performed to form a photoresist pattern on the substrate that exposes the ion implantation region. However, during exposure, various patterns on the substrate may cause light to be affected, resulting in a critical dimension variation (CD variation) of the developed photoresist pattern, that is, the true critical dimension of the developed photoresist pattern does not match. demand. In order to expose the correct photoresist pattern, the photomask must be optically adjacently corrected.

According to the above, an anti-reflection coating is formed on the substrate before the photoresist pattern is formed to avoid the critical dimension variation of the photoresist pattern due to light reflection during exposure. However, since the ion implantation region requires an ion implantation process, the anti-reflection coating does not cover the ion implantation region. When exposed, light is easily reflected by the silicon and oxide film of the ion implantation region, and shallow trench isolation topography influence (STI topography influence) leads to the traditional Optical proximity correction does not correct the mask correctly. As such, a situation in which critical dimension variation will occur. The critical dimension variation may cause the edge of the ion implantation region to be covered by photoresist or photoresist peeling, where the photoresist collapses, that is, the line width of the photoresist is too thin to break.

The present invention provides a compensation method for optical proximity correction so that the photoresist pattern meets the requirements.

In order to achieve the above advantages, the present invention proposes a compensation method for optical proximity correction, which is suitable for a lithography process. The optical proximity correction compensation method comprises the steps of: providing an integrated circuit design pattern comprising a plurality of active regions and a shallow trench isolation region, and the shallow trench isolation region is an region outside the active region. The integrated circuit design pattern further includes a plurality of ion implantation regions overlapping a portion of the shallow trench isolation region and at least a portion of the active region. Then, at least one photoresist line width compensation area is found from a photoresist coverage area other than the ion implantation area according to the integrated circuit design pattern, and the photoresist line width compensation area is located in the shallow trench isolation area. Then, according to the width of the photoresist line width compensation region, the length of the side of the active region facing the side of the photoresist line width compensation region, and the distance from the side of the photoresist line width compensation region to the active region facing To correct the integrated circuit design graphics. Then, the corrected integrated circuit design pattern is transferred to the reticle.

In an embodiment of the invention, the width of the photoresist line width compensation region is less than 500 nm.

In an embodiment of the invention, the width of the ion implantation region adjacent to the photoresist line width compensation region is greater than 700 nm.

In an embodiment of the invention, the step of modifying the integrated circuit design pattern includes: selecting a suitable one of the plurality of lookup tables according to the length of the side of the active area facing the side of the photoresist line width compensation area. Query the table. Then, the selected look-up table is queried according to the width of the photoresist line width compensation area and the distance from the side of the photoresist line width compensation area to the active area facing to obtain the correction value of the photoresist line width compensation area. After that, the integrated circuit design pattern is corrected based on the correction value.

In an embodiment of the present invention, the lookup table includes a first lookup table, a second lookup table, and a third lookup table. When the length of the side of the active area facing the side of the photoresist line width compensation area is less than 300 nm, the first lookup table is selected. When the length of the side of the active area facing the side of the photoresist line width compensation zone is between 300 nm and 600 nm, the second lookup table is selected. When the length of the side of the active area facing the side of the photoresist line width compensation area is greater than 600 nm, the third lookup table is selected.

The optical proximity correction compensation method of the present invention compensates for the line width of the photoresist pattern formed in the shallow trench isolation region, so that the problem of variation of the photoresist pattern due to the influence of the surface topography of the shallow trench isolation can be alleviated.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a layout pattern for testing used in an embodiment of the present invention. Referring to FIG. 1, the layout pattern 100 for testing is used to analyze the influence of the surface topography of the shallow trench isolation on the critical dimension of the photoresist pattern. The layout pattern 100 for this test includes a second active region 110, a diion implant region 120, and a region 130 (hereinafter referred to simply as a photoresist cover region 130) that forms a photoresist pattern of the implant layer upon implantation. The shallow trench isolation region is not the region of the active region 110, so the region that is exposed and implanted at the time of implantation is the active region 110 and a portion of the shallow trench isolation region.

According to the data analysis of the test, the critical dimension of the photoresist coverage region 130 formed in the shallow trench isolation region is affected by the width D1 of the ion implantation region 120, the spacing D2 between the two ion implantation regions 120, and the photoresist coverage region 130 to The influence of the spacing D3 of the active region 110 and the length D4 of the active region 110.

Figure 2 is a graph obtained by experimenting with a plurality of test layout patterns of different sizes. 2 is the pitch D3 of the photoresist covering region 130 to the active region 110, and the vertical axis is the true line width after development of the photoresist pattern (corresponding to D2 in the layout diagram for testing in FIG. 1), and when exposed The wavelength of the light source used is 193 nm (nm); different wavelengths can be obtained using different wavelengths of light source. In addition, the layout width D1 of the ion implantation region 120 of the plurality of different-sized test layout patterns 100 used is 600 nm, and the layout pitch D2 between the two ion implantation regions 120 is 170 nm. The curves L1, L2, L3, and L4 are experimental data obtained when the layout length D4 of the active region 110 is 200 nm, 400 nm, 600 nm, and 800 nm, respectively. Since the layout pitch D2 between the two ion implantation regions 120 is 170 nm in the test pattern 100, the ideal line width of the developed photoresist pattern should be 170 nm, but actually the line width of the photoresist pattern after development is required. Does not match. In particular, when the layout length D4 of the active region 110 is 800 nm and the layout pitch D3 of the photoresist covering region 130 to the active region 110 is 300 nm, the critical dimension variation of the photoresist pattern is the largest.

Since the optical proximity correction is used in the above experiments, there is still a problem that the true critical dimension and the layout size of the photoresist pattern vary. In view of this, an embodiment of the present invention provides a compensation method for optical proximity correction.

3 is a flow chart of a method for compensating optical proximity correction according to an embodiment of the present invention, and FIG. 4 is a schematic diagram of a design pattern of an integrated circuit. Referring to FIG. 3 and FIG. 4, the optical proximity correction compensation method of this embodiment is applicable to the lithography process. The compensation method of the optical proximity correction includes the following steps: First, as shown in step S110, the integrated circuit design pattern 200 is provided. The integrated circuit design pattern 200 includes a plurality of active regions 210 and a shallow trench isolation region 230, and the shallow trench isolation regions 230 are regions other than the active region 210. In addition, the integrated circuit design pattern 200 further includes a plurality of ion implantation regions 220. These ion implantation regions 220 overlap a portion of the shallow trench isolation regions 230 and at least a portion of the active regions 210. In the substrate, the active region 210 is located in the same layer as the shallow trench isolation region 230, and the region of the layer that is not the active region 210 is the shallow trench isolation region 230. The ion implantation region 220 is defined by the photoresist of the implant layer overlying the substrate; the region not covered by the photoresist of the implanted layer is the region of the ion implantation region 220.

Next, as shown in step S120, at least one photoresist line width compensation region 240 is found from the photoresist coverage region outside the ion implantation region 220 according to the integrated circuit design pattern 200 (FIG. 4 includes three photoresist line width compensations). District 240). The method of finding the photoresist line width compensation region 240 includes finding the photoresist coverage region in the shallow trench isolation region 230 as the photoresist line width compensation region 240. In an embodiment, the method for finding the photoresist line width compensation region 240 may further include finding a partial region of the photoresist coverage region having a width of less than 500 nm as the photoresist line width compensation region 240, so the photoresist line width compensation region 240 The width D5 is, for example, less than 500 nm. That is, when the spacing between the two ion implantation regions 220 is less than 500 nm, the photoresist line width needs to be compensated. In addition, the method of finding the photoresist line width compensation region 240 may further include finding a portion of the photoresist coverage region beside the ion implantation region 220 having a width greater than 700 nm, so the ion implantation region beside the photoresist line width compensation region 240 The width of 220 is, for example, greater than 700 nm. That is, when the width of an ion implantation region 220 is greater than 700 nm, the photoresist line width formed adjacent to the ion implantation region 220 needs to be compensated.

For convenience of explanation, the following steps will be described by taking a photoresist line width compensation area 240 as an example.

Then, as shown in step S130, after finding the photoresist line width compensation area, according to the width D5 of the photoresist line width compensation area 240, the side of the active area 210 facing the side 242 of the photoresist line width compensation area 240 The integrated circuit design pattern 200 is modified by the length of the side 212 and the distance D6 of the side edge 242 of the photoresist line width compensation area 240 to the facing active area 210.

In more detail, the step of correcting the integrated circuit design pattern 200 is, for example, first selecting a suitable one of the plurality of lookup tables according to the length of the side 212 of the active area 210 facing the side 242 of the photoresist line width compensation area 240. Query table. For example, the lookup table described above includes, for example, a first lookup table, a second lookup table, and a third lookup table. When the length of the side 212 of the active region 210 facing the side 242 of the photoresist line width compensation region 240 (as indicated by the reticle M1 in FIG. 4) is less than 300 nm (including the length equal to zero), the first lookup table is selected, wherein The case where the length of the side 212 of the active area 210 is equal to zero indicates that the side 242 of the photoresist line width compensation area 240 does not face the active area 210, and the side 242 indicated by the marking line M1 in FIG. 4 does not face the active area 210. . In addition, when the side edge 242 of the photoresist line width compensation area 240 (at the line M2 in FIG. 4) faces the side 212 of the active area 210 (such as the side 212 indicated by the symbol E1), the length is between When 300nm to 600nm, the second lookup table is selected. In addition, when the side 242 of the photoresist line width compensation area 240 (at the reticle M3 in FIG. 4) faces the side 212 of the active area 210 (such as the side 212 indicated by the symbol E2), the length is greater than 600 nm. When using the third lookup table.

The method for establishing the above-mentioned lookup table is, for example, first establishing a plurality of test reticle according to a plurality of test layout patterns of different sizes. Then, a photoresist pattern is formed on the wafer by each test reticle, and the true line width of the photoresist pattern is measured to compare the difference between the ideal line width of the photoresist pattern and the true line width. Next, a lookup table is built based on the experimental data. The look-up table includes the photoresist line width compensation area when the width D5 of the different photoresist line width compensation area 240 and the side 242 of the different photoresist line width compensation area 240 are to the distance D6 of the active area 210 facing. 240 correction value.

Then, the selected lookup table is queried according to the width D5 of the photoresist line width compensation area 240 and the side 242 of the photoresist line width compensation area 240 to the distance D6 of the active area 210 to obtain the photoresist line width compensation area. 240 correction value. Thereafter, the integrated circuit design pattern 200 is corrected based on the correction value.

Then, as described in step S140, the corrected integrated circuit design pattern is transferred to the reticle.

Since the compensation method of the optical proximity correction of the embodiment is particularly compensated for the line width of the photoresist pattern formed in the shallow trench isolation structure, the problem of variation of the photoresist pattern due to the influence of the surface topography of the shallow trench isolation can be alleviated. In this way, it is possible to avoid the situation where the edge of the ion implantation region 220 is covered by the photoresist or the photoresist is collapsed after development, so that the actually fabricated integrated circuit can conform to the design.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Test pattern

110, 210. . . Active zone

120, 220. . . Ion implantation zone

130. . . Photoresist coverage area

230. . . Shallow trench isolation zone

200. . . Integrated circuit design graphic

212, 242. . . Side

240. . . Photoresist line width compensation area

D1, D5. . . width

D2, D3. . . spacing

D4. . . length

D6. . . distance

E1, E2. . . Label

L1, L2, L3, L4. . . curve

M1, M2, M3. . . Marking

S110, S120, S130, S140. . . step

1 is a layout pattern for testing used in an embodiment of the present invention.

Figure 2 is a graph obtained by experimenting with a layout pattern for a plurality of different sizes of tests.

3 is a flow chart of a method for compensating optical proximity correction according to an embodiment of the invention.

4 is a schematic diagram of an integrated circuit design pattern.

S110, S120, S130, S140. . . step

Claims (5)

An optical proximity correction compensation method is applicable to a lithography process, and the optical proximity correction compensation method comprises: providing an integrated circuit design graphic, the integrated circuit design graphic comprising a plurality of active regions and a shallow trench isolation region, The shallow trench isolation region is a region other than the active regions, and the integrated circuit design pattern further includes a plurality of ion implantation regions overlapping a portion of the shallow trench isolation region and at least a portion of the active regions; according to the integrated circuit The design pattern finds at least one photoresist line width compensation area from a photoresist coverage area outside the ion implantation area, and the photoresist line width compensation area is located in the shallow trench isolation area; according to the photoresist line width Correcting the width of the compensation zone, the length of the side of the active zone facing the side of the photoresist line width compensation zone, and the distance from the side of the photoresist line width compensation zone to the active zone facing the correction zone The integrated circuit design graphic; and transferring the modified integrated circuit design graphic to a photomask. The method of compensating for optical proximity correction according to claim 1, wherein the width of the photoresist line width compensation region is less than 500 nm. The method of compensating for optical proximity correction according to claim 1, wherein the width of the ion implantation region beside the photoresist line width compensation region is greater than 700 nm. The method for compensating for optical proximity correction according to claim 1, wherein the step of modifying the integrated circuit design pattern comprises: according to a side of the active region facing the side of the photoresist line width compensation region Selecting a suitable lookup table from a plurality of lookup tables; querying the selected one according to the width of the photoresist line width compensation area and the distance from the side of the photoresist line width compensation area to the active area facing the Querying the table to obtain a correction value of the photoresist line width compensation area; and correcting the integrated circuit design pattern according to the correction value. The method for compensating for optical proximity correction according to claim 4, wherein the lookup tables include a first lookup table, a second lookup table, and a third lookup table, when the photoresist line width compensation area is When the length of the side of the active area facing the side is less than 300 nm, the first lookup table is selected, and the length of the side of the active area facing the side of the photoresist line width compensation area is between When the range is from 300 nm to 600 nm, the second lookup table is selected. When the side of the active area facing the side of the photoresist line width compensation area is longer than 600 nm, the third lookup table is selected. .