Claims (20)
一種電子裝置，包括：一處理器，包括：一第一多工輸入輸出腳位；一第二多工輸入輸出腳位；一外接裝置連結埠，用以連結一外接裝置，該外接裝置連結埠與該第一多工輸入輸出腳位連結，且具有一待測電位；一第一阻抗元件，具有一第一端連結該外接裝置連結埠、且具有一第二端連接至一高準位電位；以及一第二阻抗元件，具有一第一端連結該外接裝置連結埠、且具有一第二端連接至該第二多工輸入輸出腳位；其中，該處理器係組態為：若該待測電位位於該處理器內一功能方塊的一非線性操作區，自該第二多工輸入輸出腳位輸出該高準位電位或一低準位電位其中之一，以確保該待測電位操作在該功能方塊的一線性操作區內，其中，該功能方塊多工耦接該第一多工輸入輸出腳位。
An electronic device comprising: a processor comprising: a first multiplexed input and output pin; a second multiplexed input and output pin; and an external device connector for connecting an external device, the external device connecting Connected to the first multiplexed input and output pin and having a potential to be tested; a first impedance element having a first end connected to the external device connection 埠 and having a second end connected to a high level potential And a second impedance component having a first end coupled to the external device connector and having a second terminal coupled to the second multiplex pin; wherein the processor is configured to: The potential to be measured is located in a non-linear operation area of a functional block in the processor, and one of the high-level potential or a low-level potential is output from the second multiplexed input/output pin to ensure the potential to be measured. The operation is performed in a linear operation area of the function block, wherein the function block is multiplexed to the first multiplex input and output pin.
如申請專利範圍第1項所述之電子裝置，其中該處理器更組態為初始化該第二多工輸入輸出腳位作輸入使用。
The electronic device of claim 1, wherein the processor is further configured to initialize the second multiplexed input and output pin for input.
如申請專利範圍第2項所述之電子裝置，其中，該處理器更組態為在該功能方塊完成動作後重置該第二多工輸入輸出腳位作輸入使用。
The electronic device of claim 2, wherein the processor is further configured to reset the second multiplexed input and output pin for input after the function block completes the action.
如申請專利範圍第1項所述之電子裝置，其中：
該第一阻抗元件的阻抗大於該第二阻抗元件一特定數量級；且該處理器更組態為在該待測電位低於一下臨界值時，切換該第二多工輸入輸出腳位輸出該高準位電位。
The electronic device of claim 1, wherein:
The impedance of the first impedance element is greater than a certain magnitude of the second impedance element; and the processor is further configured to switch the second multiplexed input and output pin output to be high when the potential to be measured is lower than a lower threshold Level potential.
如申請專利範圍第1項所述之電子裝置，其中：該第一阻抗元件的阻抗小於該第二阻抗元件一特定數量級；且該處理器更組態為在該待測電位高於一上臨界值時，切換該第二多工輸入輸出腳位輸出該低準位電位。
The electronic device of claim 1, wherein: the impedance of the first impedance element is less than a certain order of magnitude of the second impedance element; and the processor is further configured to be higher than an upper limit of the potential to be measured When the value is changed, the second multiplexed input/output pin is switched to output the low level potential.
如申請專利範圍第1項所述之電子裝置，其中該外接裝置具有一待測電阻，其一端具有該低準位電位，另一端在該外接裝置外接該外接裝置連結埠時與該外接裝置連結埠連結。
The electronic device of claim 1, wherein the external device has a resistance to be tested, the one end having the low level potential, and the other end being connected to the external device when the external device is externally connected to the external device埠 link.
一種處理器內部功能方塊的線性區操作方法，包括：以一處理器的一第一多工輸入輸出腳位連結一外接裝置連結埠，該外接裝置連結埠用於連結一外接裝置、且具有一待測電位；以一第一阻抗元件的一第一端連結該外接裝置連結埠、且將該第一阻抗元件的一第二端連接至一高準位電位；以一第二阻抗元件的一第一端連結該外接裝置連結埠、且將該第二阻抗元件的一第二端連接至該處理器的一第二多工輸入輸出腳位；並且在該待測電位位於該處理器內一功能方塊的一非線性操作區時，令該第二多工輸入輸出腳位輸出該高準位電位
或一低準位電位其中之一，以確保該待測電位操作在該功能方塊的一線性操作區內，其中，該功能方塊多工耦接該第一多工輸入輸出腳位。
A method for operating a linear area of a processor's internal function block includes: connecting a peripheral device connector with a first multiplexed input/output pin of a processor, the external device connector for connecting an external device, and having a a potential to be measured; a first end of a first impedance element is coupled to the external device connection port, and a second end of the first impedance element is coupled to a high level potential; The first end is connected to the external device connection port, and the second end of the second impedance element is connected to a second multiplexed input/output pin of the processor; and the potential to be measured is located in the processor When a non-linear operating area of the function block, the second multiplexed input and output pin outputs the high-level potential
Or one of the low level potentials to ensure that the potential to be tested is operated in a linear operation area of the function block, wherein the function block is multiplexed to the first multiplex input and output pin.
如申請專利範圍第7項所述之方法，更包括：初始化該第二多工輸入輸出腳位作輸入使用。
The method of claim 7, further comprising: initializing the second multiplexed input and output pin for input use.
如申請專利範圍第8項所述之方法，更包括：在該功能方塊完成動作後，重置該第二多工輸入輸出腳位作輸入使用。
The method of claim 8, further comprising: resetting the second multiplexed input and output pin for input after the function block completes the action.
如申請專利範圍第7項所述之方法，其中：該第一阻抗元件的阻抗大於該第二阻抗元件一特定數量級；並且在該待測電位低於一下臨界值時，切換該第二多工輸入輸出腳位輸出該高準位電位。
The method of claim 7, wherein: the impedance of the first impedance element is greater than a certain magnitude of the second impedance element; and switching the second multiplex when the potential to be measured is lower than a lower threshold The input and output pins output the high level potential.
如申請專利範圍第7項所述之方法，其中：該第一阻抗元件的阻抗小於該第二阻抗元件一特定數量級；並且在該待測電位高於一上臨界值時，切換該第二多工輸入輸出腳位輸出該低準位電位。
The method of claim 7, wherein: the impedance of the first impedance element is less than a certain order of magnitude of the second impedance element; and switching the second plurality when the potential to be measured is higher than an upper threshold The input and output pins output the low level potential.
如申請專利範圍第7項所述之方法，其中該低準位電位為該外接裝置的一待測電阻的一第一端所耦接的電位，該待測電阻的一第二端在該外接裝置外接該外接裝置連結埠時與該外接裝置連結埠連結。
The method of claim 7, wherein the low level potential is a potential coupled to a first end of a resistor to be tested of the external device, and a second end of the resistor to be tested is externally connected When the external device is connected to the external device, the device is connected to the external device.
一種電子裝置，包括：一處理器，包括：一第一多工輸入輸出埠以及相關的一第一多工輸
入輸出腳位；一第二多工輸入輸出埠以及相關的一第二多工輸入輸出腳位；一控制模組，控制上述第一以及第二多工輸入輸出埠，以設定上述第一以及第二多工輸入輸出腳位的作用；以及一類比數位轉換器，連結該第一多工輸入輸出埠，接收的是自該第一多工輸入輸出腳位輸入該處理器的類比信號；一外接裝置連結埠，用以連結一外接裝置，且在該電子裝置內部與該第一多工輸入輸出腳位連結；一第一阻抗元件，具有一第一端連結該外接裝置連結埠、且具有一第二端控制在一高準位電位，該高準位電位等同上述第二多工輸入輸出腳位輸出的一高準位狀態；以及一第二阻抗元件，耦接於該外接裝置連結埠以及該第二多工輸入輸出腳位之間；其中，若該待測電位位於該類比數位轉換器的一非線性操作區，該控制模組更控制該第二多工輸入輸出埠輸出該高準位電位或一低準位電位其中之一，以確保該待測電位操作在該類比數位轉換器的一線性操作區內。
An electronic device comprising: a processor comprising: a first multiplex input/output port and an associated first multiplex input
Input and output pin; a second multiplexed input/output port and an associated second multiplex input/output pin; a control module that controls the first and second multiplexed input and output ports to set the first and a function of the second multiplexed input and output pin; and an analog-to-digital converter coupled to the first multiplexed input/output port, receiving an analog signal input to the processor from the first multiplexed input/output pin; The external device is connected to the external device and is connected to the first multiplexed input and output pin; the first impedance element has a first end coupled to the external device, and has a second terminal is controlled at a high level potential, the high level potential is equal to a high level state of the second multiplexed input and output pin output; and a second impedance element is coupled to the external device. And the second multiplexed input/output pin; wherein, if the potential to be measured is located in a non-linear operation area of the analog-to-digital converter, the control module further controls the second multiplex input/output and outputs the Level potential or a low potential wherein one level, to ensure that the operation test potential linear operating area of such digital converter ratio.
如申請專利範圍第13項所述之電子裝置，其中該控制模組更控制該第二多工輸入輸出埠初始化該第二多工輸入輸出腳位作輸入使用。
The electronic device of claim 13, wherein the control module further controls the second multiplex input and output, and initializes the second multiplexed input and output pin for input.
如申請專利範圍第14項所述之電子裝置，其中該
控制模組更在該類比數位轉換器完成動作後，控制該第二多工輸入輸出埠重置該第二多工輸入輸出腳位作輸入使用。
The electronic device of claim 14, wherein the electronic device
The control module further controls the second multiplexed input and output and resets the second multiplexed input and output pin for input after the analog digital converter completes the action.
如申請專利範圍第13項所述之電子裝置，其中：該第一阻抗元件的阻抗大於該第二阻抗元件一特定數量級；並且在該待測電位落入該類比數位轉換器的一低部非線性操作區時，該控制模組控制該第二多工輸入輸出埠，使該第二多工輸入輸出腳位停止作輸入使用，改切換為輸出上述高準位狀態。
The electronic device of claim 13, wherein: the impedance of the first impedance element is greater than a certain order of magnitude of the second impedance element; and the potential to be measured falls into a lower portion of the analog-to-digital converter In the linear operation area, the control module controls the second multiplexed input/output port, so that the second multiplexed input/output pin is stopped for input use, and is switched to output the high level state.
如申請專利範圍第13項所述之電子裝置，其中：該第一阻抗元件的阻抗小於該第二阻抗元件一特定數量級；且在該待測電位落入該類比數位轉換器的一高部非線性操作區時，該控制模組控制該第二多工輸入輸出埠，使該第二多工輸入輸出腳位停止作輸入使用，改切換為輸出上述低準位狀態。
The electronic device of claim 13, wherein: the impedance of the first impedance element is less than a certain order of magnitude of the second impedance element; and the potential to be measured falls into a high portion of the analog-to-digital converter In the linear operation area, the control module controls the second multiplex input/output port, so that the second multiplex input/output pin is stopped for input use, and is switched to output the low level state.
如申請專利範圍第1項所述之電子裝置，其中該第二多工輸入輸出腳位係由一通用型輸入輸出腳位實現。
The electronic device of claim 1, wherein the second multiplexed input/output pin is implemented by a general-purpose input/output pin.
如申請專利範圍第7項所述之方法，更包括採用一通用型輸入輸出腳位實現該第二多工輸入輸出腳位。
The method of claim 7, further comprising implementing the second multiplexed input and output pin by using a general-purpose input/output pin.
如申請專利範圍第13項所述之電子裝置，其中該第二多工輸入輸出腳位係由一通用型輸入輸出腳位實現。The electronic device of claim 13, wherein the second multiplexed input and output pin is implemented by a general-purpose input and output pin.