TWI454014B - Power management module for solar cell, power management method for solar cell and calculator using the same - Google Patents

Description

Solar power management module, solar power management method, and electronic computer using the same

The present invention relates to the use of a solar cell, and more particularly to a solar power management module, method, and electronic computer using the same.

A solar cell is an optoelectronic semiconductor chip that directly generates electricity by using sunlight. It can output voltage and current in an instant as long as it is illuminated. Such a solar cell is simply referred to as a solar cell or a solar cell.

Solar panels are precisely the application of the photoelectric effect principle in power production. When sunlight hits the surface of a metal or semiconductor, some of the photons hit the metal or semiconductor atoms, and part of the photon energy is converted into the energy of the outer electrons of the atom, which frees the electrons from the atoms. Energy is converted into kinetic energy that the electrons fly off the atom. The free electrons have a negative electric field and form a negative voltage in the conductor, so they flow to a region where the potential is relatively high (ie, the negative value is low). If it can be properly regulated, it can be made for human application. Electrical energy.

However, solar products generally need to be used in the presence of sunlight. If there is not enough sunlight to drive the solar cells, the above solar energy products will soon enter a state of no power, resulting in the inability to use the screen or buttons, and may even be interrupted for a moment, causing user inconvenience.

It is an object of the present invention to provide a solar power management module that detects solar cells to extend product life.

Another object of the present invention is to provide a solar power management method for adaptively adjusting the operating clock so that the product is not interrupted by insufficient power.

It is an object of the present invention to provide a solar electronic computer that minimizes operating frequency when solar energy is unstable to avoid computational interruption.

The invention provides a solar power management module, which comprises an oscillator, a frequency dividing circuit, a solar battery, a detecting circuit and a control circuit. The oscillator is used to provide a preset clock signal. The frequency dividing circuit is coupled to the oscillator, and receives the preset clock signal for dividing the preset clock signal output by the oscillator according to a frequency dividing parameter to output a frequency dividing clock signal. The solar cell is used to receive a solar energy to supply a power supply voltage. The detecting circuit is coupled to the solar cell and receives the power voltage to detect the magnitude of the power voltage. The control circuit is coupled to the detection circuit, and adjusts the frequency division parameter of the frequency division circuit according to the value of the power supply voltage detected by the detection circuit. When the detecting circuit detects that the power supply voltage is lower than a predetermined voltage, the control circuit sends the frequency dividing parameter to the frequency dividing circuit, so that the frequency dividing circuit outputs the divided frequency-divided clock signal. Drop to a minimum frequency. When the detecting circuit detects that the power supply voltage rises and exceeds the preset voltage, the control circuit sends the frequency dividing parameter to the frequency dividing circuit, so that the frequency dividing circuit adjusts the frequency dividing frequency and gradually increases the frequency. The frequency of the frequency division signal.

In addition, the present invention also provides a solar power management method, the method comprising the steps of: converting a solar energy into a power supply voltage; providing a predetermined clock signal; detecting a magnitude of the power supply voltage; providing a frequency division a parameter, configured to perform frequency division on the preset clock signal to obtain a frequency-divided clock signal; use a frequency-divided clock signal as a working clock; and when detecting that the power supply voltage drops and is lower than a preset voltage, adjusting The frequency division parameter reduces the frequency division clock signal to a lowest frequency; and when the power source voltage rises and exceeds the preset voltage, the frequency division parameter is gradually adjusted, and the frequency of the frequency division clock signal is gradually increased.

In addition, the present invention also provides a solar electronic computer comprising a display, a button module, an oscillator, a frequency dividing circuit, a solar cell, a detecting circuit and a control circuit. The display is used to display a number. The button module includes a plurality of numeric buttons and a plurality of arithmetic buttons. The oscillator is used to provide a predetermined clock signal. The frequency dividing circuit is coupled to the oscillator, and receives the preset clock signal for dividing the preset clock signal output by the oscillator according to a frequency dividing parameter to output a frequency dividing clock signal. The solar cell is used to receive a solar energy to supply a power supply voltage. The detecting circuit is coupled to the solar cell and receives the power voltage to detect the magnitude of the power voltage. The control circuit is coupled to the detection circuit, and adjusts the frequency division parameter of the frequency division circuit according to the value of the power supply voltage detected by the detection circuit. When the detecting circuit detects that the power supply voltage is lower than a predetermined voltage, the control circuit sends the frequency dividing parameter to the frequency dividing circuit, so that the frequency dividing circuit outputs the divided frequency-divided clock signal. Drop to a minimum frequency. When the detecting circuit detects that the power supply voltage rises and exceeds the preset voltage, the control circuit sends the frequency dividing parameter to the frequency dividing circuit, so that the frequency dividing circuit adjusts the frequency dividing frequency and gradually increases the frequency. The frequency of the frequency division signal. When the solar computer performs an operation, the frequency-divided clock signal output by the frequency-dividing circuit is used as its operating frequency.

The spirit of the present invention is mainly based on the characteristics of the solar cell. When the solar energy is insufficient, the frequency of the working clock is adjusted to the minimum to avoid the calculation interruption. When the solar energy gradually recovers, the frequency of the working clock is gradually adjusted. Go back to the original frequency. In this way, it is possible to avoid interruption of the solar product during operation. It is also possible to increase the operating time of solar products.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

[First Embodiment]

1 is a schematic view of a solar electronic computer according to a first embodiment of the present invention. Referring to FIG. 1 , the solar computer 100 includes a display 101 , a button module 102 , and a solar cell 103 . In order to fully explain the technology of the present invention, please refer to FIG. 2. FIG. 2 is a circuit block diagram of a solar electronic computer according to a first embodiment of the present invention. As shown in FIG. 2, the solar computer includes a display 101, a button module 102, and a solar cell 103, and includes an oscillator 201, a frequency dividing circuit 202, a detecting circuit 203, and a control circuit 204. The coupling relationship is shown in Figure 2. Among them, the solar battery cell 103 can receive an ambient light source for charging. Moreover, the solar cell 103 outputs a power supply voltage VDC to the detecting circuit 203, so that the detecting circuit 203 detects the voltage value of the power supply voltage VDC.

The control circuit 204 is coupled to the display 101, the button module 102, the frequency dividing circuit 202, and the detecting circuit 203, and receives the frequency-divided clock signal DCK as the operating clock of the solar computer, and according to a user-to-key module 102. An arithmetic operation that performs a numerical operation.

When the solar energy is sufficient, the frequency division parameter of the frequency division clock signal DCK is 1, that is, when the frequency division clock signal DCK is equal to the output of the oscillator 201. Pulse signal CLK. Therefore, the operating frequency of the control circuit 204 is the frequency of the clock signal CLK. When the light is insufficient, the voltage of the solar cell will continue to drop. When the detecting circuit 203 detects that the power supply voltage VDC is lower than a predetermined voltage, the control circuit 204 sends the frequency dividing parameter PAR to the frequency dividing circuit 202. To simplify the description of the embodiment, the frequency dividing parameter PAR of the present case includes 1, 2 , 4, 8, and 16. In this example, when the detecting circuit 203 detects that the power supply voltage VDC drops and is lower than the preset voltage, it indicates that the power is insufficient, and the control circuit 204 outputs the frequency dividing parameter PAR=16. At this time, the frequency dividing circuit 202 reduces the output frequency-divided clock signal DCK signal to the lowest frequency, that is, one-sixteenth of the frequency of the CLK, to prevent the solar computer 100 from calculating the power-off.

At this point, the solar computer 100 operates at the lowest frequency (CLK/16) such that the solar computer 100 spends less power. At the same time, the solar cell 103 still receives the ambient light source and continues to charge and store energy, so that the power supply voltage VDC rises gradually. When the detecting circuit 203 detects that the power supply voltage VDC rises and exceeds the preset voltage, the control circuit 204 sends the frequency dividing parameter PAR=8 to the frequency dividing circuit 202, so that the frequency dividing circuit adjusts the frequency dividing frequency upward. When the power supply voltage VDC rises again, the control circuit 204 again adjusts the frequency-dividing parameter PAR to 6, so that the frequency of the frequency-divided clock signal DCK is gradually increased, so that the solar-powered electronic computer 100 returns to normal operation.

When the control circuit 204 controls the frequency dividing circuit 202 to gradually increase the frequency-divided clock signal DCK, if the ambient light source is weak such that the power supply voltage VDC output by the solar battery 103 drops again and is lower than the preset voltage, the control circuit 204 again Adjusting the frequency division parameter PAR=16 causes the frequency-divided clock signal DCK signal output by the frequency dividing circuit 202 to be reduced to the lowest frequency to prevent the solar computer 100 from calculating the power-off.

It should be noted that, in the embodiment of the present invention, the power management module of the solar computer 100 can also be applied to dual power supply or multiple power supplies. The mechanism for operating the frequency provided by this embodiment may be that the power supply is switched on when it is switched to a solar battery. Alternatively, the mechanism of the operating frequency provided by the embodiment will be activated when only the solar cell is left in the power supply.

In addition, the value of the preset voltage may be set by the designer according to the power required by the power supply system or the computer, or may be adaptively adjusted according to the actual power supply and the power consumption.

[Second embodiment]

The above embodiment can be summarized into a solar power management method, and FIG. 3 is a flowchart of the solar power management method according to the second embodiment of the present invention. Please refer to Figure 3. This method includes the following steps:

Step S302: Converting a solar energy into a power supply voltage.

Step S303: providing a preset clock signal CLK.

Step S304: Provide a frequency division parameter PAR. The frequency division parameter PAR includes 1, 2, 4, 8, and 16. The preset value of the frequency division parameter PAR may be PAR=1, so that the computer starts to operate at full frequency. Alternatively, the preset value of the frequency parameter PAR can also be pre-designed by the system designer.

Step S305: Detect the size of the power supply voltage VDC.

Step S306: Adjust the frequency division parameter PAR according to the detected size of the power supply voltage VDC. When the power supply voltage VDC is detected to be lower than the preset voltage, the frequency-dividing parameter PAR is adjusted to reduce the frequency-divided clock signal DCK to a lowest frequency. In this example, when the power supply voltage VDC is lower than the preset voltage, the frequency division parameter PAR will be set to 16.

Step S307: Demultiplexing the preset clock signal CLK by using the frequency division parameter PAR to obtain a frequency division clock signal DCK. The frequency division clock signal DCK is CLK/PAR. The lowest frequency of the frequency-divided clock signal DCK is CLK/16.

Step S308: Using the frequency division clock signal DCK as the operating clock. When the computer is operating at the lowest frequency, the computer consumes less power, so that the solar cell 103 still receives the ambient light source and continues to charge and store energy, causing the power supply voltage VDC to rise gradually. At this time, in the above steps S305-S307, the power supply voltage VDC is still continuously detected. When the power supply voltage rises and exceeds the preset voltage, the frequency-dividing parameter PAR is gradually adjusted to gradually increase the frequency-divided clock. The frequency of the signal DCK.

When the frequency-repeating clock signal DCK is gradually increased, if the ambient light source is weak and the power supply voltage VCD drops again and is lower than the preset voltage, in the above steps S305-S307, the frequency-dividing parameter PAR=8 is adjusted again. The de-clocked signal DCK signal is reduced to the lowest frequency to avoid the computer 100 calculating that half of the power is off.

[Third embodiment]

4 is a system block diagram of a solar power management module according to an embodiment of the present invention. Referring to FIG. 4, the solar power management module includes a solar cell 410, a detection circuit 420, a control circuit 430, an oscillator 440, a frequency dividing circuit 450, a setting unit 460, and a load unit 470, and the coupling relationship thereof is as shown. Among them, the solar battery cell 410 can receive an ambient light source for charging. Moreover, the solar cell 410 outputs a power voltage VDC to the detecting circuit 420, so that the detecting circuit 420 detects the voltage value of the power voltage VDC.

The oscillator 440 generates an oscillation frequency CLK and outputs it to the frequency dividing circuit 450. The control circuit 430 is coupled to the detection circuit 420, the frequency dividing circuit 450 and the setting unit 460, and controls the frequency-divided clock signal DCK output by the frequency dividing circuit 450 to the load unit 470 according to the detection result of the detecting circuit 430. The load unit 470 is coupled to the frequency dividing circuit 450 and the solar cell 410, and uses the received frequency-divided clock signal DCK as the operating frequency.

When the solar energy is sufficient, the solar cell can be quickly charged, and the output power voltage VDC is higher than a predetermined voltage. When the detecting circuit 420 detects that the power supply voltage VDC is higher than the preset voltage, the control circuit 430 sets the output frequency dividing parameter PAR to 1, so that the frequency dividing clock signal DCK is equal to the clock signal output by the oscillator 440. CLK. In the case of insufficient light, when the detecting circuit 420 detects that the power supply voltage VDC is lower than the preset voltage, the control circuit 430 outputs the maximum frequency dividing parameter PAR, so that the frequency-divided clock signal DCK is reduced to the lowest frequency. At this time, the operating frequency of the load unit 470 is the lowest frequency, so that the power consumption of the load unit 470 is lowered to prevent the solar battery 410 from suddenly stopping the power supply. In the present embodiment, the frequency division parameters PAR are, for example, 1, 2, 4, 8, and 16. The lowest frequency of the frequency-division signal DCK is CLK/16.

The control circuit 430 starts counting for a preset time after outputting PAR=16. When the control circuit 430 counts up to the preset time, it will re-detect whether the power supply voltage VDC is lower than the preset voltage. If the power supply voltage VDC at this time is higher than the preset voltage, the control circuit 430 outputs the frequency dividing parameter PAR=8, so that the frequency-divided clock signal DCK is raised to CLK/8. By analogy, if the power supply voltage VDC is maintained above the preset voltage, the control circuit 430 gradually increases the frequency-divided clock signal DCK through the frequency-dividing parameter PAR. On the contrary, after the preset time is counted, if the detected power supply voltage VDC is lower than the preset voltage, the control circuit 430 will increase the output frequency dividing parameter PAR, so that the frequency-divided clock signal DCK decreases. The frequency-divided clock signal DCK has been reduced to the lowest frequency CLK/16, and the lowest frequency-divided clock signal DCK is maintained.

The setting unit 460 is configured to set the preset time. In other words, in the embodiment of the present invention, the time length of detecting the power voltage VDC can be set by the user or the circuit designer, or according to the actual power supply and The power consumption of the load is adaptively adjusted. In addition, the value of the preset voltage may be set by the designer according to the power required by the power supply system or the load, or adaptively adjusted according to the actual power supply and the power consumption.

The solar power management module proposed in this embodiment can be applied to a solar electronic computer. In other words, the above load unit includes, for example, a display, a button module, and a microprocessor. The display is used to display a number. The button module includes a plurality of numeric buttons and a plurality of arithmetic buttons. The microprocessor is used for performing arithmetic processing, and receives the frequency-divided clock signal output by the frequency-dividing circuit. The microprocessor uses the received frequency-divided clock signal as its operating clock. Therefore, when there is insufficient solar energy around, the solar computer will reduce its operating frequency and reduce the power consumption to avoid sudden interruption or shutdown of computer operations.

[Fourth embodiment]

FIG. 5 is a system block diagram of a solar power management module according to a fourth embodiment of the present invention. Referring to FIG. 5, the operations of the solar cell 410, the detecting circuit 420, the control circuit 430, the oscillator 440, the setting unit 460, and the load unit 470 are the same as those in FIG. 4 described above, and thus are not described in detail herein. The frequency dividing circuit 550 includes a plurality of frequency dividing units 501 to 505 of different levels, and the control circuit 430 determines which frequency dividing unit 501 to 505 outputs the frequency dividing clock signal DCK to the load unit 470.

[Fifth Embodiment]

The above embodiment can be summarized into a solar power management method, and FIG. 6 is a flowchart of a solar power management method according to a sixth embodiment of the present invention. Here, for convenience of description of the present embodiment, the solar power management method is applied to a solar computer. Referring to FIG. 6, the method includes the following steps: Step S601: Start each step of the solar power management method.

Step S602: Entering the standby mode. At this point, the computer only begins to display and does not begin operation, only the solar computer only waits for instructions to receive operations or operations.

Step S605: Enter an operation mode. In this embodiment, when the user inputs an operation or operation command to the solar computer through the input interface, the operation mode is entered.

Step S610: detecting whether the power supply voltage VDC is lower than a preset voltage. When the power supply voltage VDC is lower than the preset voltage, step S615 is performed. When the power supply voltage VDC is equal to or greater than the preset voltage, step S655 is performed.

Step S615: Lowering the frequency dividing circuit to the lowest order, so that the frequency dividing clock signal DCK is the lowest frequency.

Step S620: Counting a preset time. After the counting period expires, step S625 is performed.

Step S625: detecting whether the power supply voltage VDC is lower than a preset voltage. When the power supply voltage VDC is equal to or greater than the preset voltage, step S630 is performed. when If the power supply voltage VDC is lower than the preset voltage, step S670 is performed.

Step S630: Check if the frequency dividing circuit is already the highest order. When the frequency dividing circuit has not risen to the highest level, step S635 is performed. When the frequency dividing circuit is already the highest order, step S640 is performed.

Step S635: The frequency dividing circuit is raised by one step.

Step S640: Maintain the frequency division of the original frequency dividing circuit.

Step S645: Check if the operation of the computer is completed. If the calculation is not completed, step S650 is performed. If the calculation is completed, it returns to step S605. In this embodiment, since the solar power management method is applied to a computer, after the computer operation is completed, it returns to the initial state.

Step S650: Counting a preset time. After the counting period expires, step S625 is performed.

Step S655: setting the frequency dividing circuit to the highest order, so that the load can use the high speed operation.

Step S660: Counting a preset time. After the counting period expires, step S665 is performed.

Step S665: Detect whether the power supply voltage VDC is lower than a preset voltage. When the power supply voltage VDC is lower than the preset voltage, step S670 is performed. When the power supply voltage VDC is equal to or greater than the preset voltage, step S680 is performed.

Step S670: Check if the frequency dividing circuit is already the lowest order. When the frequency dividing circuit has not fallen to the lowest order, step S675 is performed. When the frequency dividing circuit is already the lowest order, step S640 is performed.

Step S675: Lowering the frequency dividing circuit to the lowest order, so that the frequency dividing clock signal DCK is the lowest frequency.

Step S680: Maintain the frequency division of the original frequency dividing circuit.

As can be seen from the above embodiments, the present patent uses the voltage of the solar cell 103 to be detected, and the computer is divided into three types of working states:

(1) When the power supply voltage VDC is in a strong power supply, the load performance is improved to achieve a higher operation speed.

(2) When the power supply voltage VDC is in a weak power supply, the load performance is reduced to achieve a more power-saving mode.

(3) When the power supply voltage VDC is not enough to supply the highest load performance, the progressive method is used to find the maximum load performance available for the solar battery.

In addition, the embodiment further provides an interrupt command. When the firmware in the system detects that the power voltage VDC is too low, an interrupt command is directly issued, and the control circuit 430 stops the above steps, and directly removes the frequency dividing circuit 450 ( Or 550) is reduced to the lowest order. In other words, when the control circuit 430 receives the interrupt command, the above step S615 is directly performed to prevent the solar battery 410 from suddenly stopping the power supply to prevent the computer from being turned off halfway.

In summary, the spirit of the present invention is mainly based on the characteristics of the solar cell, when the solar energy is insufficient, the frequency of the working clock is adjusted to the minimum to avoid the calculation interruption, and when the solar energy gradually recovers, the working clock is gradually stepped. The frequency is gradually adjusted back to the original frequency. In this way, it is possible to avoid interruption of the solar product during operation. It is also possible to increase the operating time of solar products.

The specific embodiments of the present invention are intended to be illustrative only and not to limit the invention to the above embodiments, without departing from the spirit of the invention and the following claims. The scope of the invention and the various changes made are within the scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧ solar computer

101‧‧‧ display

102‧‧‧Key Module

103, 410‧‧‧ solar cells

201, 440‧‧‧ oscillator

202, 450‧‧‧ Frequency dividing circuit

203, 420‧‧‧Detection circuit

204, 430‧‧‧ control circuit

460‧‧‧Setting unit

470‧‧‧Load unit

501~505‧‧‧Division unit

550‧‧‧frequency circuit

DCK‧‧‧frequency clock signal

CLK‧‧‧ clock signal

VDC‧‧‧Power supply voltage

PAR‧‧‧frequency parameter

S302~S308‧‧‧ steps of the solar power management method of the second embodiment of the present invention

S601~S680‧‧‧ steps of the solar power management method of the fifth embodiment of the present invention

1 is a schematic diagram of a solar electronic computer in accordance with an embodiment of the present invention.

2 is a circuit block diagram of a solar electronic computer according to an embodiment of the present invention.

FIG. 3 is a flow chart of a solar power management method according to an embodiment of the present invention.

4 is a system block diagram of a solar power management module according to an embodiment of the present invention.

FIG. 5 is a system block diagram of a solar power management module according to a fourth embodiment of the present invention.

FIG. 6 is a flowchart of a solar power management method according to a sixth embodiment of the present invention.

S301～S308. . . Each step of the solar power management method of the embodiment of the invention

Claims (25)

A solar power management module includes: an oscillator for providing a preset clock signal; a frequency dividing circuit coupled to the oscillator to receive the preset clock signal for using a frequency dividing parameter The preset clock signal outputted by the oscillator is divided to output a frequency-divided clock signal; a solar battery is used to receive a solar energy to supply a power voltage; and a detecting circuit is coupled to the solar energy The battery receives the power voltage for detecting the magnitude of the power voltage; and a control circuit coupled to the detecting circuit and adjusting the frequency dividing circuit according to the value of the power voltage detected by the detecting circuit The frequency-dividing parameter, wherein when the detecting circuit detects that the power voltage is lower than a predetermined voltage, the control circuit sends the frequency-dividing parameter to the frequency-dividing circuit, so that the frequency-dividing circuit outputs the The frequency-divided clock signal is reduced to a lowest frequency. When the detecting circuit detects that the power supply voltage rises and exceeds the preset voltage, the control circuit sends the frequency-dividing parameter to the frequency-dividing circuit, so that the Frequency dividing circuit adjustment And gradually increases the frequency of the clock signal when the frequency divider. The solar power management module of claim 1, further comprising: after the power supply voltage is raised and the frequency dividing circuit gradually increases the frequency-divided clock signal, the preset voltage is again decreased and is lower than When the voltage is preset, the control circuit adjusts the frequency division parameter to reduce the frequency division clock signal to the lowest frequency. The solar power management module of claim 1, wherein the frequency dividing circuit has an Nth order, wherein the frequency of the i+1th order output is smaller than the frequency of the ith order output, wherein N and i are A positive integer. The solar power management module of claim 1, wherein the frequency dividing circuit is coupled to the control circuit, and receives the frequency-divided clock signal as its operating clock. The solar power management module of claim 1, wherein the frequency dividing circuit is coupled to a load unit, and the load unit receives the frequency-divided clock signal as its operating clock. The solar power management module of claim 1, further comprising: a setting unit configured to set a preset time, wherein the preset time is a length of time each time the power voltage is detected. The solar power management module of claim 1, wherein the frequency dividing circuit has an Nth order, wherein the frequency of the i+1th output is smaller than the frequency of the ith output, and the control circuit outputs the After the frequency division parameter is used to reduce the frequency division clock signal to the lowest frequency, the control circuit counts a preset time, and when the preset time count expires, detecting whether the power supply voltage is lower than the preset voltage, When the power supply voltage is greater than or equal to the preset voltage, the frequency dividing circuit is controlled to be up to the first step. When the power supply voltage is less than the predetermined voltage, the order of the frequency dividing circuit is maintained, where N and i are positive integers. The solar power management module of claim 1, wherein the frequency division parameter is used to change the frequency of the preset clock signal to: a frequency of the preset clock signal/the frequency division parameter. The solar power management module of claim 3, wherein the frequency division parameter comprises 1, 2, 4, 8, and 16. A solar power management method, the method comprising: converting a solar energy into a power supply voltage; providing a preset clock signal; detecting a magnitude of the power supply voltage; providing a frequency division parameter, and performing the preset clock signal De-frequencying to obtain a frequency-divided clock signal; using the frequency-divided clock signal as a working clock; when detecting that the power-supply voltage drops to a predetermined voltage, adjusting the frequency-dividing parameter to make the frequency-dividing clock signal Decrease to a minimum frequency; and when the power supply voltage rises and exceeds the preset voltage, gradually adjust the frequency division parameter and gradually increase the frequency of the frequency division clock signal. The solar power management method according to claim 10, further comprising: after the power supply voltage is raised and the frequency dividing circuit gradually increases the frequency-divided clock signal, the preset voltage is again decreased and lower than the When the voltage is preset, the frequency division parameter is adjusted to reduce the frequency division clock signal to the lowest frequency. The solar power management method of claim 10, further comprising: providing a preset time, the preset time being a length of time each time the power voltage is detected. The solar power management method of claim 12, wherein the frequency of the frequency division clock signal has an Nth order, and the frequency of the i+1th order is smaller than the frequency of the ith order, wherein, at the frequency division After the pulse signal is reduced to the minimum frequency, the method further includes: counting the preset time; when the preset time count expires, detecting whether the power voltage is lower than the preset voltage; when the power voltage is greater than or equal to the preset Voltage, adjusting the frequency division parameter to increase the frequency of the frequency division clock signal by one order; and maintaining the order of the frequency division clock signal when the power supply voltage is less than the preset voltage, wherein N and i are positive integers . The solar power management method of claim 10, wherein the frequency division parameter is used to change the frequency of the preset clock signal to: a frequency of the preset clock signal/the frequency division parameter. The solar power management method of claim 14, wherein the frequency division parameter comprises 1, 2, 4, 8, and 16. The solar power management method of claim 10, wherein when the value of the power supply voltage is lower than the predetermined voltage, an interrupt command is issued to reduce the frequency-divided clock signal to the lowest frequency. A solar computer includes: a display for displaying a number; a button module comprising a plurality of numeric buttons and a plurality of arithmetic buttons; an oscillator for providing a predetermined clock signal; and a frequency dividing circuit The oscillator is coupled to receive the preset clock signal for de-frequencying the preset clock signal outputted by the oscillator according to a frequency-dividing parameter to output a frequency-divided clock signal; a battery for receiving a solar energy to supply a power voltage; a detecting circuit coupled to the solar cell, receiving the power voltage for detecting a magnitude of the power voltage; and a control circuit coupled to the detecting a circuit, and adjusting the frequency dividing parameter of the frequency dividing circuit according to the value of the power voltage detected by the detecting circuit, wherein when the detecting circuit detects that the power voltage is lower than a preset voltage, The control circuit sends the frequency-dividing parameter to the frequency-dividing circuit, so that the frequency-dividing circuit reduces the output of the frequency-divided clock signal to a lowest frequency, and when the detecting circuit detects that the power-supply voltage rises, exceed When the voltage is preset, the control circuit sends the frequency division parameter to the frequency dividing circuit, so that the frequency dividing circuit adjusts the frequency of the frequency division and gradually increases the frequency of the frequency division clock signal; wherein, when the solar computer performs the operation The frequency division clock signal output by the frequency dividing circuit is used as its operating frequency. The solar electronic computer of claim 17, further comprising: after the power supply voltage is raised and the frequency dividing circuit gradually increases the frequency-divided clock signal, the preset voltage is again decreased and is lower than the preset When the voltage is set, the control circuit adjusts the frequency division parameter to reduce the frequency division clock signal to the lowest frequency. The solar computer of claim 17, wherein the frequency dividing circuit has an Nth order, wherein the frequency of the i+1th order output is smaller than the frequency of the ith order output, wherein N and i are positive integers. The solar computer of claim 17, wherein the frequency dividing circuit is coupled to the control circuit, and receives the frequency-divided clock signal as its operating clock. The solar computer of claim 17, wherein the frequency dividing circuit is coupled to a load unit, and the load unit receives the frequency division clock signal as its operating clock. The solar electronic computer of claim 17, further comprising: a setting unit configured to set a preset time, wherein the preset time is a length of time each time the power supply voltage is detected. The solar computer of claim 17, wherein the frequency dividing circuit has an Nth order, wherein the frequency of the i+1th order output is smaller than the frequency of the ith order output, and the dividing circuit is outputted by the control circuit. a parameter, after the frequency-divided clock signal is reduced to the lowest frequency, the control circuit starts counting for a preset time, and when the preset time count expires, detecting whether the power supply voltage is lower than the preset voltage, when The power supply voltage is greater than or equal to the preset voltage, and the frequency dividing circuit is controlled to be up one step. When the power supply voltage is less than the preset voltage, the order of the frequency dividing circuit is maintained, where N and i are positive integers. The solar computer of claim 17, wherein the frequency division parameter is used to change the frequency of the preset clock signal to: a frequency of the preset clock signal / the frequency division parameter. The solar computer of claim 24, wherein the frequency division parameter comprises 1, 2, 4, 8, and 16.