TWI452685B - Solid state imaging device - Google Patents

Description

Solid state imaging device

Cross-reference to related applications

The present application claims priority based on Japanese Patent Application (Application No. 2009-130589) filed on May 29, 2009, and is incorporated herein in its entirety.

The present invention relates to a solid state imaging device.

One of the solid state imaging devices is known as a CMOS image sensor. The CMOS image sensor features a single power supply, low voltage drive, and low power consumption. Like the CCD, the CMOS image sensor is multi-pictured and miniaturized, and a photodiode (photoelectric conversion element) and a transistor are formed on the same substrate.

Further, in the CMOS image sensor, the potential of the signal charge storage portion is modulated by the signal charge generated by the photoelectric conversion element, and the potential of the pixel inside the pixel is modulated by the potential to be amplified inside the pixel. Features.

In the CMOS image sensor, it is very important to reduce the electrical noise of the photodiode in the pixel and reduce the signal noise. For example, when the photodiode is composed of an N-type epitaxial growth layer and a P-type diffusion layer, the electrical separation is achieved by a P-type diffusion layer surrounding the P-type diffusion layer (for example, refer to JP-A-2006-286933) Bulletin).

However, even if this electrical separation is performed, signal noise will still occur.

Specifically, a pixel transistor for reading a signal by a photodiode is composed of a read transistor, a reset transistor, and an amplifying transistor, and these are formed on a P-type diffusion layer.

In such a configuration, when the light is obliquely incident on the photodiode, electrons are generated in the P-type diffusion layer (the neutral region where the electric field is zero).

The electrons generated in the P-type diffusion layer are moved by diffusion to enter a pixel transistor other than the pixel transistor that must be detected by the electron (for example, reading of the transistor). Part), become a signal noise.

A solid-state imaging device according to an aspect of the present invention includes a semiconductor layer having a first conductivity type, a diffusion layer having a second conductivity type and an array arranged in the semiconductor layer, and each of which constitutes a pixel. a pixel transistor disposed on the semiconductor layer and disposed under the pixel transistor, and disposed not on the insulating layer directly under the plurality of diffusion layers, wherein the pixel transistor is disposed Between pixels other than the pixels that are electrically connected.

Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to the drawings.

Here, as an example of the solid-state imaging device, a CMOS image sensor is taken as an example.

Device structure

(1) Floor plan

Figure 1 is a plan view of a CMOS image sensor.

In the wafer 1, a pixel area PA constituting a main portion of the CMOS image sensor is disposed. The area other than the pixel area PA is a peripheral circuit area.

The pixel area PA is composed of a plurality of pixels.

FIG. 2 shows a portion X of the pixel area PA of FIG. 1 in detail.

The plural pixels 2A, 2B, 2C, and 2D are arranged in an array. Each of the pixels 2A, 2B, 2C, and 2D is composed of, for example, a photodiode as an optical conversion element.

A region between the complex pixels 2A, 2B, 2C, and 2D is disposed with a pixel Q4 for reading signals by the photodiode. In this example, the pixel transistor 4 is provided for one of the two pixels 2A, 2B.

The pixel transistor 4 is composed of, for example, a read transistor 5 connected in series, a reset transistor 6 and an amplifier transistor 7. These transistors are composed, for example, of field effect transistors (FETs).

The read transistor 5 has a gate 8, the reset transistor 6 has a gate 9, and the amplifying transistor 7 has a gate 10.

Directly below the pixel transistor 4, a diffusion layer for the electrical separation of the plurality of pixels 2A, 2B, 2C, and 2D is disposed.

Here, the pixel crystals 4 of the pixels 2A and 2B are arranged from the end portions of the pixels 2A and 2B toward the other pixels 2C and 2D different from the pixels 2A and 2B.

In other words, in such a configuration, for example, the electrons generated in the diffusion layer by the obliquely incident light of the pixels 2C and 2D have the possibility of entering the pixel crystals 4 of the pixels 2A and 2B to become signal noise.

Here, the structure of the apparatus for preventing the signal noise is explained below.

(2) Sectional view

Fig. 3 is a first example of the structure of the display device.

This figure is a cross-sectional view taken along line II-II of Fig. 2.

An N-type epitaxial growth layer (N-epi) 12A is disposed on the P-type semiconductor substrate (P-sub) 11. In the N-type epitaxial growth layer 12A, the N ⁺ -type diffusion layer 13 is disposed. The photodiode is composed of a P-type semiconductor substrate 11, an N-type epitaxial growth layer 12A, and an N ⁺ -type diffusion layer 13.

Further, in the N-type epitaxial growth layer 12A, the P ⁺ -type diffusion layer 14 and the P-type well region 20 are disposed. The P ⁺ -type diffusion layer 14 surrounds the photodiode to realize electrical separation of the photodiode.

On the P-type well region 20 on the P ⁺ -type diffusion layer 14, a pixel transistor 4 for reading a signal from a pixel (photodiode) 2A is disposed. The pixel transistor 4 is connected to a corner of the N ⁺ -type diffusion layer 13 having a square shape in plan view.

The pixel transistor 4 is composed of, for example, a read transistor 5 connected in series, a reset transistor 6, and an amplifying transistor 7. These transistors are composed of, for example, an N-channel type field effect transistor (FET).

The read transistor 5 has a gate 8, the reset transistor 6 has a gate 9, and the amplifying transistor 7 has a gate 10.

The N-type diffusion layers 15, 16, 17 become the source/drain of the pixel transistor 4, respectively. Among them, the N-type diffusion layer 15 that becomes the drain of the transistor 5 is particularly referred to as a detection portion. The N-type diffusion layer 15 as a detecting portion is electrically connected to the gate 10 of the amplifying transistor 7.

Here, in this example, the insulating layer 18 is disposed between the pixel transistor and the P ⁺ -type diffusion layer 14. The insulating layer 18 is made of an oxide, a nitride, a carbide, an oxynitride or the like.

For example, the insulating layer 18 can eliminate the electrons generated in the P ⁺ -type diffusion layer 14 by the obliquely incident light of the pixels 2C and 2D, and enter the pixel transistor 4 of the pixel 2A to become a signal noise. Sex.

That is, the electrons generated in the P ⁺ -type diffusion layer 14 do not enter the pixel transistor 4 of the pixel 2A, so that signal noise can be reduced.

Further, by the presence of the insulating layer 18, the electrons generated in the P ⁺ -type diffusion layer 14 may return to the pixel (N ⁺ -type diffusion layer) which must be detected, so that the photodiode is also The sensitivity of the body contributes.

However, in this example, the insulating layer 18 is not disposed directly under the pixel 2A.

This is because the N ⁺ -type diffusion layer 13 constituting the photodiode is sufficiently deep to improve the sensitivity of the photodiode.

Specifically, the bottom surface of the N ⁺ -type diffusion layer 13 is formed at a position lower than the upper surface of the insulating layer 18.

Further, the N-type epitaxial growth layer 12A may be a P-type epitaxial growth layer.

As described above, according to the first example of the device configuration, the signal noise of the CMOS image sensor as the solid-state imaging device can be reduced.

Fig. 4 is a second example of the structure of the display device.

This figure is a cross-sectional view taken along line II-II of Fig. 2.

A P-type well region (P-Well) 12B is disposed in the P-type semiconductor substrate (P-sub) 11. In the P-type well region 12B, an N ⁺ -type diffusion layer 13 is disposed. The photodiode is composed of a P-type well region 12B and an N ⁺ -type diffusion layer 13.

On the P-type well region 12B, a pixel transistor 4 for reading a signal by a pixel (photodiode) 2A is disposed.

The pixel transistor 4 is composed of, for example, a read transistor 5 connected in series, a reset transistor 6, and an amplifying transistor 7. These transistors are composed, for example, of field effect transistors (FETs).

The read transistor 5 has a gate 8, the reset transistor 6 has a gate 9, and the amplifying transistor 7 has a gate 10.

The N-type diffusion layers 15, 16, 17 become the source/drain of the pixel transistor 4, respectively. Among them, the N-type diffusion layer 15 that becomes the drain of the transistor 5 is particularly referred to as a detecting portion. The N-type diffusion layer 15 as a detecting portion is electrically connected to the gate 10 of the amplifying transistor 7.

Here, in this example, the insulating layer 18 is disposed between the pixel transistor 4 and the P-type well region 12B. The insulating layer 18 is made of an oxide, a nitride, a carbide, an oxynitride or the like.

For example, the insulating layer 18 can eliminate the possibility that the electrons generated in the P-type well region 12B by the obliquely incident light of the pixels 2C and 2D enter the pixel transistor 4 of the pixel 2A to become a signal noise. .

That is, the electrons generated in the P-type well region 12B do not enter the pixel transistor 4 of the pixel 2A, so signal noise can be reduced.

Further, by the presence of the insulating layer 18, the electrons generated in the P-type well region 12B may return to the pixel (N ⁺ -type diffusion layer) which must be detected, so that the photodiode is also The sensitivity has contributed to the improvement.

However, in this example, the insulating layer 18 is not disposed directly under the pixel 2A.

This is because the N ⁺ -type diffusion layer 13 constituting the photodiode is sufficiently deep to improve the sensitivity of the photodiode.

Specifically, the bottom surface of the N ⁺ -type diffusion layer 13 is formed at a position lower than the upper surface of the insulating layer 18.

As described above, according to the second example of the device configuration, the signal noise of the CMOS image sensor as the solid-state imaging device can be reduced.

The first example and the second example may be used for both the surface illumination type CMOS image sensor and the back side illumination type CMOS image sensor.

In the surface type CMOS image sensor, the light system is incident from the side on which the pixel crystal 4 is formed. On the other hand, in the back surface type CMOS image sensor, the light system is incident on the surface opposite to the side on which the pixel crystal 4 is formed.

In the back side illumination type, light incident on the photodiode is not affected by an obstacle such as an interconnection formed on the pixel crystal 4, and therefore has a feature that the aperture ratio can be improved.

Further, in the back side illumination type, the amount of electrons generated in the P ⁺ -type diffusion layer 14 should be increased, and the present invention is particularly suitable for the back side illumination type.

2. Manufacturing method

Hereinafter, a method of manufacturing a solid-state imaging device having the device configuration of FIGS. 3 and 4 will be described.

(1) Device configuration of Figure 3

First, as shown in FIG. 5, an N-type epitaxial growth layer (semiconductor layer) 12A having a thickness of about 3 μm is formed on the P-type semiconductor substrate (P-sub) 11 by epitaxial growth.

Next, a mask material (for example, a photoresist) is formed on the N-type epitaxial growth layer 12A, and this is used as a mask, and an oxygen (O) ion is, for example, an acceleration energy of 300 KV, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ Ion implantation was performed at a dose of cm ^-2 .

Thereafter, the masking material is peeled off. When the mask material is composed of a photoresist, the photoresist is peeled off using a mixture of sulfuric acid and hydrogen peroxide water.

Next, for example, a heat treatment at a temperature of 1150 ° C for 30 minutes is performed, and the insulating layer 18 is partially formed in the N-type epitaxial growth layer 12A. The depth of the insulating layer 18 is set, for example, such that the width from the surface of the N-type epitaxial growth layer 12A to the upper surface of the insulating layer 18 is about 0.5 μm.

In this example, the insulating layer 18 is yttria. However, instead of this component, for example, nitrogen nitride or carbon ions may be implanted to form tantalum nitride, tantalum carbide or the like.

Next, an N ⁺ -type diffusion layer 13 is formed in the N-type epitaxial growth layer 12A to form a photodiode as a photoelectric conversion element.

The N ⁺ -type diffusion layer 13 is provided with a mask material (for example, a photoresist) on the N-type epitaxial growth layer 12A, and this is used as a mask to accelerate the phosphorus (P) ions, for example, at an acceleration energy of 150 kV. A dose of ×10 ¹² cm ^-2 was formed by ion implantation.

In order to increase the sensitivity of the photodiode, the bottom surface of the N ⁺ -type diffusion layer 13 is formed at a position lower than the upper surface of the insulating layer 18.

Thereafter, the masking material is peeled off. When the mask material is composed of a photoresist, the photoresist is peeled off using a mixture of sulfuric acid and hydrogen peroxide water.

Next, the P ⁺ -type diffusion layer 14 and the P-type well region 20 are formed in the N-type epitaxial growth layer 12A, and electrical separation of the photodiode as a photoelectric conversion element is performed.

The P ⁺ -type diffusion layer 14 is provided with a mask material (for example, a photoresist) on the N-type epitaxial growth layer 12A, and this is used as a mask, and the boron (B) ions are, for example, 400 KV, 800 KV, and 1200 KV, respectively. , 1600KV, 2000KV, 2400KV acceleration energy, 1 × 10 ¹² cm ^-2 dose is formed by ion implantation.

Next, as shown in FIG. 3, a pixel transistor 4 is formed on the P-type well region 20 on the insulating layer 18.

First, on the P-type well region 20, the gate 8 of the read transistor 5 is formed, the gate 9 of the transistor 6 and the gate 10 of the amplifying transistor 7 are reset.

Thereafter, a masking material (for example, a photoresist) is formed on the P-type well region 20, and the phosphorus (P) ions are accelerated by, for example, 20 KV by the gate self-alignment, 1.3 × 10 ¹² cm ^{-2 .} The dose is ion implanted into the P-well region 20.

Thereby, the pixel transistor 4 is formed on the P-type well region 20 on the insulating layer 18.

The device configuration of Fig. 3 is completed by the above steps.

(2) Device configuration of Figure 4

First, as shown in FIG. 6, a P-type well region 12B is formed in a P-type semiconductor substrate (P-sub) 11.

Next, a mask material (for example, a photoresist) is formed on the P-type well region 12B, and this is used as a mask, and the oxygen (O) ions are, for example, an acceleration energy of 300 KV, 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^- The dose of ² was ion implanted.

Thereafter, the masking material is peeled off. When the mask material is composed of a photoresist, the photoresist is peeled off using a mixture of sulfuric acid and hydrogen peroxide water.

Next, for example, heat treatment at a temperature of 1150 ° C for 30 minutes is performed, and the insulating layer 18 is partially formed in the P-type well region 12B. The depth of the insulating layer 18 is set, for example, such that the width from the surface of the P-type well region 12B to the upper surface of the insulating layer 18 is about 0.5 μm.

In this example, the insulating layer 18 is yttria. However, instead of this component, for example, nitrogen nitride or carbon ions may be implanted to form tantalum nitride, tantalum carbide or the like.

Next, an N ⁺ -type diffusion layer 13 is formed in the P-type well region 12B to form a photodiode as a photoelectric conversion element.

The N ⁺ -type diffusion layer 13 is provided with a mask material (for example, a photoresist) on the P-type well region 12B, and this is used as a mask to accelerate the phosphorus (P) ions, for example, at an acceleration energy of 150 kV, 1.3×10. The dose of ¹² cm ^-2 was formed by ion implantation.

In order to increase the sensitivity of the photodiode, the bottom surface of the N ⁺ -type diffusion layer 13 is formed at a position lower than the upper surface of the insulating layer 18.

Thereafter, the masking material is peeled off. When the mask material is composed of a photoresist, the photoresist is peeled off using a mixture of sulfuric acid and hydrogen peroxide water.

Next, as shown in FIG. 4, a pixel transistor 4 is formed on the P-type well region 12B on the insulating layer 18.

First, on the P-type well region 12B, the gate 8 of the read transistor 5 is formed, the gate 9 of the transistor 6 and the gate 10 of the amplifying transistor 7 are reset.

Thereafter, a masking material (for example, a photoresist) is formed on the P-type well region 12B, and the phosphorus (P) ions are accelerated by, for example, 20 KV by the gate self-alignment, 1.3 × 10 ¹² cm ^{-2 .} The dose is ion implanted into the P-type well region 12B.

Thereby, the pixel transistor 4 is formed on the P-type well region 12B on the insulating layer 18.

The device configuration of Fig. 4 is completed by the above steps.

3. Application examples

(1) Back-illuminated CMOS image sensor (back illuminated imager)

7 and 8 show a back side illumination type CMOS image sensor.

The device configuration of Fig. 7 corresponds to the device configuration of Fig. 3, and the device configuration of Fig. 3 corresponds to the device configuration of Fig. 4.

These device configurations are characterized in that the semiconductor substrate 11B is attached to the interlayer insulator 19 on the side where the pixel transistor 4 is formed. In this case, the semiconductor substrate 11A on the opposite side to the side on which the pixel transistor 4 is formed is honed and thinned by a chemical mechanical honing (CMP) or the like.

In the back-illuminated CMOS image sensor, light is incident from the side of the semiconductor substrate 11A. Therefore, when determining the aperture ratio, it is not necessary to consider an obstacle such as a wiring formed on the pixel transistor 4.

(2) Photographic module

Fig. 9 shows the entirety of the photographing module. Figure 10 shows the important parts of the photographic module.

Here, in the example of the CMOS image sensor (wafer) 1, the back side illumination type CMOS image sensor of FIG. 8 is used. In FIG. 10, the same elements as those in FIG. 8 are denoted by the same reference numerals.

The CMOS image sensor 1 is mounted in a package 24. The microlens 22 directs light to the CMOS image sensor 1. The color filter 20 and the planarization layer 21 are disposed between the CMOS image sensor 1 and the microlens 22.

The module lens 23 directs light to the microlens 22.

4. Variants

The solid-state imaging device according to the present invention can be applied to an image sensor such as a CCD in addition to a CMOS image sensor.

In the above example, the pixel transistor is composed of an N-channel FET, and the photodiode system is composed of a P-type semiconductor substrate and an N-type epitaxial growth layer (N ⁺ -type diffusion layer).

The solid-state imaging device according to the present invention is not limited to such a conductive type configuration, and may be applied to, for example, a conductive type device opposite thereto.

5 Conclusion

According to the present invention, signal noise of the solid-state imaging device can be reduced.

Other advantages and modifications will be apparent to those skilled in the art, and the scope of the invention is not limited to the specific details and representative embodiments shown and described herein. All modifications encompassing the scope of the invention, its sub-items, and equivalents are also included in the scope of the invention.

2A, 2B. . . Pixel (photodiode)

4. . . Pixel crystal

5. . . Reading transistor

6. . . Reset transistor

7. . . Amplifying the transistor

8,9,10. . . Gate

11. . . P-type semiconductor substrate (P-sub)

12A. . . N-type epitaxial growth layer (N-epi)

13. . . N ⁺ type diffusion layer

14. . . P ⁺ type diffusion layer

15,16,17. . . N type diffusion layer

20. . . P-well area

Figure 1 is a plan view of a CMOS image sensor.

Fig. 2 is a plan view showing in detail a part of a pixel area.

Fig. 3 is a cross-sectional view showing a first example of the structure of the apparatus.

Fig. 4 is a cross-sectional view showing a second example of the structure of the apparatus.

Fig. 5 is a cross-sectional view showing a manufacturing method.

Fig. 6 is a cross-sectional view showing a manufacturing method.

Fig. 7 is a cross-sectional view showing a back side illumination type CMOS image sensor.

Fig. 8 is a cross-sectional view showing a back side illumination type CMOS image sensor.

Fig. 9 is a view showing the entirety of the photographing module.

Fig. 10 is a view showing an important part of the photographic module.

2A. . . Pixel (photodiode)

4. . . Pixel crystal

5. . . Reading transistor

6. . . Reset transistor

7. . . Amplifying the transistor

8,9,10. . . Gate

11. . . P-type semiconductor substrate (P-sub)

12A. . . N-type epitaxial growth layer (N-epi)

13. . . N+ type diffusion layer

14. . . P+ type diffusion layer

15,16,17. . . N type diffusion layer

18. . . Insulation

20. . . P-well area

Claims (7)

A solid-state imaging device comprising: a semiconductor layer having a first conductivity type; and a second conductivity type, arranged in an array in the semiconductor layer, and each of which constitutes a plurality of diffusion layers of pixels, and is disposed in the foregoing The pixel transistor on the semiconductor layer is disposed directly under the pixel transistor, and is disposed not on the insulating layer directly under the plurality of diffusion layers, and is disposed on the semiconductor layer to cover the pixel transistor An interlayer insulating layer, a first semiconductor substrate disposed under the semiconductor substrate, and a second semiconductor substrate disposed on the interlayer insulating layer; wherein the pixel transistor is disposed on a pixel electrically connected thereto Between the pixels outside. The solid-state imaging device according to claim 1, wherein the bottom surface of the plurality of diffusion layers is disposed at a position lower than an upper surface of the insulating layer. The solid-state imaging device according to claim 1, wherein the semiconductor layer is an epitaxial growth layer on the semiconductor substrate. The solid-state imaging device of claim 1, wherein the semiconductor layer is a well region in the semiconductor substrate. A solid-state imaging device according to claim 1, wherein the light is incident on the plurality of diffusion layers from the first semiconductor substrate. A solid-state imaging device as claimed in claim 1, wherein The light system is incident on the plurality of diffusion layers from the second semiconductor substrate. A solid-state imaging device according to claim 1, wherein each of the plurality of diffusion layers has a quadrangular shape, and the pixel transistor is connected to a corner of the quadrangle.