TWI452574B - Nand flash memory device and method for speeding up erasing verification procedure - Google Patents

Description

NAND flash memory device and method capable of accelerating erase verification program

The present invention relates to a NAND flash memory device and method of operation, and more particularly to a NAND flash memory device and method that can speed up an erase verification process.

In a flash memory device, a verification operation is necessary to confirm that the charge is properly injected into the memory cell by a stylization operation. If the verification operation fails, the stylization and verification operations are repeated until the result of the verification operation is successful or a special condition is met (for example, if it is repeated 100 times).

In the erase operation, the verify operation is similarly performed to confirm that the charge is properly removed from the memory cell. The erase verification is usually performed by applying a voltage of 0 V to the memory cell. If the operation of the memory cell is normal, the page buffer of the back-end connection receives a voltage of 0 V and outputs a signal for verification.

However, once the bit line is broken due to defects in the process or other failures in the memory cell, although the memory cell whose bit line has been damaged is replaced by a redundant memory cell, the erase command ERV is erased. However, the verification process of the damaged memory unit is still performed, and the verification process is stopped after repeated verification of a certain period of time, thereby causing an excessive erasure verification time.

One of the objects of the present invention is to reduce the erase verification time.

To achieve the above and other objects, the present invention provides a NAND flash memory device capable of speeding up an erase verification process, comprising a page buffer and a memory cell array including a plurality of bit lines, the bit elements The line system receives a erase verification command, and further includes: a erase verification correction unit connected between the bit line and the page buffer, the erase verification correction unit having correspondingly connecting the bits A plurality of grounding switches of the line, the grounding switches being configured to cause the damaged bit lines in the bit lines to be connected to the ground voltage upon receiving the erase verifying command.

To achieve the above and other objects, the present invention provides a method for accelerating an erase verification program for a NAND flash memory device, the NAND flash memory device including a page buffer and a plurality of bit lines a memory cell array, the method comprising: obtaining an address of a damaged bit line in the memory cell array; connecting an erase verifying correction unit between the bit line and the page buffer, and erasing the bit line Verifying that the plurality of grounding switches in the correction unit are correspondingly connected to the bit line; and setting the grounding switches according to the address, so that when the erasing verification correction unit receives a wiping verification instruction, the connection is broken The grounding switch of the bit line is connected to the ground voltage.

In one embodiment, the grounding switches are set to receive the erase verify command, and the remaining uncorrupted bit lines are also connected to the ground voltage.

In an embodiment, when the erase verifying unit receives the erase verify command, the ground switch connected to the remaining bit lines is also connected to the ground voltage.

Thereby, the present invention arranges the special line of the damaged bit line so that when the erase verification process is performed, the erase verification unit can simultaneously output a predetermined voltage signal to the page buffer, so that the page buffer The device will consider that the damaged bit line has been verified by erasure, which greatly saves the repeated verification time consumed by the prior art.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings.

First, please refer to FIG. 1 , which is a circuit block diagram of the NAND flash memory device in the embodiment of the present invention in the erase verify state. The memory array 100 of FIG. 1 is exemplified by three NAND strings. In this example, each NAND string 400 includes a string of selection transistors ST1, a selection transistor ST2, and three memory cells MC. .

The memory cell array 100 includes a plurality of memory cells MC connected in series between a bit line (BL0, BL1 or BL2) and a ground select line (GSL). The memory cell MC in series with the bit line (BL0, BL1 or BL2), the string selection transistor ST1 and the ground selection transistor ST2 is referred to as a NAND string 400. The string selection transistor ST1 and the ground selection transistor ST2 are used to select a memory cell MC for operation, and the turn-on or turn-off of the string selection transistor ST1 is selected by a string. The state of the line SSL (string select line) is determined. The string selection transistor ST1 is selectively switched to couple the associated memory cell strings and bit lines. The ground selection transistor ST2 is selectively switched to control the electrical connection between each NAND string 400 and a common source line (not shown). In Figure 1, the common source line is grounded in response to the erased state of the NAND string, and therefore, in the erased state, each string of NAND strings 400 should be connected to a ground voltage.

As shown in FIG. 1, one bit line and one NAND string 400 constitute a column of the memory cell array 100. The word lines (WL0, WL1, and WL2) are the rows of the memory array 100. Each word line connects the control gate of each memory cell MC in each column.

When the bit line connected to the NAND string 400 in the memory array 100 is damaged, as in the damaged area BA shown in FIG. 1, the erase command causes each string of the NAND string 400 to be connected to the ground voltage, however, The NAND string corrupted by the line will not be able to pass the ground voltage signal that was passed during the subsequent erase verification to the page buffer 200. Thus, under the prior art, the page buffer 200 will not be able to send the pass signal of the ERV (ie, the buffer 200 has received the ground voltage signal of the NAND string), and the verification program will repeat on the damaged bit line. Verify the ground.

Based on this, in the embodiment, an erase verification correction unit 300 is further added, which is a hardware block, and includes a plurality of grounding switches GSW, and the grounding relationship acts as a logic gate. Since each memory array is tested for the function of the memory cell at the completion of the production, and replaced by redundant memory cells when the memory cell is erroneous or damaged, the address of the damaged memory cell is thus Can be easily obtained.

Therefore, in this embodiment, the correction of the erasure verification is performed based on the error or the address of the memory cell obtained at the time of completion of the production. The erase verification correction unit 300 is connected between the bit lines (BL0, BL1, BL2) and the page buffer 200, and each bit line is correspondingly connected to a ground switch GSW. The grounding switch GSW is configured to connect the grounding switch GSW corresponding to the damaged bit line to the ground voltage based on the wrong or damaged memory cell address to receive the erase verifying command ERV. . In turn, the page buffer 200 will consider that the damaged bit line has been verified by erasing, thereby greatly reducing the repetitive verification time consumed by the prior art.

The remaining normal bit lines can pass the grounding voltage of the NAND string in the erase state by itself, so that the grounding switch GSW connected to the normal bit line can be not specially modified. However, in an embodiment, the grounding switch GSW connected to the normal bit line may be set to connect the corresponding grounding switch GSW to the ground voltage when receiving the erasing verification command ERV.

The foregoing function of the erase verification correction unit 300 and the grounding switches GSW can easily achieve the foregoing functional actions by various logic gates or other equivalent components, which can be easily accomplished by those skilled in the art. Therefore, the configuration of each logical operation element in the erase verification unit 300 will not be described here.

Next, please refer to FIG. 2, which is a flowchart of a method for accelerating the erase verification program of the NAND flash memory device in the embodiment of the present invention.

The NAND flash memory device includes a page buffer and a memory cell array including a plurality of bit lines. The method for accelerating the erase verifying process includes: (S1) obtaining the damaged bit line in the memory cell array. Address (S2) connecting a erase verification correction unit between the bit line and the page buffer, and causing the plurality of ground switches in the erase verification correction unit to be correspondingly connected to the bit line; S3) According to the address, the grounding switches are set to connect the grounding switch connected to the damaged bit line to the grounding voltage when the erasing verification correction unit receives a erasing verification command.

In the embodiment of the present invention, a damaged bit line is taken as an example. In actual implementation, an erase verifying correction unit with different driving capabilities may be selected according to the bit line damage condition of the memory array. For example, when the memory array has a corresponding In the case of 50 corrupted bit lines of 50 strings of NAND, the erase verification correction unit must be serially connected between 50 bit lines and at least one page buffer, and the erase verification correction unit must also have the capability to provide 50 respectively. The group presets the voltage signal into the at least one page buffer.

In summary, the present invention provides a special circuit arrangement for the damaged bit line, so that when the erase verification process is performed, the erase verification unit can simultaneously output a predetermined voltage signal to the page buffer, so that the The page buffer will consider that the corrupted bit line has been verified by erasure, which greatly saves the repetitive verification time consumed by the prior art.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application.

100. . . Memory array

200. . . Page buffer

300. . . Erase verification correction unit

400. . . NAND string

BA. . . Damaged area

BL0~2. . . Bit line

ERV. . . Erase verification instruction

MC. . . Memory cell

SSL. . . String selection line

GSL. . . Ground selection line

GSW. . . Grounding switch

ST1. . . String selection transistor

ST2. . . Ground crystal

S1~S3. . . step

WL0~3. . . Word line

FIG. 1 is a circuit block diagram of a NAND flash memory device in an embodiment of the present invention.

2 is a flow chart of a method for accelerating an erase verification program of a NAND flash memory device in an embodiment of the present invention.

100. . . Memory array

200. . . Page buffer

300. . . Erase verification correction unit

400. . . NAND string

BA. . . Damaged area

BL0~2. . . Bit line

ERV. . . Erase verification instruction

MC. . . Memory cell

SSL. . . String selection line

GSL. . . Ground selection line

GSW. . . Grounding switch

ST1. . . String selection transistor

ST2. . . Ground crystal

WL0~2. . . Word line

Claims (4)

A NAND flash memory device capable of speeding up an erase verification program, comprising a page buffer and a memory cell array including a plurality of bit lines, the bit line system receiving a erase verify command, wherein The method further includes: a wipe verification correction unit connected between the bit line and the page buffer, the erase verification correction unit having a plurality of ground switches correspondingly connected to the bit lines, the ground switches It is set to connect the damaged bit line in the bit line to the ground voltage when receiving the erase verify command. The NAND flash memory device of claim 1, wherein the grounding switches are set to receive the erase verifying command, and the remaining uncorrupted bit lines are also connected to the ground voltage. A method for accelerating an erase verification program of a NAND flash memory device, the NAND flash memory device comprising a page buffer and a memory cell array including a plurality of bit lines, the method comprising: obtaining the memory cell An address of the damaged bit line in the array; a wipe verification correction unit is connected between the bit line and the page buffer, and the plurality of ground switches in the erase verification correction unit are correspondingly connected And the grounding line is set according to the address, so that when the erasing verification correction unit receives a erase verification command, the grounding switch connected to the damaged bit line is connected to the ground voltage. The method of claim 3, wherein when the erase verifying unit receives the erase verify command, the ground switch connected to the remaining bit lines is also connected to the ground voltage.