TWI451689B - Class D audio amplifiers and methods - Google Patents

Description

Class D audio amplifier and method

This invention relates to analog integrated circuits, and more particularly to class D power amplifiers.

In recent years, Class D amplifiers have been widely used in audio equipment. Class D amplifiers offer the advantages of high efficiency and compactness, reducing heat and power requirements. The class D power amplifier works by converting an analog or digital audio signal into a high frequency pulse width modulation (PWM) signal and then driving the power MOSFET with the generated PWM signal, which either constitutes a half bridge topology or constitutes a full Bridge topology. Finally, a passive low-pass filter is used to convert the output signal of the power MOSFET into a low-frequency analog waveform signal suitable for the audio speaker.

The implementation of the above class D amplifier is relatively simple. However, to produce high-quality audio signals, these amplifiers have a number of issues worthy of attention. One of the main problems is that the output analog signal is degraded due to power noise and non-ideal output stages.

For a half-bridge topology, since there is essentially a single-ended structure, there is no common-mode rejection and all noise from the amplifier supply is directly coupled to the output. This undesirable effect is exacerbated by digital Class D amplifiers, where the power MOSFET is switched between the power supply and the output, and the power supply is also used as a voltage reference. Therefore, the power supply rejection ratio (PSRR) of a half-bridge Class D amplifier is unacceptable without the addition of a noise cancellation structure. Unlike half-bridge topologies, full-bridge Class D amplifiers have sufficient common-mode rejection, the same power supply, and differential outputs that eliminate the effects of power-supply noise at the output. However, full-bridge Class D amplifiers are still subject to power transients that are caused by changes in the load that cause DC power to change. Moreover, non-ideal power MOSFETs and mismatches in the switching circuit also reduce the PSRR performance of the full-bridge topology.

Another method of suppressing noise commonly used in Class D audio amplifiers is the sigma delta modulator structure. The sigma delta modulator changes the noise to a high frequency and then uses a low pass filter to only output the audio analog signal. 1 is a schematic diagram of a prior art class D amplifier 100 showing the use of a sigma delta modulator structure to improve noise rejection. The existing class D amplifier 100 receives an analog input signal (Vin) at the input terminal 101. The sigma delta modulator includes an adder circuit 102, an integrator 103 coupled to the comparator 104, and a latch 105 that will feedback the output signal and the analog input signal (Vin) The difference is transformed into a bit signal stream that reflects the quantized noise spike applied to the original analog input signal (Vin). The switch circuit 107 includes a high side MOSFET transistor 107_1 and a low side MOSFET transistor 107_2. The two transistors operate in an alternate conduction mode to pulse modulate the bit signal stream. In order to regain the original PWM input signal (Vin), a simple LC low-pass filter 109 is used to filter out the noise spikes that have been modulated into high frequencies. However, this technique is flawed for PWM input because the output frequency is not directly controlled and can be affected by component variations. Moreover, the existing Class D audio amplifier has no correction for the distortion caused by the non-ideal power MOSFET transistors 107_1, 107_2 and the integrator 103. The time constant of the integrator 103 may affect the switching rate of the switching circuit 107. Moreover, the inductor current at the output of the switching circuit 107 inadvertently extends or shortens the pulse width of the drive control signal.

The present invention provides a high performance Class D audio amplifier circuit that effectively eliminates noise and distortion. The class D amplifier disclosed in the present invention comprises: a modulator circuit for receiving a PWM input signal and generating a control signal, driving a control circuit, a switching circuit and a feedback circuit. The drive control circuit generates a drive control signal to the switch circuit. The drive control signal includes a compensation signal for noise and distortion in the output signal, and the compensation signal is implemented by selecting a first pulse signal or a second pulse signal in each cycle based on information of the control signal.

The invention also discloses a method for reducing signal distortion in a class D audio amplifier, the method comprising: providing an output feedback signal, quantizing a difference signal of the output feedback signal and the input signal and obtaining a control signal; and modulating the output based on the control signal The duty cycle of the signal compensates for the output signal at the end of each cycle.

The present invention adopts the above structure and/or method, and can effectively eliminate noise by filtering the output signal and obtaining a control signal based thereon, filtering out the noise spike modulated into high frequency, and adjusting the duty cycle of the output signal. And distortion to get higher quality audio output.

In order to provide a thorough understanding of the present invention, numerous details are provided in the following description. However, it will be apparent to those skilled in the art that these specific details are not required to practice the invention. It is to be understood that the invention and the specific embodiments are intended to clarify the practical application of the technical solutions provided by the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art can make various modifications, equivalent substitutions or improvements within the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. In order to avoid obscuring the present invention, some well-known methods related to implementation are not specifically described.

2 shows a block diagram of a class D audio amplifier 200 in accordance with one embodiment of the present invention. Class D audio amplifier 200 receives pulse width modulated input signal PWM _IN and converts it to a PWM input current signal through first resistor 202. The PWM output signal PWM _OUT is converted to a PWM output current signal by the second resistor 210. The PWM output current signal is fed back to the input terminal 201 via the feedback circuit 209. The subtractor 203 subtracts the PWM output current signal from the PWM input current signal. The resulting difference signal PWM _Δ includes a noise spike and a PWM input signal, and the difference signal is transmitted to the integrator 204 so that the average value PWMa of the difference signal can be estimated. Then, the difference signal average value PWMa is quantized by the comparator 205 to obtain a control signal PWMq. Those skilled in the art will appreciate that 205 herein may be a multi-stage circuit and should not be limited to a comparator. The comparator 205 compares the difference signal average value PWMa with the first reference voltage V _FEF+ and the second reference voltage V _FEF- . The noise spike is quantized to a logic high signal or a logic low signal only when the noise spike exceeds these two reference values. In other words, undesired noise spikes are modulated into high frequencies. The drive control circuit 206 receives the control signal PWMq and modulates the width of each pulse based on the information of the PWM input current signal to compensate for the distortion caused by the non-ideal switching circuit 207 of the subsequent stage. According to one embodiment, the drive control circuit 206 selects a pulse signal that is longer or shorter, the width of the pulse signal being determined by the stretch distortion of the pulse, and the stretch distortion of the pulse being caused by the components of the switch circuit 207. The PWM output signal PWM _{OUT is} input to the low pass filter 211, and the low pass filter 211 filters out the noise signal leaving only the desired audio signal V _OUT . Moreover, in accordance with an embodiment of the present invention, all distortion of the PWM output signal PWM _OUT will be corrected by the drive control circuit 206. Finally, the output of the low pass filter 211 is connected to the audio speaker 212. Those skilled in the art will appreciate that for inductive loads, i.e., inductive speakers, low pass filter 211 is not required.

3 is a block diagram of one embodiment of a class D audio amplifier 300, including the structure of a drive control circuit in accordance with one embodiment of the present invention. Class D audio amplifier 300 includes a PWM input terminal 301 that receives a PWM input signal PWM _IN . Next, the potential shift circuit 302 is connected to the PWM input terminal 301 to convert the PWM input signal into the signal level of the power MOSFET transistor in the switch circuit 320. The output of potential offset circuit 302 is then coupled to a modulator circuit 303 which also receives a PWM output signal PWM _OUT . In one embodiment, the output of the potential offset circuit 302 and the PWM output signal PWM _{OUT are} first converted to a current signal to determine the difference between the two. The output of the modulator circuit 303 is passed to the drive control circuit 310. The output of drive control circuit 310 in turn drives switch circuit 320.

As shown in FIG. 3, in one embodiment, the drive control circuit 310 includes a delay circuit 311, a first pulse width modulation circuit 312, a second pulse width modulation circuit 313, a multiplexer 314, and a latch. 316 and selector circuit of inverter 315. The delay circuit 311 receives the PWM input signal PWM _IN and generates a delay signal PWM _dly . Next, the delay signal PWM _{dly is} coupled to the first pulse width modulation circuit 312 and the second pulse width modulation circuit 313, respectively. The PWM input signal PWM _{IN is} also coupled to the first pulse width modulation circuit 312 and the second pulse width modulation circuit 313, respectively. A first PWM circuit 312 outputs a second PWM _L and the pulse width modulation circuit 313 is coupled to the output of multiplexer 314 PWM _S. The input terminal of the latch 316 receives the control signal PWMq output from the modulator circuit 303, the clock terminal of the latch 316 is connected to the output of the inverter 315, and the input of the inverter 315 is connected to the output of the delay circuit 311. PWM _dly . The operation of the class D audio amplifier 300 including the drive control circuit 310 will be described in detail in FIGS. 5 and 6.

4 is a schematic diagram of a drive control circuit 400 in accordance with one embodiment of the present invention. Structurally, the drive control circuit 400 includes a delay circuit 402 coupled to the input 401 for receiving a pulse width modulated input signal PWM _IN . The output of delay circuit 402 is coupled to a (NAND) gate 403 and a reverse (NOR) gate 404. In the present embodiment, the inverse gate 403 is an example of the first pulse width modulation circuit 312 of FIG. 3, and the inverse gate 404 is an example of the second pulse width modulation circuit 313 of FIG. The other input of the anti-gate 403 and the anti-gate 404 is coupled to the input 401. The output of the inverse OR gate 404 is coupled to the multiplexer 405. The output 409 outputs an output signal PWM _{S of the} inverse gate 403 or an output signal PWM _{L of the} inverse gate 404, the selection of which is based on a command coupled to the latch 407 of the inverter 408. In one embodiment, latch 407 is a D flip-flop.

The D input of the D flip-flop 407 is connected to the terminal 406 and receives the control signal PWMq output by the modulator circuit 303. The Q outputs of the D flip-flop 407 are coupled to the input of the inverter 408 and the second select of the multiplexer 405, respectively. The output of inverter 408 is coupled to a first select terminal of multiplexer 405. In one embodiment as shown in FIG. 4, the multiplexer 405 includes a first inverter 405_1 and a second inverter 405_2.

In accordance with the teachings of one embodiment of the present invention, FIG. 5 shows a signal diagram 500 (also a signal timing diagram) of the PWM signal that drives control circuit 400. Graph 501 represents the PWM input signal PWM _IN received at input 401. As shown, PWM input signal PWM _IN 501 is a pulse width modulated signal having a variable pulse width. Graph 502 represents the output signal PWM _dly of delay circuit 402. As can be seen from graph 502, the delayed signal PWM _dly is the PWM input signal PWM _IN is delayed by δ time. In one embodiment, the delay value δ is rigorously selected to be greater than the equivalent pulse width of the maximum difference between the desired PWM output signal PWM _OUT and the distorted PWM output signal. Otherwise, the feedback loop 209 cannot correct the distorted PWM output signal PWM _OUT in the worst case. Next, graph 504 represents the output signal PWM _{S of} the inverse gate 403. As shown in FIG. 4, the inverse gate 403 receives the PWM input signal PWM _IN at the first input and the delayed PWM input signal PWM _dly at the second input. As long as the input signal is low, the output signal PWM _S goes high. Graph 503, on the other hand, represents the output signal PWM _{L of} the inverse OR gate 404.

Naturally, the output signal PWM _L goes high only when the input signal goes low. Finally, chart 505 shows the drive control signal PWM _DR of multiplexer 405. In one embodiment, the clock signal of the D flip-flop 407 is the output signal PWM _S of the inverse gate 403. Whenever the output signal PWM _S goes low, the D flip-flop 407 latches a shortened PWM signal PWM _S or an extended PWM signal PWM _L .

Returning to FIGS. 2, 4 and 5, the PWM input signal PWM _IN is a desired signal input from the input terminal 201, and the delay signal PWM _{dly is} input to the inverse gate 403 and the inverse gate 404, respectively. The final output signal is a pulse width modulation signal PWM _S with a pulse width shortened at the output of the gate 403, and/or a pulse width modulation signal PWM _L with a pulse width extension at the output of the NAND gate 404. Each cycle, determined by the control signal output by the comparator 205, selects one of the two PWM signals (PWM _L and PWM _S ) to be transferred to the gates of the MOSFET transistors 207_1 and 207_2. For example, at the end of one cycle, the output of comparator 205 goes high, meaning that the average voltage value of the distorted PWM output signal PWM _OUT is less than the average voltage value of the desired PWM input signal PWM _IN . Therefore, the pulse width of the PWM output signal PWM _OUT is undesirably shortened. In order to correct this distorted PWM output signal PWM _OUT , a PWM signal PWM _L longer than the desired PWM input signal PWM _IN pulse width is required to be transferred to the gates of the MOSFET transistors 207_1 and 207_2; thus passing through the D flip-flop 407 The "high" control signal selects the signal PWM _L at the output of the inverse OR gate 404 such that in the next cycle, a PWM signal PWM _{L that} is longer than the desired PWM input signal PWM _IN pulse width is transferred to the MOSFET transistor 207_1 And the gate of 207_2.

On the other hand, if the control signal goes low, it means that the average voltage value of the distorted PWM output signal PWM _OUT is greater than the average voltage value of the desired PWM input signal PWM _IN . Thus, the pulse width of the PWM output signal PWM _OUT is undesirably extended. Therefore, a PWM signal PWM _S having a narrower pulse width at the output of the inverse gate 403 is selected to compensate for the difference between the desired PWM input signal PWM _IN and the distorted PWM output signal PWM _OUT .

As shown in Figure 6, a series of graphs 600 illustrate the operation of the Class D audio amplifier of Figure 4. Graph 601 again shows the PWM input signal PWM _IN at terminal 301. Next, graph 602 represents the drive control signal PWM _{DR at the} output of multiplexer 314. As shown in graph 602, the falling edge of each pulse is either elongated or shortened. In particular, the falling edge of the first pulse 602_V is lengthened, and then the falling edge of the second pulse 602_W is shortened. Similarly, the falling edge of the third pulse 602_X is shortened, and the falling edge of the fourth pulse 602_Y is extended. The cause of the delay may be due to the limited, non-linear rise time of the power components in the switch circuit 320, and/or linear or non-linear delays in the system. The turn-on time of the power component in the switch circuit 320, and/or the reverse recovery time of the body diode, etc., may cause an error in the nonlinear rise time.

As shown in FIG. 6, chart 603 represents the corresponding pulse generated at the output of each pulse at the input of switching circuit 320. Pulse 603_V has a small negative error at the rising edge. Obviously, the PWM output signal PWM _OUT can be changed until the drive control signal PWM _DR changes, so there is a delay. These undesired delays can cause the high side power MOSFET transistor 207_1 and the low side MOSFET transistor 207_2 to turn "on" or "off" slowly. Therefore, the transient inductor current I _L in the low pass filter 211 will cause a pulse width distortion of the drive control signal PWM _DR . The inductor current I _L flowing to input terminal 201 will result in an undesirable extension of the PWM output pulse width of the PWM _OUT signal. Otherwise, the inductor current I _L flowing to the output filter 211 will result in an undesirable shortening of the PWM output pulse width of the PWM _OUT signal. Thus, graph 604 shows the difference signal PWM _Δ containing the PWM output signal PWM _OUT distortion. Graph 605 represents the average difference signal after integrator 204. Finally, graph 606 shows the audio output signal _VOUT output by low pass filter 211. The noise spike is filtered by the low pass filter 211, and after the pulse width distortion is compensated by the drive control circuit 206, a graph 606 is obtained.

As shown in FIG. 7, a flow chart depicts a method 700 of providing a Class D audio amplifier low distortion signal. The method 700 includes providing an output feedback signal, quantizing the output feedback signal and the difference signal of the input signal to obtain a control signal; and based on the control signal, compensating the output signal at the end of each cycle by modulating the duty cycle of the output signal.

In particular, step 701 provides an output feedback signal. In one embodiment, step 701 further includes converting the pulse width modulation input signal PWM _IN into an input current signal, and converting the PWM output signal PWM _{OUT of the} switching circuit into a second output current signal. The second output current signal is then fed back to the subtractor, which subtracts the second output current signal from the input current signal. Step 701 is implemented by a feedback path 209, a first resistor 202, and a subtractor 203.

Next, in step 702, the difference between the output feedback signal and the input signal is quantized to obtain a control signal. Step 702 is implemented by the integrator 204 connected between the subtractor 203 and the comparator 205 in FIG. The control signal is selected either by a longer pulse signal or a shorter pulse signal to drive the switching circuit 207.

Finally, in step 703, the pulse width of the drive control signal for driving the switch circuit is modulated by a control signal every cycle. In particular, when the PWM output signal is shortened, the control signal selects a longer pulse. On the other hand, when the PWM output signal is extended by the power MOSFET transistors 207_1 and 207_2, the control signal selects a shorter pulse. Step 703 is implemented by driving control circuit 310 and class D audio amplifier 300. In one embodiment, step 703 is implemented by the drive control circuit 400 of FIG. 4 of the present invention.

Variations and modifications of the disclosed embodiments are possible, and other possible alternative embodiments and equivalent variations to the elements of the embodiments will be apparent to those of ordinary skill in the art. It is to be understood that the invention and the embodiments of the invention are intended to illustrate the practical application of the technical solutions provided by the present invention and should not be construed as limiting the scope of the invention. Those skilled in the art can make various modifications, equivalent substitutions, or improvements within the spirit and scope of the invention. Other variations and modifications of the disclosed embodiments of the invention do not depart from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Class D amplifier

101. . . Input terminal

102. . . Addition circuit

103. . . Integrator

104. . . Comparators

105. . . Latches

106. . . Gate drive

107. . . Switch circuit

107_1. . . High-end MOSFET transistor

107_2. . . Low-side MOSFET transistor

109. . . LC low pass filter

200. . . Class D audio amplifier

201. . . Input

202. . . First resistance

203. . . Subtractor

204. . . Integrator

205. . . Comparators

206. . . Drive control circuit

207. . . Switch circuit

211. . . Low pass filter

212. . . Audio speaker

300. . . Class D audio amplifier

301. . . PWM input terminal

302. . . Potential offset circuit

303. . . Modulator circuit

310. . . Drive control circuit

311. . . Delay circuit

312. . . First pulse width modulation circuit

313. . . Second pulse width modulation circuit

314. . . Multiplexer

315. . . inverter

316. . . Latches

320. . . Switch circuit

400. . . Drive control circuit

401. . . Input

402. . . Delay circuit

403. . . NAND gate

404. . . Reverse or (NOR) gate

405. . . Multiplexer

405_1. . . First inverter

405_2. . . Second inverter

406. . . terminal

407. . . D flip-flop

408. . . inverter

409. . . Output

500. . . Signal diagram

600. . . chart

The present invention has been described in detail by means of embodiments and is not limited to the accompanying drawings.

Figure 1 shows a block diagram of a prior art Class D audio amplifier employing a sigma delta modulator topology to suppress unwanted noise.

2 shows a block diagram of a class D audio amplifier having a drive control circuit that provides a compensated drive signal in accordance with one embodiment of the present invention.

3 shows a block diagram of a drive control circuit including a first pulse width modulation circuit and a second pulse width modulation circuit in accordance with one embodiment of the present invention.

Figure 4 shows a schematic diagram of one embodiment of a drive control circuit of the present invention.

Figure 5 is a timing diagram showing the operation of the drive control signal shown in Figure 4, in accordance with one embodiment of the present invention.

Figure 6 is a timing diagram showing the operation of the Class D audio amplifier circuit of Figure 2, in accordance with one embodiment of the present invention.

7 shows a flow chart of a method of implementing a high quality audio signal in a class D audio amplifier in accordance with one embodiment of the present invention.

200. . . Class D audio amplifier

201. . . Input

202. . . First resistance

203. . . Subtractor

204. . . Integrator

205. . . Comparators

206. . . Drive control circuit

207. . . Switch circuit

211. . . Low pass filter

212. . . Audio speaker

Claims (21)

A class D audio amplifier includes: a modulator circuit that receives a pulse width modulated PWM input signal and a PWM output signal feedback signal to provide a control signal; a drive control circuit electrically coupled to the modulator circuit to generate drive control a signal, the drive control circuit compensates the PWM output signal by selecting the first pulse signal or the second pulse signal in each cycle based on the control signal; the switch circuit is electrically coupled to the drive control circuit, and is switched in response to the drive control signal Turning on and off of the switch to generate the PWM output signal; the feedback circuit is electrically coupled to the switch circuit and the modulator circuit, receiving the PWM output signal, providing a feedback signal of the PWM output signal; and wherein the driving control The circuit includes: a delay circuit that receives the PWM input signal; a first pulse width modulation circuit electrically coupled to the delay circuit to generate a first pulse signal having a pulse width longer than a pulse width of the PWM output signal; a pulse width modulation circuit electrically coupled to the delay circuit to generate a pulse width pulse of the PWM output signal a second pulse signal having a shorter width; a multiplexer electrically coupled to the first pulse width modulation circuit and the second pulse width modulation circuit, and selecting the first pulse signal or The second pulse signal; a selector circuit electrically coupled to the multiplexer and the modulator circuit, based on the control signal, controlling the multiplexer circuit selection or the first pulse signal or the second pulse signal. A class D audio amplifier as claimed in claim 1, wherein the modulator circuit provides the control signal by quantizing an average difference between the PWM input signal and a feedback signal of the PWM output signal. For example, the class D audio amplifier of claim 1 further includes: an input end electrically coupled to the modulator circuit to receive the PWM input signal; and an output end electrically coupled to the switch circuit to output an analog audio signal . The class D audio amplifier of claim 1, further comprising: an output filter electrically coupled to the switch circuit to generate the analog audio signal in response to the PWM output signal. For example, the class D audio amplifier of claim 1 further includes: a first converter electrically coupled to the modulator circuit, converting the PWM input signal into a PWM input current signal; and a second converter, an electrical coupling The switch circuit is connected to convert the PWM output signal into a PWM output current signal. A class D audio amplifier as claimed in claim 4, wherein The first converter further includes a first resistor, and the second converter further includes a second resistor. The class D audio amplifier of claim 3, further comprising: a potential offset circuit electrically coupled between the input terminal and the modulator circuit. The class D audio amplifier of claim 1, wherein the selector circuit further comprises: an inverter electrically coupled to the delay circuit; and a flip-flop circuit electrically coupled to the inverter and multiplexer And modulator circuit. For example, in the class D audio amplifier of claim 8, the input end of the inverter is coupled to the delay circuit, and the output end thereof is coupled to the clock terminal of the flip-flop circuit; the D input terminal of the flip-flop circuit is coupled Connected to the output of the modulator circuit, the Q output is coupled to the multiplexer. A class D audio amplifier as claimed in claim 1, wherein the first pulse width modulation circuit further comprises an inverse OR circuit. A class D audio amplifier according to claim 1, wherein the second pulse width modulation circuit further comprises a reverse circuit. A class D audio amplifier as claimed in claim 1, wherein the switch circuit further comprises a plurality of MOSFET transistors electrically connected together in a half bridge topology. A class D audio amplifier as claimed in claim 12, wherein the plurality of MOSFET transistors further includes a high side MOSFET component and a low side a MOSFET component, the high-side MOSFET component and the low-side MOSFET component are coupled in series, the gate of the high-side MOSFET component is electrically coupled to the driving control circuit, and the drain is electrically coupled to the first supply voltage, and the source is electrically coupled To the drain of the low side MOSFET device, the gate of the low side MOSFET component is electrically coupled to the drive control circuit, the source of which is electrically coupled to the second supply voltage. A class D audio amplifier as claimed in claim 1, wherein the switch circuit further comprises a plurality of MOSFET transistors electrically connected together in a full bridge topology. The class D audio amplifier of claim 14, wherein the switch circuit further comprises: a first high-side MOSFET component, the gate of which is electrically coupled to the driving control circuit, the drain of which is electrically coupled to the first supply voltage; a first low side MOSFET device, a source of the first high side MOSFET device is electrically coupled to a drain of the first low side MOSFET device, and a gate of the first low side MOSFET device is electrically coupled to the driving control circuit, The source is electrically coupled to the second supply voltage; the second high-side MOSFET component has a gate electrically coupled to the drive control circuit, a drain electrically coupled to the first supply voltage; and a second low-side MOSFET component The source of the second high-side MOSFET device is electrically coupled to the drain of the second low-side MOSFET device, and the gate of the second low-side MOSFET device is electrically coupled to the driving control circuit, and the source thereof is electrically coupled To the second supply voltage. For example, a class D audio amplifier of the third application patent scope, wherein The modulator circuit further includes a subtractor electrically coupled to the input terminal and the feedback circuit, an integrator electrically coupled to the subtractor, and a comparator electrically coupled to the integrator. A method for generating an analog signal, comprising: providing an output feedback signal; quantizing a difference between the output feedback signal and the input signal to obtain a control signal; modifying a duty cycle of the output signal based on the control signal; and modulating the output signal therein The duty cycle further includes: selecting a preset delay value for the input signal; delaying the input signal by the preset delay value to generate the first pulse signal and the second pulse signal; and selecting the first pulse signal or the second pulse signal . The method of claim 17, wherein the modulating the output signal duty cycle further comprises determining, by the control signal, the first pulse signal or the second pulse signal. The method of claim 17, further comprising filtering the output signal to generate an audio analog signal. The method of claim 17, wherein providing the output feedback signal further comprises converting the input signal into an input current signal, the output signal being converted to an output current signal. The method of claim 17, wherein the difference between the quantized output feedback signal and the input signal further comprises: And subtracting the output feedback signal from the input signal to obtain a difference signal; integrating the difference signal to obtain an average signal; and comparing the average signal with the first reference signal and the second reference signal to obtain the control signal.