TWI451560B - Electrostatic discharge protection device - Google Patents

Description

Electrostatic discharge protection device

This invention relates to a protective device and, more particularly, to an electrostatic discharge protection device.

Electrostatic discharge (ESD) is a phenomenon of electrostatic movement from a non-conductive surface, which causes damage to the semiconductor in the integrated circuit. For example, a conventional charged body such as a machine that houses an integrated circuit or an instrument that tests an integrated circuit will discharge to the wafer when it contacts the wafer, and the instantaneous power of the electrostatic discharge may cause damage to the integrated circuit in the wafer.

In order to prevent the integrated circuit from being damaged by the external electrostatic effect, the design of the electrostatic discharge protection device is added to the integrated circuit. In the silicide process, a common electrostatic discharge protection device is provided with a silicide block on the drain of the N-type transistor, so that the N-type transistor has a uniform opening when an electrostatic discharge event occurs. Uniform turn-on, which provides a more complete discharge path. However, the additional placement of the telluride barrier increases process complexity and production costs.

In order to improve the above disadvantages, most of the existing electrostatic discharge protection devices have removed the arrangement of the telluride blocking layer and used a control circuit to control the N-type transistor. However, the electrostatic discharge protection device of this architecture must have a good control circuit to turn on the N-type transistor in a timely manner. In addition, existing control circuits are often susceptible to noise, which in turn causes electrostatic discharge Malfunction of the protection device.

The invention provides an electrostatic discharge protection device, wherein a control circuit uses two power supply voltages from different power supply lines to control the clamping unit, thereby increasing the anti-noise capability of the electrostatic discharge protection device.

The present invention provides an electrostatic discharge protection device that receives two supply voltages from different power supply wirings and operates the control circuit using two supply voltages. Thereby, the anti-noise capability of the ESD protection device can be improved.

The invention provides an electrostatic discharge protection device comprising a clamping unit and a control circuit. The clamping unit provides a discharge path from the first power wiring to the first ground wiring. The control circuit receives the first power supply voltage from the first power supply wiring and the second power supply voltage from the second power supply wiring. Wherein, when the first power voltage and the second power voltage are supplied, the control circuit generates an isolation signal to cut off the discharge path. In addition, when the first power voltage and the second power voltage are not supplied, the control circuit generates a trigger signal by using an electrostatic signal from the first power wiring to turn on the discharge path.

In an embodiment of the invention, the control circuit includes a trigger unit and a latch unit. The trigger unit is electrically connected to the first power wiring, the second power voltage, and the first ground wiring. In addition, the trigger unit generates a first control signal according to the first power voltage and the second power voltage, and generates a second control signal according to the static signal. The latch unit is electrically connected to the first power wiring and the first ground wiring. In addition, the latch unit generates the isolation signal according to the first control signal, and the latch unit generates the trigger signal according to the second control signal.

In an embodiment of the invention, the trigger unit includes a first P-type transistor, a resistor, and a first inverter. The source of the first P-type transistor is electrically connected to the first power supply wiring, and the gate of the first P-type transistor is electrically connected to the second power supply wiring. The first end of the resistor is electrically connected to the drain of the first P-type transistor, and the second end of the resistor is electrically connected to the first ground wiring. The input end of the first inverter is electrically connected to the first end of the resistor, and the output end of the first inverter outputs the first control signal or the second control signal.

In an embodiment of the invention, the latch unit includes a second P-type transistor, a second inverter, and a first N-type transistor. The source of the second P-type transistor is electrically connected to the second power supply wiring, and the drain of the second P-type transistor generates an isolation signal or a trigger signal. The input end of the second inverter is electrically connected to the drain of the second P-type transistor, and the output end of the second inverter is electrically connected to the gate of the second P-type transistor. The source of the first N-type transistor is electrically connected to the first ground wiring, the drain of the first N-type transistor is electrically connected to the drain of the second P-type transistor, and the gate of the first N-type transistor is received. A control signal or a second control signal.

The invention provides an electrostatic discharge protection device comprising a control circuit and a clamping unit. The control circuit electrically connects the first power wiring, the second power wiring, and the first ground wiring. The clamping unit provides a discharge path from the first power wiring to the first ground wiring. Wherein, when the first power voltage and the second power voltage are respectively supplied to the first power wiring and the second power wiring, the control circuit generates an isolation signal to cut off the discharge path. In addition, when the first power voltage and the second power voltage are not supplied, the control circuit generates a trigger signal by using an electrostatic signal from the first power wiring to turn on the discharge path.

Based on the above, the present invention proposes an electrostatic discharge protection device whose control circuit controls the clamping unit using two power supply voltages from different power supply wirings. Thereby, when the first power voltage and the second power voltage are supplied, the control circuit controlled by the two power voltages will not be easily affected by the noise, thereby increasing the anti-noise capability of the electrostatic discharge protection device.

The above described features and advantages of the present invention will be more apparent from the following description.

In the following description, in order to present the consistency of the description of the present invention, in the different embodiments, the same element symbols and names are used for the same or similar elements.

[First Embodiment]

1 is a block diagram showing an electrostatic discharge protection device according to a first embodiment of the present invention. Referring to FIG. 1 , the electrostatic discharge protection device 100 includes a control circuit 110 and a clamping unit 120 . The control circuit 110 is electrically connected to the power supply wiring 131, the power supply wiring 133, and the ground wiring 135. Further, the control circuit 110 is for receiving the power supply voltage VDD1 from the power supply line 131, the power supply voltage VDD2 from the power supply line 133, and the ground voltage GND1 from the ground line 135. The clamping unit 120 is electrically connected between the power supply wiring 131 and the ground wiring 135 and is used to provide a discharge path from the power supply wiring 131 to the ground wiring 135.

In practical applications, when the power supply voltage VDD1 and the power supply voltage VDD2 are supplied, the control unit 110 generates an isolation signal IS to clamp The control end of unit 120 is such that clamp unit 120 cuts off the discharge path. In contrast, when the power supply voltage VDD1 and the power supply voltage VDD2 are not supplied, an electrostatic discharge event may occur in the power supply wiring 131. In response to this situation, when an electrostatic discharge event occurs, the electrostatic signal will be coupled from the power supply wiring 131 to the control unit 110, and the control unit 110 will generate the trigger signal TS by using the electrostatic signal, and transmit the electrostatic signal to the control end of the clamping unit 120. So that the clamping unit 120 turns on the discharge path.

FIG. 2 is a schematic circuit diagram of an electrostatic discharge protection device according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a circuit of the electrostatic discharge protection device according to the first embodiment of the present invention. The detailed circuit and operation of the clamping unit 120.

The control unit 110 includes a trigger unit 210 and a latch unit 240. The trigger unit 210 is electrically connected to the power supply wiring 131, the power supply wiring 133, and the ground wiring 135, and the trigger unit 210 includes a P-type transistor MP1, a resistor R1, and an inverter 211. In the electrical connection, the source of the P-type transistor MP1 is electrically connected to the power supply wiring 131, and the gate of the P-type transistor MP1 is electrically connected to the power supply wiring 133. The first end of the resistor R1 is electrically connected to the drain of the P-type transistor MP1, and the second end of the resistor R1 is electrically connected to the ground wiring 135. The inverter 211 has an input terminal, an output terminal, a power supply terminal, and a ground terminal. The input end of the inverter 211 is electrically connected to the first end of the resistor R1, the power end of the inverter 211 is electrically connected to the power supply line 131 to receive the power supply voltage VDD1, and the ground end of the inverter 211 is electrically connected to the ground line 135. The ground voltage GND1 is received, and the output of the inverter 211 is used to output the control signal CS1 or the control signal CS2.

In the overall operation, when the power supply voltages VDD1 and VDD2 are supplied to the power supply wirings 131 and 133, respectively, the gate of the P-type transistor MP1 will receive the power supply voltage VDD2, thereby causing the P-type transistor MP1 to be turned off. Moreover, since the second end of the resistor R1 is electrically connected to the ground wiring 135, the ground voltage GND1 is transmitted to the input terminal of the inverter 211 through the resistor R1. Thereby, the inverter 211 operating between the power supply voltage VDD1 and the ground voltage GND1 will generate a control signal CS1 having a high voltage level, for example, the power supply voltage VDD1 in response to the received ground voltage GND1.

Incidentally, in order to ensure that the P-type transistor MP1 bias is maintained in the off state at the power supply voltages VDD1 and VDD2, the power supply voltage VDD1 must be less than or equal to the power supply voltage VDD2. In practical applications, the electrostatic discharge protection device 100 can be applied, for example, to a flash memory device. At this time, the two power supply voltages VDD1 and VDD2 required by the flash memory device are two voltages having the same voltage value, and thus the control unit 110 can be maintained in normal operation. In other words, the electronic circuit as long as the power supply voltage meets the above conditions is a range in which the electrostatic discharge protection device 100 can be applied.

When the power supply voltages VDD1 and VDD2 are not supplied, the power supply wiring 133 is in a floating state, so that the voltage of the gate of the P-type transistor MP1 will approach the ground voltage. At this time, if an electrostatic discharge event occurs in the power supply wiring 131, an electrostatic signal (for example, a positive pulse signal) from the power supply wiring 131 causes the P-type transistor MP1 to be turned on. Thereby, the electrostatic signal will be transmitted to the input end of the inverter 211 through the P-type transistor MP1. The inverter 211 is caused to generate a control signal CS2 having a low voltage level, for example, a ground voltage GND1.

The latch unit 240 includes a P-type transistor MP2, an inverter 213, and an N-type transistor MN1. Wherein, the source of the N-type transistor MN1 is electrically connected to the ground wiring 135, the drain of the N-type transistor MN1 is electrically connected to the drain of the P-type transistor MP2, and the gate of the N-type transistor MN1 is used for receiving Control signal CS1 or control signal CS2. The inverter 213 has an input terminal, an output terminal, a power supply terminal, and a ground terminal. The input end of the inverter 213 is electrically connected to the drain of the P-type transistor MP2, the power terminal of the inverter 213 is electrically connected to the power supply line 131 to receive the power supply voltage VDD1, and the ground end of the inverter 213 is electrically connected to the ground. The wiring 135 receives the ground voltage GND1, and the output end of the inverter 213 is electrically connected to the gate of the P-type transistor MP2. The source of the P-type transistor MP2 is electrically connected to the power supply wiring 131, and the drain of the P-type transistor MP2 is used to generate the isolation signal IS or the trigger signal TS.

When the power supply voltages VDD1 and VDD2 are respectively supplied to the power supply wiring 131 and the power supply wiring 133, the N-type transistor MN1 receives the control signal CS1 having a high voltage level, thereby turning on the N-type transistor MN1. Thereby, the drain of the N-type transistor MN1 will generate an isolation signal IS having a low voltage level, for example, the ground voltage GND1. On the other hand, the ground voltage GND1 is transmitted from the ground wiring 135 to the input terminal of the inverter 213. Thereby, the inverter 213 operating between the power supply voltage VDD1 and the ground voltage GND1 will generate a signal having a high voltage level (for example, the power supply voltage VDD1) to the P in response to the received ground voltage GND1. The gate of the transistor MP2, which in turn causes the P-type transistor MP2 to enter The state of conduction.

When the power supply voltages VDD1 and VDD2 are not supplied, and an electrostatic discharge event occurs in the power supply wiring 131, the trigger unit 210 will generate a control signal CS2 having a low voltage level. At this time, the gate of the N-type transistor MN1 will receive the control signal CS2 having a low voltage level, causing the N-type transistor MN1 to be turned off. In addition, an electrostatic signal (eg, a positive pulse signal) from the power supply line 131 will be coupled to the drain of the N-type transistor MN1. Thereby, the drain of the N-type transistor MN1 will generate a trigger signal TS having a high voltage level. On the other hand, the input terminal of the inverter 213 is electrically connected to the drain of the N-type transistor MN1, so an electrostatic signal (for example, a positive pulse signal) from the power supply line 131 is also coupled to the input terminal of the inverter 213. Thereby, the inverter 213 automatically latches the position of the drain of the N-type transistor MN1 through the P-type transistor MP2. That is, the inverter 213 will generate a signal having a low voltage level to the gate of the P-type transistor MP2, thereby causing the P-type transistor MP2 to be latched in an on state.

The clamping unit 120 includes an N-type transistor MN2. The source of the N-type transistor MN2 is electrically connected to the ground wiring 135, the drain of the N-type transistor MN2 is electrically connected to the power supply wiring 131, and the gate of the N-type transistor MN2 receives the isolation signal IS or the trigger signal TS. In operation, when the supply voltages VDD1 and VDD2 are supplied, the N-type transistor MN2 will receive the isolation signal IS. Since the voltage level of the isolation signal IS is the ground voltage GND1, the N-type transistor MN2 is turned off. At this time, the discharge path of the power supply wiring 131 to the ground wiring 135 is cut off, thereby preventing the power supply voltage VDD1 from leaking to the ground wiring 135.

When the power supply voltages VDD1 and VDD2 are not supplied, and an electrostatic discharge event occurs in the power supply wiring 131, the N-type transistor MN2 will correspondingly receive the trigger signal TS. Since the voltage level of the trigger signal TS is at a high voltage level, the N-type transistor MN2 is turned on. Thereby, the electrostatic signal will be guided to the ground wiring 135 via the N-type transistor MN2, so that the protected circuit is not affected by the electrostatic signal.

As described above, when an electrostatic discharge event occurs on the power supply wiring 131, the clamping unit 120 turns on the discharge path, thereby causing the protected circuit to be unaffected by the electrostatic signal. On the other hand, under normal operation, since the P-type transistor MP1 is switched to a non-conducting state under the control of the two power supply voltages VDD1 and VDD2, the control circuit 110 will not be easily received by the power supply wirings 131 and 133. The impact of noise.

For example, FIGS. 3A to 3E are respectively analog waveform diagrams according to the first embodiment of the present invention, wherein the horizontal axis in the graph represents time (in nanoseconds, ns), and the vertical axis represents voltage ( The unit is volt, V). As shown in the waveform diagram of the left half of FIG. 3A, when an electrostatic discharge event occurs on the power supply wiring 131, a positive pulse signal PS will appear on the power supply wiring 131, and the control circuit 110 will generate a voltage level as a trigger of the positive pulse signal PS. The signal TS, in turn, causes the clamping unit 120 to conduct a discharge path. Moreover, as shown in the waveform diagram of the right half of FIG. 3A, under normal operation, the power supply voltage VDD1 and the power supply voltage VDD2 are both about 3.6V, and the control circuit 110 will generate the isolation signal IS having a low voltage level. For example, 0 V, so that the clamping unit 120 cuts off the discharge path.

As shown in FIG. 3B, under normal operation, when the power supply wiring 133 is turned on In the current noise, when the power supply voltage VDD2 is briefly pulled down from 3.6V to 0V, the isolation signal IS will only briefly pull down from 0V to -0.5V. As a result, the clamping unit 120 at this time is still maintained in the cut-off state. On the other hand, as shown in FIG. 3C, when the noise appearing on the power supply wiring 133 is a positive glitch, that is, when the power supply voltage VDD2 is briefly pulled up to 10 V, the level of the isolation signal IS is almost unchanged. That is to say, the clamping unit 120 at this time is still maintained in the cut-off state.

As shown in FIG. 3D, under the above operation, if noise is simulated on the power supply wiring 131, so that the power supply voltage VDD1 is briefly pulled down from 3.6V to 0V, the isolation signal IS will only briefly pull down from 0V. To -0.25V. As a result, the clamping unit 120 at this time is still maintained in the cut-off state. Furthermore, as shown in FIG. 3E, if noise is simulated on the power supply wiring 131, so that the power supply voltage VDD1 is briefly pulled up from 3.6V to 10V, the isolation signal IS received by the clamping unit 120 will only briefly elapse from 0V. Pulled to 1.5V, and the clamping unit 120 is still maintained in the off state.

[Second embodiment]

4 is a circuit diagram of an electrostatic discharge protection device according to a second embodiment of the present invention. Referring to FIG. 4, the present embodiment is substantially the same as the first embodiment, and the same or similar component numbers in FIG. 4 denote the same or similar components, and will not be described again in this embodiment.

The main difference between this embodiment and the first embodiment is that the embodiment further includes an N-type transistor MN3, a diode D1, and a diode D2. Wherein, the source of the N-type transistor MN3 is electrically connected to the ground wiring 135, N The drain of the type transistor MN3 is electrically connected to the power supply wiring 133, and the gate of the N-type transistor receives the isolation signal IS or the trigger signal TS. The anode of the diode D1 is electrically connected to the power supply wiring 131, and the cathode of the diode D1 is electrically connected to the power supply wiring 133. The anode of the diode D2 is electrically connected to the power supply wiring 133, and the female body of the diode D2 is electrically connected to the power supply wiring 131.

In order to cause the electrostatic signals to flow between the power supply wiring 131, the power supply wiring 133, and the ground wiring 135, the diode D1 and the diode D2 are connected in series between the two power supply wirings 131 and 133. In addition, when an electrostatic discharge event occurs on the power supply wiring 131, the trigger signal TS having a high voltage level is transmitted to the gate of the N-type transistor MN3, thereby turning on the N-type transistor MN3. Furthermore, as the N-type transistor MN3 is turned on, a current loop can be formed between the power supply wiring 133 and the ground wiring 135, thereby causing the diode D1 to be turned on in response to the electrostatic signal from the power supply wiring 131. As a result, the voltage difference formed by the diode D1 can ensure that the P-type transistor MP1 is maintained in an on state, thereby causing the trigger unit 210 to normally generate the control signal CS2 having a low voltage level.

[Third embodiment]

Fig. 5 is a circuit diagram showing an electrostatic discharge protection device according to a third embodiment of the present invention. Referring to FIG. 5, the present embodiment is substantially the same as the second embodiment, and the same or similar components in FIG. 5 denote the same or similar components, and will not be described again in this embodiment.

The main difference between this embodiment and the second embodiment is that the embodiment further includes a grounding wire 137, a diode D3, and a diode D4. The grounding wire 137 is configured to receive the ground voltage GND2. The anode of the diode D3 The pole is electrically connected to the ground wiring 135, and the cathode of the diode D3 is electrically connected to the ground wiring 137. In addition, the anode of the diode D4 is electrically connected to the ground wiring 137, and the cathode of the diode D4 is electrically connected to the ground wiring 135. The ESD protection device 500 has ground wirings 135 and 137, and the diodes D3 and D4 are connected in series between the ground wirings 135 and 137 to make the flow path of the electrostatic current more complete.

In summary, the present invention provides an electrostatic discharge protection device whose control circuit utilizes two supply voltages from different power supply wirings to control the clamping unit. Wherein, when static electricity occurs, the control circuit turns on the discharge path in the clamping unit. In addition, under normal operation, the control circuit cuts off the discharge path in the clamp unit, and since the control circuit at this time is controlled by the two power supply voltages, it is not easily affected by noise. In addition, the present invention further configures the diode between different power supply wirings and different ground wirings to make the flow path of the electrostatic current more complete.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 400, 500‧‧‧ Electrostatic discharge protection device

110‧‧‧Control circuit

120‧‧‧Clamping unit

131, 133‧‧‧Power wiring

135, 137‧‧‧ Grounding Wiring

VDD1, VDD2‧‧‧ power supply voltage

GND1, GND2‧‧‧ Grounding voltage

210‧‧‧Trigger unit

240‧‧‧Latch unit

211, 213‧‧ ‧ inverter

MP1, MP2‧‧‧P type transistor

MN1, MN2, MN3‧‧‧N type transistor

R1‧‧‧ resistance

CS1, CS2‧‧‧ control signals

IS‧‧‧Isolation signal

TS‧‧‧ trigger signal

PS‧‧‧ Positive Pulse Signal

D1, D2, D3, D4‧‧‧ diodes

1 is a block diagram showing an electrostatic discharge protection device according to a first embodiment of the present invention.

2 is a circuit diagram of an electrostatic discharge protection device according to a first embodiment of the present invention.

3A to 3E are respectively analog waveform diagrams according to a first embodiment of the present invention.

4 is a circuit diagram of an electrostatic discharge protection device according to a second embodiment of the present invention.

Fig. 5 is a circuit diagram showing an electrostatic discharge protection device according to a third embodiment of the present invention.

100‧‧‧Electrostatic discharge protection device

110‧‧‧Control circuit

120‧‧‧Clamping unit

131, 133‧‧‧Power wiring

135‧‧‧ Grounding Wiring

VDD1, VDD2‧‧‧ power supply voltage

GND1‧‧‧ Grounding voltage

IS‧‧‧Isolation signal

TS‧‧‧ trigger signal

Claims (12)

An electrostatic discharge protection device comprising: a clamping unit providing a discharge path from a first power supply wiring to a first ground wiring; and a control circuit receiving a first power supply voltage from the first power supply wiring and a second power supply voltage of the second power supply wiring, wherein the control circuit includes a trigger unit and a latch unit, and when the first power voltage and the second power voltage are supplied, the trigger unit generates a first Controlling the signal, and the latch unit generates an isolation signal to cut off the discharge path. When the first power voltage and the second power voltage are not supplied, the trigger unit is based on an electrostatic wave from the first power line. The signal generates a second control signal, and the latch unit generates a trigger signal to turn on the discharge path, wherein the latch unit includes: a first P-type transistor, the source of which is electrically connected to the first power source Wiring, the drain of the first P-type transistor generates the isolation signal or the trigger signal; and a first inverter whose input end is electrically connected to the first P-type transistor An output terminal of the first inverter is electrically connected only to a gate of the first P-type transistor; and a first N-type transistor has a source electrically connected to the first ground wiring, the first The first pole of the first type N transistor is electrically connected to the trigger unit and receives the first control signal or the second Control signal. The electrostatic discharge protection device of claim 1, wherein the trigger unit comprises: a second P-type transistor, the source of which is electrically connected to the first power supply wiring, and the gate of the second P-type transistor The first power supply is electrically connected to the drain of the second P-type transistor, the second end of the resistor is electrically connected to the first ground wiring, and the second The inverter is electrically connected to the first end of the resistor, and the output of the second inverter outputs the first control signal or the second control signal. The electrostatic discharge protection device of claim 1, wherein the clamping unit is formed by a second N-type transistor, wherein a source of the second N-type transistor is electrically connected to the first ground wiring. The first N-type transistor is electrically connected to the first power supply line, and the gate of the second N-type transistor receives the isolation signal or the trigger signal. The electrostatic discharge protection device of claim 1, further comprising: a first diode, wherein the anode is electrically connected to the first power wiring, and the cathode of the first diode is electrically connected to the second a power supply wiring; a second diode having an anode electrically connected to the second power wiring, a cathode of the second diode being electrically connected to the first power wiring; and a third N-type transistor having a drain Electrically connecting the second power wiring, the gate of the third N-type transistor receives the isolation signal or the trigger signal, and the source of the third N-type transistor is electrically connected to the first ground wiring or Second ground wiring. The electrostatic discharge protection device of claim 4, wherein the source of the third N-type transistor is electrically connected to the second ground wiring, and the electrostatic discharge protection device further comprises: a third diode An anode is electrically connected to the first grounding wire, a cathode of the first diode is electrically connected to the second grounding wire, and a fourth diode is electrically connected to the second grounding wire. The cathode of the diode is electrically connected to the first ground wiring. The electrostatic discharge protection device of claim 1, wherein the first power supply voltage is equal to the second power supply voltage. An electrostatic discharge protection device includes: a control circuit electrically connected to a first power wiring, a second power wiring and a first ground wiring; and a clamping unit providing the first power wiring to the first ground a discharge path of the wiring, wherein the control circuit includes a trigger unit and a latch unit, when a first power voltage and a second power voltage are respectively supplied to the first power line and the second power line, The trigger unit generates a first control signal, and the latch unit generates an isolation signal to cut off the discharge path. When the first power voltage and the second power voltage are not supplied, the trigger unit is based on the An electrostatic signal of the first power supply line generates a second control signal, and the latch unit generates a trigger signal to turn on the discharge path, wherein the latch unit comprises: a first P-type transistor, the source thereof Electrically connecting the first power supply a drain of the first P-type transistor to generate the isolation signal or the trigger signal; a first inverter having an input terminal electrically connected to the drain of the first P-type transistor, the first inversion The output end of the device is only electrically connected to the gate of the first P-type transistor; and a first N-type transistor, the source of which is electrically connected to the first ground wiring, and the drain of the first N-type transistor The first P-type transistor is electrically connected to the first P-type transistor, and the gate of the first N-type transistor is electrically connected to the trigger unit and receives the first control signal or the second control signal. The electrostatic discharge protection device of claim 7, wherein the trigger unit comprises: a second P-type transistor, the source of which is electrically connected to the first power supply wiring, and the gate of the second P-type transistor The first power supply is electrically connected to the drain of the second P-type transistor, the second end of the resistor is electrically connected to the first ground wiring, and the second The inverter is electrically connected to the first end of the resistor, and the output of the second inverter outputs the first control signal or the second control signal. The electrostatic discharge protection device of claim 7, wherein the clamping unit is formed by a second N-type transistor, wherein a source of the second N-type transistor is electrically connected to the first ground wiring. The first N-type transistor is electrically connected to the first power supply line, and the gate of the second N-type transistor receives the isolation signal or the trigger signal. Such as the electrostatic discharge protection device described in claim 7 The first diode has an anode electrically connected to the first power wiring, a cathode of the first diode is electrically connected to the second power wiring, and a second diode has an anode. Connecting the second power wiring, the cathode of the second diode is electrically connected to the first power wiring; and a third N-type transistor electrically connected to the second power wiring, the third N The gate of the transistor receives the isolation signal or the trigger signal, and the source of the third N-type transistor is electrically connected to the first ground wiring or a second ground wiring. The electrostatic discharge protection device of claim 10, wherein the source of the third N-type transistor is electrically connected to the second ground wiring, and the electrostatic discharge protection device further comprises: a third diode An anode is electrically connected to the first grounding wire, a cathode of the first diode is electrically connected to the second grounding wire, and a fourth diode is electrically connected to the second grounding wire. The cathode of the diode is electrically connected to the first ground wiring. The electrostatic discharge protection device of claim 7, wherein the first power supply voltage is equal to the second power supply voltage.