TWI451110B - Dc-to-dc converter having test circuit and test method of the same - Google Patents

Description

DC converter with test circuit and test method thereof

The present disclosure relates to a test circuit, and more particularly to a test circuit for a DC converter and a test method therefor.

DC converters have a wide range of applications in many circuit designs. For example, a light-emitting diode circuit often uses a DC converter to drive the light-emitting diodes for illumination. The power MOS transistor is an essential component in the DC converter to charge and discharge the capacitor in the DC converter to turn the LED on or off. Therefore, the source-on-resistance of the power MOS transistor becomes an important parameter for measuring the performance. In conventional designs, the circuit that initiates the test often uses a negative voltage to trigger the control module in the test mode to control the conduction of the power MOS transistor to measure its 汲 source-on resistance. However, the ESD protection circuit connected to the test circuit may be activated due to a negative voltage and generate heat. The 导 source on-resistance is extremely sensitive to heat, so if heat is generated in the circuit environment, it will be affected and cannot be accurately measured in the test mode.

Therefore, how to design a new DC converter with test circuit and its test method to overcome the above problems is an urgent problem to be solved in the industry.

Accordingly, one aspect of the present disclosure is to provide a test circuit for a DC converter, wherein the DC converter includes a capacitor, a load, and a power MOS transistor, and the power MOS transistor is used to conduct and Closed to further charge and discharge the capacitor to drive the load. The test circuit includes: a test start-up MOS transistor and a latch module. The test start MOS transistor includes a drain, a source, and a gate for receiving a particular voltage level. The latching module comprises a latching input end and a latching output end, wherein the latching input end is connected to the drain of the test starter metal oxide semi-transistor, and the latching output end is connected to the control module of the DC converter. In the test mode, when the diode of the test start MOS transistor receives at least a certain number of signal transition patterns, the latch input is detected at the source of the test start MOS transistor. To the switch event of the corresponding signal transition mode, the latch module is triggered to latch the latch output from the initial voltage level to the test start voltage level, so that the control module can control the DC converter. The power MOS transistor is turned on to initiate a test procedure in which each signal transition form causes the test to initiate the MOS transistor to turn on and off once.

According to an embodiment of the present disclosure, when the supply voltage of the latch module is restarted, the latch module resets the latch output to terminate the test procedure.

According to another embodiment of the present disclosure, each signal transition form includes an on period and a off period, wherein the on period has a first voltage level, and the first voltage level and the specific voltage level have at least greater than the test start gold oxide. The difference between the threshold voltages of the semi-transistors, the off period having a voltage approximately equivalent to a particular voltage level. The test start-up MOS transistor is a test start-up N-type MOS transistor, the specific voltage level is the ground potential and the first voltage level is a negative voltage.

According to still another embodiment of the present disclosure, the latch module causes the control module to initiate a test procedure when the test start MOS transistor receives at least three signal transition forms.

According to still another embodiment of the present disclosure, the control module turns on the power MOS transistor in the test program to measure the drain to source on-resistance of the power MOS transistor.

Another aspect of the present disclosure is to provide a DC converter. The DC converter contains capacitors, loads, power MOS transistors, and test circuits. The power MOS transistor is connected to the capacitor and the load from the connection end and is used to turn on and off to further charge and discharge the capacitor to drive the load. The test circuit includes: a test starter MOS transistor and a latch module. The test start MOS transistor includes a drain, a source, and a gate for receiving a particular voltage level. The latching module comprises a latching input end and a latching output end, wherein the latching input end is connected to the drain of the test starter metal oxide semi-transistor, and the latching output end is connected to the control module of the DC converter. In the test mode, when the diode of the test start MOS transistor receives at least a certain number of signal transition patterns, the latch input is detected at the source of the test start MOS transistor. To the switch event of the corresponding signal transition mode, the latch module is triggered to latch the latch output from the initial voltage level to the test start voltage level, so that the control module can control the DC converter. The power MOS transistor is turned on to initiate a test procedure in which each signal transition form causes the test to initiate the MOS transistor to turn on and off once.

According to an embodiment of the present disclosure, when the supply voltage of the latch module is restarted, the latch module resets the latch output to terminate the test procedure.

According to another embodiment of the present disclosure, each signal transition form includes an on period and a off period, wherein the on period has a first voltage level, and the first voltage level and the specific voltage level have at least greater than the test start gold oxide. The difference between the threshold voltages of the semi-transistors, the off period having a voltage approximately equivalent to a particular voltage level. The test start-up MOS transistor is a test start-up N-type MOS transistor, the specific voltage level is the ground potential and the first voltage level is a negative voltage.

According to still another embodiment of the present disclosure, the latch module causes the control module to initiate a test procedure when the test start MOS transistor receives at least three signal transition forms.

According to still another embodiment of the present disclosure, the control module turns on the power MOS transistor in the test program to measure the 汲 source on-resistance of the power MOS transistor.

According to the present disclosure, there is an embodiment in which, when the DC converter is in the operation mode, the source of the test start MOS transistor receives the feedback voltage associated with the output voltage of the load to enable the test to start the MOS half. The transistor is turned off.

Another aspect of the present disclosure is to provide a test method. The test method is applied to a DC converter, wherein the DC converter includes a capacitor, a load, and a power MOS transistor. The power MOS transistor is used to turn on and off to further charge and discharge the capacitor to drive the load. The test method includes the steps of transmitting a specific voltage level to the gate of the test start MOS transistor. In the test mode, at least a specific number of signal transition forms are transmitted to the drain of the test start MOS transistor, wherein each signal transition form causes the test start MOS transistor to be turned on and off once. The source of the test MOS transistor detects the transition state of the corresponding signal transition state. The latch module is triggered to latch the latch output from the initial voltage level to the test start voltage level. According to the test starting voltage level, the control module of the DC converter is enabled to control the conduction of the power MOS transistor of the DC converter, and the test procedure is started.

According to an embodiment of the present disclosure, the method further includes the steps of: restarting the supply voltage of the latch module and resetting the latch output to terminate the test procedure.

According to another embodiment of the present disclosure, each signal transition form includes an on period and a off period, wherein the on period has a first voltage level, and the first voltage level and the specific voltage level have at least greater than the test start gold oxide. The difference between the threshold voltages of the semi-transistors, the off period having a voltage approximately equivalent to a particular voltage level. The test start-up MOS transistor is a test start-up N-type MOS transistor, the specific voltage level is the ground potential and the first voltage level is a negative voltage.

According to still another embodiment of the present disclosure, the latch module causes the control module to initiate a test procedure when the test start MOS transistor receives at least three signal transition forms.

According to still another embodiment of the present disclosure, wherein when the DC converter is in the operation mode, the source of the test start MOS transistor receives the feedback voltage associated with the output voltage of the load to enable the test to start the MOS transistor. shut down.

The advantage of applying the disclosure is that the static protection circuit is activated by avoiding the continuous receiving negative voltage of the test start-up MOS transistor by a specific number of signal transition forms, and further avoiding the thermal influence test procedure generated by the static protection circuit. The measurement results in the above, and easily achieve the above purpose.

Please refer to Figure 1. FIG. 1 is a circuit diagram of a DC converter 1 in an embodiment of the disclosure. The DC converter 1 includes a capacitor 12, a load 14, a power MOS transistor 16, a control module 18, and a test circuit 10.

The power MOS transistor 16 is connected to the capacitor 12 and the load 14 via a connection terminal P. The power MOS transistor 16 is used to turn on and off to further charge and discharge the capacitor 12 to drive the load 14. In one embodiment, the load 14 includes a plurality of light emitting diodes (not shown) to cause the light emitting diodes to conduct and emit light when the power MOS transistors 16 are turned on. When the power MOS transistor 16 is turned off, the capacitor 12 will discharge to turn off the light-emitting diode.

In one embodiment, the power MOS transistor 16 is an N-type MOS transistor, wherein the drain of the power MOS transistor 16 is connected to the connection terminal P. In an embodiment, in the operation mode, the supply voltage Vss is connected to the connection terminal P through the inductor L such that the voltage of the supply voltage Vss is coupled to the connection terminal P through the inductance L.

The control module 18 is connected to the power MOS transistor 16. The control module 18 can include an error amplifier, an oscillator, and a bandwidth modulator (not shown) to control the gate of the power MOS transistor 16 based on the reference voltage Vr and the feedback voltage FB. In the operation mode, the control module 18 can control the gate of the power MOS transistor 16 according to the comparison result between the reference voltage Vr and the feedback voltage FB to control the turn-on and turn-off of the power MOS transistor 16. In one embodiment, the feedback voltage FB is a voltage associated with an output voltage (not shown) of the load 14.

The source-on-resistance (Rds, on) of the power MOS transistor 16 is a parameter for determining its efficiency. Therefore, the 汲 source on-resistance of the power MOS transistor 16 is often measured in the test mode. In test mode, some components, such as inductor L, may not be connected to DC converter 1 for testing procedures.

In the prior art, a negative voltage is often used to trigger the control module to turn on the power MOS transistor in the test mode to measure the 导 source on-resistance. However, the ESD protection circuit connected to the test circuit may be activated due to a negative voltage and generate heat. The 导 source on-resistance is extremely sensitive to heat, so if heat is generated in the circuit environment, it will be affected and cannot be accurately measured in the test mode.

Therefore, please refer to Figure 2 at the same time. FIG. 2 is a schematic diagram of the test circuit 10 in an embodiment of the disclosure. The test circuit 10 includes a test start MOS transistor 20 and a latch module 22. In the present embodiment, the test start MOS transistor 20 is a test start N-type MOS transistor and includes a drain D, a source S and a gate G. The gate G receives a specific voltage level. In this embodiment, the specific voltage level is a ground potential GND.

The latch module 22 includes a latch input and a latch output. The latch input is connected to the drain D of the test start MOS transistor 20. The latch output is connected to the control module 18 of the DC converter 1 (not shown in Figure 2). In the test mode, when the diode D of the test start MOS transistor 20 receives at least a certain number of signal-transformed forms 21, the latch input terminal of the latch module 22 will be tested to activate the MOS transistor 20 The source D detects a transition condition corresponding to the signal transition form 21. The signal transition form of each of the signals causes the test start MOS transistor 20 to be turned on and off once.

Please refer to Figure 3. FIG. 3 is a diagram showing the signal transition form 21 (shown as Vd) of the drain D of the test start-up MOS transistor 20, and the test start-up MOS transistor 20 in an embodiment of the present disclosure. The voltage at source S (shown as Vs) and the voltage at the latch output of latch module 22 (shown as Vo).

As shown in FIG. 3, the drain D(Vd) of the test start MOS transistor 20 substantially receives a voltage approximately equal to a particular voltage level to cause the test start MOS transistor 20 to be non-conductive. Therefore, the source S (Vs) of the test start MOS transistor 20 will remain at a high level.

The gate D (Vd) of the test start MOS transistor 20 then receives three signal transition forms 3. Each signal transition form 3 includes a turn-on period 30 and a turn-off period 31. The on period 30 has a first voltage level 32, and the first voltage level 32 has a difference from a particular voltage level. The specific voltage level is a ground potential in the embodiment, and the first voltage level 32 and the specific voltage level have a difference at least greater than a threshold voltage of the test start MOS transistor 20. In the present embodiment, since the test start MOS transistor 20 is a test start N-type MOS transistor, the first voltage level 32 is a negative voltage, so that the first voltage level 32 is lower than a specific one. The voltage level (ie, the gate voltage) further causes the test to start the MOS transistor 20.

Therefore, the negative voltage in the on-period 30 allows the test to initiate the conduction of the N-type MOS transistor. The source S (Vs) of the test start MOS transistor 20 is thus pulled to a low level. In one embodiment, the negative voltage is -1 volt. In other embodiments, the negative voltage can be any value less than the threshold voltage of the test start MOS transistor 20.

During the off period 31, the voltage level will return to a particular voltage level, which in this embodiment is the ground potential. Therefore, the test start MOS transistor 20 will be turned off again. The source S (Vs) of the test start MOS transistor 20 is pulled to a high potential.

After the drain D (Vd) of the test start MOS transistor 20 receives three signal transition forms 3, the source S (Vs) has a transition condition corresponding to the three signal transition forms 3. After detecting the transition state of the source S, the latch module 22 is triggered to latch the latch output (Vo) to be latched to a test start voltage level by an initial voltage level. In this embodiment, respectively, a low voltage and a high voltage. In this embodiment, the three low levels can trigger the latch module 22. In other embodiments, a full waveform of three low levels and three high levels may be set to trigger the latch module 22. After the latch output (Vo) is latched, the latch module 22 no longer changes the state of the latch output regardless of any subsequent changes to the latch input. Therefore, the latch module 22 can start the test procedure after detecting the transition state of the three signal transition states, even if the gate D of the test start MOS transistor 20 actually receives four or more. Signal form.

The test start voltage level of the latch output (Vo) is then transmitted to the control module 18 depicted in FIG. 1 to enable the control module 18 to further power the DC converter 1 power MOS transistor. 16 conduction. Therefore, the test program will start. In one embodiment, the power MOS transistor 16 will be turned on in the test mode to measure its 汲 source on-resistance.

In one embodiment, the latch module 22 receives the supply voltage Vdd. When the supply voltage Vdd of the latch module 22 is restarted, the latch module 22 can reset the latch output terminal (Vo) to return to the initial voltage level, and end the test procedure.

In one embodiment, the gate D (Vd) of the test start MOS transistor 20 can receive only one signal transition form to initiate the test procedure. However, some test procedures that do not measure power MOS transistors, such as open circuit tests or short circuit tests in chip probing (CP), or static protection circuit tests, may trigger a test. The aforementioned signal transition form causes the test to start the MOS transistor 20 to falsely start the test procedure. Therefore, in order to avoid accidental contact with the test circuit in other test procedures, it is preferable to have the test start MOS transistor 20 initiate the test procedure upon receiving two or more signal transition forms.

In one embodiment, in the operational mode, the source S of the startup MOS transistor 20 is tested to receive a feedback voltage FB (positive voltage in this embodiment) associated with the output voltage of the load 14 to The test starter MOS transistor 10 is turned off in operational mode. In the operational mode, all necessary components will be connected to the circuit of the DC converter 1.

The DC converter having the test circuit in the present disclosure provides a mechanism for preventing the detection of the start-up of the MOSFET of the MOS transistor due to the continuous connection to the negative voltage, thereby causing the generated heat to affect the measurement result.

Please refer to Figure 4. Figure 4 is a flow chart of a test method in an embodiment of the disclosure. The test method can be applied to the DC converter 1 having the test circuit 10 shown in FIG. The test method consists of the following steps. (It should be understood that the steps mentioned in the present embodiment can be adjusted according to actual needs, and can be performed simultaneously or partially simultaneously, unless otherwise specified.

Step 401: Transfer a specific voltage level to the gate of the test start MOS transistor 20.

Step 402: Transmit at least a specific number of signal-transformed forms 21 to the gates of the test-starting MOS transistor 20, wherein each of the signal-transformed forms causes the test-starting MOS transistor to be turned on and off once.

Step 403: The source of the MOS transistor 20 is tested to detect the transition state of the corresponding signal transition state 21.

Step 404: Trigger the latch module 22 to latch the latch output from the initial voltage level to the test start voltage level.

Step 405: The control module 18 of the DC converter 1 is enabled according to the test start voltage level to control the conduction of the power MOS transistor 16 of the DC converter 1, and the test procedure is started. In one embodiment, the test procedure measures the germanium source on-resistance of the power MOS transistor 16 of FIG. 1 by the conduction of the power MOS transistor 16.

Step 406: Restart the supply voltage Vdd of the latch module 22 and reset the latch output to terminate the test procedure. That is, after the latch output is reset, it will return to the initial voltage level, and the power MOS transistor 16 is turned off to terminate the measurement of the 汲 source on-resistance of the power MOS transistor 16.

The present disclosure has been disclosed in the above embodiments, but it is not intended to limit the disclosure, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the disclosure. The scope of protection of the disclosure is subject to the definition of the scope of the patent application.

1‧‧‧DC Converter

10‧‧‧Test circuit

12‧‧‧ Capacitance

14‧‧‧ load

16‧‧‧Power MOS semi-transistor

18‧‧‧Control Module

20‧‧‧Test start-up MOS semi-transistor

21‧‧‧ Signal form

22‧‧‧Latch module

3‧‧‧ Signal form

30‧‧‧ conduction cycle

31‧‧‧Close cycle

32‧‧‧First voltage level

401-406‧‧‧Steps

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. The description of the drawings is as follows: FIG. 1 is a circuit diagram of a DC converter according to an embodiment of the disclosure; 2 is a schematic diagram of a test circuit in an embodiment of the disclosure; FIG. 3 is a diagram showing a signal transition state of a drain of a test start-up MOS transistor, and a test start in an embodiment of the present disclosure A waveform diagram of the voltage of the source of the MOS transistor and the voltage at the latch output of the latch module; and FIG. 4 is a flow chart of the test method in an embodiment of the disclosure.

10. . . Test circuit

20. . . Test starter gold oxide semi-transistor

twenty one. . . a specific number of signal transition forms

twenty two. . . Latch lock module

Claims (19)

A test circuit is applied to a dc-to-dc converter, wherein the DC converter includes a capacitor, a load, and a power MOS transistor, and the power MOS transistor is used Turning on and off to further charge and discharge the capacitor to drive the load. The test circuit includes: a test start MOS transistor, including a drain, a source, and a specific voltage level for receiving a gate; and a latch module comprising a latch input and a latch output, wherein the latch input is coupled to the drain of the test start MOS transistor, the latch output Connected to a control module of the DC converter; wherein in a test mode, when the test initiates the drain of the MOS transistor to receive at least a certain number of signal transition patterns, The latch input terminal detects a switch event of the corresponding signal transition state at the source of the test start MOS transistor, and triggers the latch module to enable the latch output End from an initial Pressing the voltage level to a test starting voltage level, so that the control module can control the conduction of the power MOS transistor of the DC converter to initiate a test procedure, wherein each of the signals is in a state of transition This test initiates the galvanic transistor to turn on and off once. The test circuit of claim 1, wherein when one of the latch modules supplies a voltage restart, the latch module resets the latch output to terminate the test procedure. The test circuit of claim 1, wherein each of the signal transition forms includes an on period and a off period, wherein the on period has a first voltage level, the first voltage level and the specific voltage level There is at least a difference between a threshold voltage of the test start-up MOS transistor, and the turn-off period has a voltage approximately equivalent to the specific voltage level. The test circuit of claim 3, wherein the test start MOS transistor is a test start N-type MOS transistor, the specific voltage level is a ground potential and the first voltage level is a negative Voltage. The test circuit of claim 1, wherein the latch module causes the control module to initiate the test procedure when the test start MOS transistor receives at least three signal transition forms. The test circuit of claim 1, wherein the control module turns on the power MOS transistor to measure a 汲 source on-resistance of the power MOS transistor. A DC converter comprising: a capacitor; a load; a power MOS semi-transistor connected to the capacitor and the load by a connection end, the power MOS transistor being used to be turned on and off to further The capacitor is charged and discharged to drive the load; a control module is coupled to the power MOS transistor; and a test circuit includes: a test start MOS transistor, including a drain, a source And a latching module for receiving a specific voltage level; and a latching module comprising a latching input end and a latching output end, wherein the latching input end is connected to the test to activate the metal oxide half-electricity a drain of the crystal, the latch output being coupled to a control module of the DC converter; wherein in a test mode, when the test initiates the drain of the MOS transistor, at least a specified number is received When the signal is in the form of a transition state, the latch input terminal detects a transition state of the corresponding signal transition state at the source of the test start MOS transistor, and triggers the latch module to make the plug Lock output from one The initial voltage level is latched to a test enable voltage level, so that the control module can control the conduction of the power MOS transistor of the DC converter to initiate a test procedure, wherein each of the signal transition forms The test is initiated to turn the MOS transistor on and off once. The DC converter of claim 7, wherein when one of the latch modules supplies a voltage restart, the latch module resets the latch output to terminate the test procedure. The DC converter of claim 7, wherein each of the signal transition forms includes an on period and a off period, wherein the on period has a first voltage level, the first voltage level and the specific voltage level The bit has a difference at least greater than a threshold voltage of the test start MOS transistor, the turn-off period having a voltage approximately equivalent to the particular voltage level. The DC converter of claim 9, wherein the test start MOS transistor is a test start N-type MOS transistor, the specific voltage level is a ground potential and the first voltage level is a Negative voltage. The DC converter of claim 7, wherein the latch module causes the control module to initiate the test procedure when the test start MOS transistor receives at least three signal transition forms. The DC converter of claim 7, wherein when the DC converter is in an operational mode, the source of the test-starting MOS transistor receives a feedback voltage associated with an output voltage of the load, In order for this test to start the MOS transistor is turned off. The DC converter of claim 7, wherein the control module conducts the power MOS transistor in the test procedure to measure a source-on-resistance of the power MOS transistor. A test method is applied to a DC converter, wherein the DC converter includes a capacitor, a load, and a power MOS transistor, and the power MOS transistor is used to turn on and off to further The capacitor is charged and discharged to drive the load. The test method includes the steps of: transmitting a specific voltage level to a gate of a test start MOS transistor; and transmitting at least a specific number in a test mode The signal transition form to the test initiates one of the MOSFETs, wherein each of the signal transition forms causes the test to initiate the MOS transistor to be turned on and off once; The source detects a transition state corresponding to the signal transition mode; triggers a latch module to latch the latch output from an initial voltage level to a test enable voltage level; and according to the test The startup voltage level enables a control module of the DC converter to control the conduction of the power MOS transistor of the DC converter, and initiates a test procedure. The test method of claim 14, further comprising the steps of: restarting one of the latch modules to supply a voltage; and resetting the latch output to terminate the test procedure. The test method of claim 14, wherein each of the signal transition forms includes a conduction period and a shutdown period, wherein the conduction period has a first voltage level, the first voltage level and the specific voltage level There is at least a difference between a threshold voltage of the test start-up MOS transistor, and the turn-off period has a voltage approximately equivalent to the particular voltage level. The test method of claim 14, wherein the test-starting MOS transistor is a test-starting N-type MOS transistor, the specific voltage level is a ground potential and the first voltage level is a negative Voltage. The test method of claim 14, wherein the latch module causes the control module to initiate the test procedure when the test start MOS transistor receives at least three signal transition forms. The test method of claim 14, wherein the control module turns on the power MOS transistor to measure a 汲 source on-resistance of the power MOS transistor.