TWI448030B - Deglitch circuit - Google Patents

Description

Surge elimination circuit

This invention relates to a circuit design, and more particularly to a circuit that can be used in a communication busbar to effectively suppress or eliminate glitch.

In many electronic devices, serial communication busbars such as I ² C and SMBus have a rise time required for the signal on the cable to reach a high level and a fall time required to return to a low level is too long. In the process of digitization, the output signal tends to fluctuate up and down, and the correct waveform cannot be formed. Such an error is generally called a glitch, which may also be called a glitch.

These unpredictable surges can cause erroneous logic output and lead to errors or even loss of data. Therefore, how to effectively suppress and avoid the occurrence of glitch is an important issue.

In the prior art, the high-sampling technique is used to eliminate the glitch, wherein the frequency of the high sampling clock must be more than several times higher than the I ² C clock, and cannot be turned off through the I ² C interface, thus causing I ² C The standby power consumption of the device increases, and if the I ² C device is operated with a battery, the use time is further reduced.

In view of this, the present invention particularly provides a circuit capable of effectively suppressing and eliminating glitch, which can be widely applied to various electronic devices, particularly serial communication busbars such as I ² C and SMBus.

One of the objects of the present invention is to eliminate the occurrence of glitch in an electronic device, thereby avoiding the error or distortion of the output signal, thereby eliminating the problem of data loss and damage.

Another object of the present invention is to eliminate the glitch with a simpler and more stable circuit architecture to improve the shortcomings of conventional glitch cancellation circuits, such as overcoming the increase in standby power consumption caused by high sampling techniques.

In order to achieve the above object, in one aspect of the present invention, a surge elimination circuit is disclosed, comprising: an input terminal; at least one and a gate delay element coupled to the input terminal; at least one or a gate delay element coupled to the above An input end; a multiplexer coupled to the at least one gate delay element and the at least one gate delay element; and an output coupled to the multiplexer; wherein the multiplexer is based on an output signal The level is determined to transmit an input signal by the at least one gate delay element or by the at least one gate delay element. Preferably, if the output signal is at a high level, the multiplexer selects or gates the delay element to transmit the connected input signal; relatively, if the output signal is at the low level, the multiplexer selects the gate delay element. To transmit the incoming input signal.

In another aspect of the present invention, a communication bus circuit having a surge elimination circuit is disclosed, comprising: a bus bar; a buffer coupled to the input terminal; and a plurality of electrostatic discharge (ESD) devices coupled Between the input terminal and the buffer; and a surge cancellation circuit. The glitch canceling circuit includes: at least one and a gate delay element coupled to the buffer; at least one gate delay element coupled to the buffer; a multiplexer coupled to the at least one gate delay element and And the at least one gate delay element; and an output terminal coupled to the multiplexer; wherein the multiplexer determines the at least one gate delay component or the at least one of the gates according to an output signal level The gate delay element transmits an input signal. Preferably, if the output signal is at a high level, the multiplexer selects or gates the delay element to transmit the connected input signal; relatively, if the output signal is at the low level, the multiplexer selects the gate delay element. To transmit the incoming input signal.

With the above design, the surge canceling circuit of the present invention has the advantage of utilizing the gate delay element and the gate delay element to eliminate the glitch caused by the rise and fall of the original signal, respectively. In addition, another advantage of the present invention is that a multiplexer can be utilized to select an appropriate OR gate or gate delay element to cancel the corresponding glitch based on the level of the output signal. Thereby, the invention not only has a simple structure, but also effectively eliminates the glitch, thereby overcoming the difficulties existing in the prior art.

The above is used to clarify the object of the present invention, the technical means for achieving the object, the advantages thereof, and the like. The invention will be apparent to those skilled in the art from the description of the appended claims.

The invention will be described in the following preferred embodiments and aspects, which are intended to illustrate the invention, and are intended to be illustrative only and not to limit the scope of the invention. Therefore, the present invention may be widely practiced in other embodiments in addition to the preferred embodiments described in the specification.

Referring to the first figure, this figure shows the communication bus circuit disclosed in the present invention. As shown, the communication bus circuit includes at least a power supply terminal 101, a bus bar 102, an electrostatic discharge device 103, a buffer 104, and a surge cancel circuit 105. In this embodiment, the bus bar 102 is coupled to the power terminal 101 via a resistor, and can be connected to an external master device or an open-drain input/output device (I/O) for transmitting data. . The waveform of the original signal A input by the external device is depicted below the bus bar 102. As shown in the figure, the original signal has to go through a rising time when it wants to reach a high level, thus forming a rising curve to the left of the signal A. Similarly, the original signal To return to the low level, it is necessary to go through a fall time to form a falling curve to the right of the signal A waveform. Electrostatic discharge device 103 is coupled to bus bar 102 for protecting internal circuitry from static electricity. The buffer 104 is coupled to the electrostatic discharge device 103, which may additionally be coupled to a Schmidt trigger (not shown) to facilitate signal processing. The waveform of the signal B shown below the buffer 104 depicts the signal presented after passing through the buffer 104. As shown, the signal B has a number of small square waves, which are the surges caused by the rising and falling curves of the signal A. The glitch cancellation circuit 105 is coupled to the buffer 104 for canceling the glitch in the signal B to produce the correct output signal C. The signal C processed by the surge cancel circuit 105 is transmitted to the circuit at the rear.

Referring to the second figure, the figure shows a preferred embodiment of the surge canceling circuit 105 disclosed in the present invention. The surge eliminating circuit 105 includes an input terminal 201, at least one and a gate delay element 202, and at least one or a gate. Delay element 203, multiplexer 204 and output 205. In the present embodiment, the gate delay element 202 is coupled between the input terminal 201 and the multiplexer 204 for eliminating the spur caused by the signal rising to a high level, or the gate delay element 203 is coupled to The input terminal 201 and the multiplexer 204 are used to eliminate the spur caused by the signal being lowered to a low level. In other words, the gate delay element 202 and the gate delay element 203 are connected in parallel between the input terminal 201 and the multiplexer 204. Output 205 is coupled to multiplexer 204 to transmit the post-surge signal to the rear circuit. In the present embodiment, the multiplexer 204 selects the pass and gate delay element 202 or the gate delay element 203 to transmit an input signal based on the level of the output signal. In detail, when the signal output by the multiplexer 204 is a high level "1", the gate delay element 203 is selected to transmit the subsequent input signal, and relatively, when the output signal of the multiplexer is low." When 0", the gate delay element 202 is selected to also transmit subsequent input signals. Referring to the first figure again, after the original signal A is at a high level, it will start to drop to a low level, and the falling time is too long, thereby causing a glitch. At this time, due to the multiplexer 204 selection or gate delay The component 203 is transmitted, so that the spur generated by the level drop can be effectively eliminated; relatively, when the original signal A is at the low level, it will start to rise to a high level, and if the rising time is too long, the glitch will be caused. At this time, since the multiplexer 204 selects and transmits the gate delay element 202, the glitch generated by the level rise can be effectively eliminated. Therefore, the multiplexer 204 of the present invention utilizes the above characteristics to eliminate the glitch generated when the signal rises and falls. In this embodiment, the more the number of the gate delay element 202 and the gate delay element 203, the more effectively the glitch can be eliminated, and the number can be determined according to the user's needs. In some embodiments, the gate delay element 202 and the gate delay element 203 may be connected in series with other delay elements, such as a delay element or a flip-flop connected in series by a plurality of inverters.

Referring to the third figure, this figure shows an embodiment of the gate delay element disclosed in the present invention, which mainly includes a delay element 301 and an AND gate 302, and the input terminals of the gate 302 are Connected to the input and output terminals of the delay element 301, when the signal is logically operated via the AND gate 302, the output signal can filter out the glitch. The delay element 301 can be connected in series by a plurality of inverters or a flip-flop. As shown in the figure, the signal D represents the glitch of the input and the delay element, which is caused by the rise of the original signal, and the signals E and F represent the signal processed by the AND gate 302. In this embodiment, it is assumed that the square wave width of the signal D is Tp, and the judgment reference width of the gate 302 is Td. When Tp>Td, the width of the output signal of the gate 302 is Tp-Td, when Tp<Td Then, the glitch will be eliminated. With such a logical operation, if the complex and gate delay elements 202 are connected in series, the width of the glitch can be gradually reduced, and finally completely eliminated, so that the spur caused by the rise in level can be effectively eliminated.

Referring to the fourth figure, this figure shows an embodiment of the present invention or a gate delay element, which includes a delay element 401 and an OR gate 402. The two inputs of the OR gate 402 are respectively connected to the delay. Input and output of component 401. When the signal is logically operated via the OR gate 402, the output signal can filter out the glitch. The delay element 401 can be connected in series by a plurality of inverters or a flip-flop. As shown in the figure, the signal G represents the glitch of the input and the delay element, which is the glitch caused by the falling of the level of the original signal, and the signals H and I represent the processing via the sluice 402. Signal. In this embodiment, it is assumed that the square wave width of the signal D is Tp, or the judgment reference width of the gate 302 is Td. When Tp>Td, the width of the output signal of the gate 302 is Tp-Td, when Tp<Td Then, the glitch will be eliminated. With such a logical operation, if the complex or gate delay elements 203 are connected in series, the width of the glitch can be gradually reduced, and finally completely eliminated, so that the spur caused by the level drop can be effectively eliminated.

The above-mentioned gate delay element, gate delay element and multiplexer can be completed by a conventional clockless static logic circuit, so no other clock is needed, so standby power consumption can be minimized.

In addition, the above delay elements can also be implemented with a clocked circuit, but the standby power consumption cannot be minimized.

Please refer to FIG. 5A. This figure shows an embodiment of the present invention for processing an I ² C clock signal. Generally, as shown in the first figure, an I ² C clock signal is input from the bus bar 102 via a glitch. After the circuit 105 is eliminated, the I ² C clock signal after the cancellation of the surge is transmitted to the I ² C protocol controller 501 for the surge cancellation circuit.

Please also refer to FIG. 5B, which shows a conventional circuit system for processing I ² C clock signals. As shown, the conventional circuitry includes four D-Flip flops (D-FlipFlop) that are coupled to the buffer 104. One of the inputs of the AND gate 504 is coupled to one of the D flip-flops 503; or one of the inputs of the gate 505 is coupled to another D flip-flop 503. The AND gate 504 and the other input of the OR gate 505 are coupled to each other, and the outputs of the AND gate 504 and OR gate 505 are coupled to the I ² C protocol controller 502, respectively. In addition, the circuitry further includes a clock signal generator 506 coupled to the I ² C protocol controller 502. Compared to the embodiment of the present invention shown in FIG. 5A, the prior art shown in FIG. 5B must use more logic elements to transmit signals, and utilize high sampling techniques to eliminate the glitch, wherein the high sampling The frequency of the clock must be higher than the I ² C clock several times and cannot be turned off through the I ² C interface, thus causing the standby power consumption of the I ² C device to rise. If the I ² C component is operated by the battery, the use will be reduced. time. However, if the system of the present invention is employed, the above problems can be effectively eliminated.

The above description is a preferred embodiment of the invention. Those skilled in the art should be able to understand the invention and not to limit the scope of the patent claims claimed herein. The scope of patent protection is subject to the scope of the patent application and its equivalent fields. Any modification or refinement made by those skilled in the art without departing from the spirit or scope of the present invention is equivalent to the equivalent change or design made in the spirit of the present disclosure, and should be included in the following patent application scope. Inside.

101. . . Power terminal

102. . . Busbar

103. . . Electrostatic discharge device

104. . . buffer

105. . . Surge elimination circuit

106. . . Output

201. . . Input

202. . . Gate delay element

203. . . Gate delay element

204. . . Multiplexer

205. . . Output

301. . . Delay element

302. . . Gate

401. . . Delay element

402. . . Gate

501. . . I ² C protocol controller for surge cancellation circuit

502. . . I ² C protocol controller

503. . . D flip-flop

504. . . Gate

505. . . Gate

506. . . Clock signal generator

A, B, C, D, F, G, H, I. . . Signal

The first figure shows an embodiment of the busbar circuit of the present invention;

The second figure shows a preferred embodiment of the surge cancellation circuit of the present invention;

The third figure shows an embodiment of the gate delay element of the present invention;

The fourth figure shows an embodiment of the OR gate delay element of the present invention;

Figure 5A shows an embodiment of the present invention for processing an I ² C clock signal;

Figure 5B shows a conventional circuit system for processing I ² C clock signals.

201. . . Input

202. . . Gate delay element

203. . . Gate delay element

204. . . Multiplexer

205. . . Output

Claims (10)

A surge elimination circuit comprising: an input; at least one and a gate delay element coupled to the input; at least one or a gate delay element coupled to the input; a multiplexer coupled to the at least one a gate delay element and the at least one gate delay element; and an output terminal coupled to the multiplexer; wherein the multiplexer determines whether the at least one gate delay component or the gate device is based on an output signal level The at least one or gate delay element transmits an input signal. The glitch canceling circuit of claim 1, wherein when the output signal is at a high level, the multiplexer selects the at least one or gate delay element to transmit the input signal. The glitch canceling circuit of claim 1, wherein when the output signal is at a low level, the multiplexer selects the at least one gate delay element to transmit the input signal. The surge cancellation circuit of claim 1, wherein the gate delay element comprises a delay element and a gate. The surge cancellation circuit of claim 4, wherein the input terminals of the AND gate are respectively coupled to the input and output terminals of the delay element. The surge cancellation circuit of claim 1, wherein the OR gate delay element comprises a delay element and an OR gate. The surge cancellation circuit of claim 6, wherein the input terminals of the OR gate are respectively coupled to the input and output terminals of the delay element. A communication bus circuit having a surge elimination circuit, comprising: a bus bar; a buffer coupled to the bus bar; and a surge cancellation circuit comprising: at least one and a gate delay element coupled to the buffer At least one or a gate delay element coupled to the buffer; a multiplexer coupled to the at least one gate delay element and the at least one gate delay element; and an output coupled to the multiplexer; The multiplexer determines to transmit an input signal by the at least one gate delay element or by the at least one gate delay element according to an output signal level. The communication bus circuit with a surge canceling circuit according to claim 8, wherein when the output signal is at a high level, the multiplexer selects the at least one or gate delay element to transmit the input signal. The communication bus circuit with a surge canceling circuit according to claim 8, wherein when the output signal is at a low level, the multiplexer selects the at least one gate delay element to transmit the input signal.