TWI447950B - Leds and methods for manufacturing the same - Google Patents

Description

Light-emitting diode and method of forming same

The present invention relates to light emitting diodes, and more particularly to their sidewall structures.

As shown in FIG. 1, a common LED chip is formed by stacking a substrate 10, a semiconductor layer 11, an active layer 13, and a semiconductor layer 15, and has a flat sidewall surface. The above semiconductor layers 11 and 15 are electrically opposite. A solder pad 17 is provided on the semiconductor layers 11 and 15, respectively, to be electrically connected to an external circuit. The flat sidewall surface causes total reflection of the light emitted by the active layer 13, thereby reducing the light extraction efficiency of the LED wafer. In order to solve the above problem, an undercut shaped LED wafer can be formed by dry etching or wet etching, as shown in FIG. The upper and lower narrow undercut structures can increase the light extraction efficiency of the LED chip, but destroy some of the active layer 13 and degrade the device performance.

In summary, there is a need for a new LED wafer structure and corresponding formation method to solve the problem of total reflection caused by the flat sidewall surface.

An embodiment of the present invention provides a method for forming a light emitting diode, comprising: sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, and electrically connecting the first semiconductor layer and the second semiconductor layer Conversely; forming a trench through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to define a stacked structure between the trenches; forming a planarization layer on the first semiconductor layer and the second semiconductor layer Full of trenches; forming a hard mask pattern on the planarization layer, the hard mask pattern has a mask region and an open region, and the open region corresponds to the trench; oblique ion implantation is performed through the open region to make the first semiconductor layer The sidewall has a doped region; the hard mask pattern and the planarization layer are removed; and the doped region is removed to form a recess.

An embodiment of the invention provides a light emitting diode comprising: a substrate; the first semiconductor layer is disposed on the substrate, the first semiconductor layer has a first region and a second region, and the thickness of the first region is greater than the thickness of the second region; a recess, a sidewall of the first region of the first semiconductor layer; a light emitting layer on the first region of the first semiconductor layer; and a second semiconductor layer on the light emitting layer, and the first semiconductor layer and the second semiconductor The electrical properties of the layers are reversed.

As shown in FIG. 3A, the substrate 10 is first provided. The substrate 10 may be a sapphire substrate, a germanium substrate, or a tantalum carbide substrate. Then, the semiconductor layer 11, the active layer 13, and the semiconductor layer 15 are sequentially formed on the substrate 10, and the formation method may be an epitaxial method. The electrical properties of the semiconductor layers 11 and 15 are opposite. When the semiconductor layer 11 is of the n-type, the semiconductor layer 15 is p-type, and vice versa. In an embodiment of the invention, the semiconductor layer 11 is an n-type gallium nitride layer, the semiconductor layer 15 is a p-type gallium nitride layer, and the active layer 13 is a multiple quantum well composed of indium gallium nitride/gallium nitride. (MQW). In other embodiments, the semiconductor layers 11 and 15 and the active layer 13 may be other known compositions, and are not limited to the above composition. The thickness of the semiconductor layer 11 may be greater than, equal to, or less than the thickness of the semiconductor layer 15. In an embodiment of the invention, the n-type semiconductor layer 11 has a thickness smaller than the thickness of the p-type semiconductor layer 15. The structure shown in Fig. 3A is as shown in Fig. 3B.

Next, as shown in FIG. 4A, a trench 41 is formed through the semiconductor layer 15, the active layer 13, and a portion of the semiconductor layer 11 to define a stacked structure between the trenches 41. The method of forming the trenches 41 can be a common lithography process with an etching process. For example, a mask layer (not shown) may be formed on the semiconductor layer 15, and a photoresist pattern may be formed on the mask layer by a lithography process. The mask layer not protected by the photoresist pattern is then removed, and the semiconductor layer 15, the active layer 13, and a portion of the semiconductor layer 11 which are not protected by the mask layer are removed. The etching process described above is preferably an anisotropic etching process, such as dry etching using plasma. As a result, the stacked structure will have flat sidewalls and avoid undercut damage to the active layer 13. The structure shown in Fig. 4A is as shown in Fig. 4B. As shown in FIGS. 4A and 4B, the semiconductor layer 11 is divided into a first portion 11A in the stacked structure and a second portion 11B exposed by the trench 41. It will be understood that although the first portion 11A in the illustration has a top view that is rectangular, it may be other shapes such as squares, diamonds, or other shapes, depending on the needs.

Next, as shown in Fig. 5A, the planarization layer 51 is satisfactorily formed on the structure of Fig. 4A. The layer 51 is planarized and has a flat upper surface. In an embodiment of the invention, the planarization layer 51 may be a benzocyclobutene (BCB) such as a non-photosensitive BCB resin, which may be formed by a spin coating method. The structure shown in Fig. 5A is as shown in Fig. 5B.

Next, as shown in FIG. 6A, a hard mask pattern 61 is formed on the planarization layer 51. The hard mask pattern 61 is divided into a mask region 61A and an opening region 61B, and the opening region 61B corresponds to the trench 41. The hard mask pattern 61 may be formed by forming a full layer of a hard mask layer (not shown) such as a metal mask, a photoresist, an oxide such as yttria or zinc oxide, or a nitride such as tantalum nitride. Then, a photoresist pattern is formed on the hard mask layer by a lithography process. The hard mask layer not covered by the photoresist pattern is then removed, that is, the hard mask pattern 61 is completed. The structure shown in Fig. 6A is as shown in Fig. 6B.

Next, as shown in Fig. 7A, oblique ion implantation is performed. The oblique ion implantation will pass through the opening region 61B, so that the semiconductor layer 11 near the bottom of the trench 41 forms the doping region 81 shown in Fig. 8A. In order to prevent the oblique ion implantation from affecting the active layer 13, the width of the open region 61A is preferably smaller than the width of the trench 41. In an embodiment of the invention, the dopant used in the oblique ion implantation process may be argon ions or oxygen ions, and the oblique angle may be between 5° and 40°. If the oblique angle of the implant is too large, the active region 13 may have a doped region. If the oblique angle of the implant is too small, the doping region 81 will be formed on the upper surface of the second portion 11B of the semiconductor layer 11, instead of the sidewall portion of the first portion 11A of the semiconductor layer 11 adjacent to the trench 41. . The structure shown in Fig. 7A is as shown in Fig. 7B.

Next, as shown in FIG. 8A, the hard mask pattern 61 and the planarization layer 51 are removed. The method of removing the hard mask pattern 61 may be wet etching using an acid or alkali solution. The method of removing the planarization layer 51 may be wet etching using an acid or alkali solution. The structure shown in Fig. 8A is as shown in Fig. 8B.

Next, as shown in FIG. 9A, a protective layer 91 is formed on the upper surface of the semiconductor layer 15. The protective layer 91 may be composed of cerium oxide (SiO ₂ ), cerium nitride (Si ₃ N ₄ ), or aluminum oxide (Al ₂ O ₃ ), etc., and may be formed by plasma-assisted chemical vapor deposition or sputtering. Such as electron gun sputtering (E-Gun / Sputter), or evaporation. The structure shown in Fig. 9A is as shown in Fig. 9B.

Next, as shown in FIG. 10A, the doping region 81 is removed. In an embodiment of the invention, the method of removing the doping region 81 may be inductively coupled plasma, reactive ion etching, wet etching, or a combination thereof. Since the semiconductor layer 15 is covered with the protective layer 91, the step of removing the doping region 81 does not affect the upper surface of the semiconductor layer 15. It is worth noting that the aforementioned oblique ion implantation deteriorates the crystal lattice of the doping region 81, so the same removal condition can completely remove the doping without significantly affecting the sidewalls of the semiconductor layer 15 and the active layer 13. Zone 81 is formed to form a recess 100. It can be understood that although the recess 100 in Fig. 10A has a curved edge, it may have a flat edge and look at the parameters of the oblique ion implantation. The structure shown in Fig. 10A is as shown in Fig. 10B. As described above, the upper view of the first portion 11A of the semiconductor layer 11 may be rectangular as shown in FIG. 10B. In an embodiment of the invention, the recess 100 is formed on four sides of the first portion 11A of the rectangle. In another embodiment of the present invention, the recess 100 is formed only on the long side of the first portion 11A of the rectangle without forming the short side of the first portion 11A of the rectangle to save on the short side of the rectangle. The cost of forming the cavity 100. When the ratio of the long side to the short side of the first portion 11A of the rectangle is larger, the above technique of forming only the concave side on the long side of the rectangle is more cost-effective, and the light extraction efficiency is not lost.

Next, as shown in Fig. 11, after the protective layer 91 is removed, pads 17 are formed on the surfaces of the semiconductor layer 15 and the second portion 11B of the semiconductor layer 11, respectively. A cutting process is then performed to form individual light emitting diodes 110. The method of removing the protective layer 91 may be wet etching using an acid or alkali solution. The pad 17 may be composed of gold, silver, copper, titanium, aluminum, nickel, or a combination thereof, and may be formed by electron gun sputtering. The so-called light-emitting diode has been completed so far, and the sidewall of the semiconductor layer 11 has a recess 100 to avoid a total reflection phenomenon, thereby increasing the light extraction efficiency. On the other hand, the step of forming the recess 100 does not destroy the active layer 13, and thus has better component performance than the conventional undercut structure.

While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Substrate

11, 15. . . Semiconductor layer

11A. . . First region of the semiconductor layer 11

11B. . . Second region of the semiconductor layer 11

13. . . Active layer

17. . . Solder pad

41. . . Trench

51. . . Flattening layer

61. . . Hard mask pattern

61A. . . Mask area

61B. . . Open area

81. . . Doped region

91. . . The protective layer

100. . . pit

110. . . Light-emitting diode

Figure 1-2 is a cross-sectional view of a light-emitting diode in the prior art;

3A-10A and 11 are cross-sectional views showing a process of a light-emitting diode in an embodiment of the present invention;

3B-10B is a top view of the structure of Figures 3A-10A.

10. . . Substrate

11, 15. . . Semiconductor layer

11A. . . First region of the semiconductor layer 11

11B. . . Second region of the semiconductor layer 11

13. . . Active layer

17. . . Solder pad

100. . . pit

110. . . Light-emitting diode

Claims (7)

A method for forming a light emitting diode includes: sequentially forming a first semiconductor layer, an active layer, and a second semiconductor layer on a substrate, and electrical properties of the first semiconductor layer and the second semiconductor layer Conversely, forming a trench through the second semiconductor layer, the active layer, and a portion of the first semiconductor layer to define a stacked structure between the trenches; forming a planarization layer on the first semiconductor layer And filling the trench with the second semiconductor layer; forming a hard mask pattern on the planarization layer, the hard mask pattern having a mask region and an opening region, and the opening region corresponds to the trench Performing an oblique ion implantation through the open area such that a sidewall of the first semiconductor layer has a doped region; removing the hard mask pattern and the planarization layer; and removing the doped region to A cavity is formed. The method of forming a light-emitting diode according to claim 1, wherein the width of the open area is smaller than the width of the groove. The method of forming a light-emitting diode according to claim 1, wherein the method of removing the doped region comprises inductively coupled plasma, reactive ion etching, wet etching, or a combination thereof. The method for forming a light-emitting diode according to claim 1, further comprising the step of removing the hard mask pattern and the planarization layer, and forming a step of removing the doped region. A protective layer is on the second semiconductor layer. The method for forming a light-emitting diode according to claim 1, wherein the upper structure of the stacked structure is a rectangle having a long side and a short side, and the concave hole is located only on the long side. A light emitting diode includes: a substrate; a first semiconductor layer is disposed on the substrate, the first semiconductor layer has a first region and a second region, and the first region has a thickness greater than the second region a recess; a sidewall located on the first region of the first semiconductor layer; a light emitting layer on the first region of the first semiconductor layer; and a second semiconductor layer on the light emitting layer And the electrical properties of the first semiconductor layer and the second semiconductor layer are opposite. The light-emitting diode of claim 6, wherein the first view of the first region of the first semiconductor layer is a rectangle having a long side and a short side, and the recess is located only The long side.