TWI442547B - Electrostatic discharge protection circuit - Google Patents

Description

Electrostatic protection circuit

The present invention relates to an electrostatic discharge protection circuit for increasing the voltage operating range of a signal input to an integrated circuit.

Please refer to Figure 1. Fig. 1 is a circuit diagram showing a prior art electrostatic protection circuit 100. The electrostatic protection circuit 100 is coupled to the first end T ₁ , the second end T _{2 ,} and the third end T _{3 of the} integrated circuit 101 to prevent the integrated circuit 101 from being damaged by static electricity. The integrated circuit 101 receives an input signal S _IN through the first terminal T ₁ ; the second terminal T _{2 of the} integrated circuit 101 is coupled to a voltage source V _DD (for example, the voltage source V _DD provides a voltage V of 3.3V) _DD ); the third terminal T _{3 of the} integrated circuit 101 is coupled to a voltage source V _SS (for example, the voltage source V _SS provides a voltage V _SS of a low potential of 0V). The electrostatic protection circuit 100 includes a P-type channel metal oxide semiconductor (PMOS) transistor Q _P1 and an N-type channel metal oxide semiconductor (NMOS) transistor Q _N1 . The PMOS transistor Q _P1 includes a drain (D), a source (S), a gate (G), and an N-well (W). The source, the gate, and the N-type well region of the PMOS transistor Q _{P1 are} coupled to the second terminal T _{2 of the} integrated circuit 101 , and the drain of the PMOS transistor Q _P1 is coupled to the integrated circuit 101 One end T ₁ . The NMOS transistor Q _N1 includes a drain (D), a source (S), a gate (G), and a P-well (W). The source, the gate, and the P-type well region of the NMOS transistor Q _{N1 are} coupled to the third terminal T _{3 of the} integrated circuit 101 , and the drain of the NMOS transistor Q _N1 is coupled to the integrated circuit 101 One end T ₁ . Thus, the parasitic diode D _{QP1 of the} PMOS transistor Q _P1 is coupled between the first terminal T ₁ and the second terminal T _{2 of the} integrated circuit 101 , and the parasitic diode D _{QN1 of the} NMOS transistor Q _N1 is coupled. Connected between the first end T ₁ and the third end T _{3 of the} integrated circuit 101 (as shown in FIG. 1). Therefore, when positive static electricity is generated at the input terminal END _IN , the parasitic diode D _{QP1 is} turned on, so that the positive static electricity can pass through the turned-on parasitic diode D _QP1 to the voltage source V _DD , so that the electrostatic protection circuit 100 can eliminate the positive Static electricity. When negative static electricity is generated at the input terminal END _IN , the parasitic diode D _{QN1 is} turned on, so that the negative static electricity can pass through the turned-on parasitic diode D _QN1 to the voltage source V _SS , and thus, the electrostatic protection circuit 100 can eliminate negative static electricity.

However high the sum, when the input signal S _IN of the voltage potential than V _DD (3.3V) of the parasitic diode conducting voltage V _FW (about 0.7V) of D _QP1, the parasitic diode D _QP1 is turned on, at this time, A leakage current I _L1 is generated between the input terminal END _IN and the voltage source V _DD , so that the input signal S _{IN is} dissipated from the voltage source V _DD . Similarly, when the potential of the D _QN1 voltage V _SS (3.3V) minus the parasitic diode conduction voltage V _FW (about 0.7V) higher than the input signal S _IN, the parasitic diode D _QN1 turns on, then A leakage current I _L2 is generated between the input terminal END _IN and the voltage source V _SS , so that the input signal S _{IN is} dissipated from the voltage source V _SS . In other words, the voltage operation range of the input signal S _IN of the integrated circuit 101 is limited by the prior art electrostatic protection circuit 100 between (V _SS - V _FW ) ~ (V _DD + V _FW ). In addition, when the potential of the input signal S _IN is not between (V _SS -V _FW )~(V _DD +V _FW ), a leakage current is generated between the input terminal END _IN and the voltage source V _DD (or V _SS ). .

The invention provides an electrostatic protection circuit. The electrostatic protection circuit is coupled between the first end and a second end of an integrated circuit to prevent the integrated circuit from being damaged by static electricity. The electrostatic protection circuit includes a first P-type channel metal oxide semiconductor (PMOS) transistor and a deep N-well N-type channel (N-type channel) Metal oxide semiconductor, NMOS) transistor. The first PMOS transistor includes a drain (D), a source (S), a gate (G), and an N-well. The source of the first PMOS transistor is coupled to the first end of the integrated circuit. The gate of the first PMOS transistor is coupled to the drain of the first PMOS transistor. The N-type well region of the first PMOS transistor is coupled to the drain of the first PMOS transistor. The deep N-well NMOS transistor includes a source (S), a drain (D), a gate (G), a P-well (P-well), and a deep N-well region. The source of the deep N-type well NMOS transistor is coupled to the second end of the integrated circuit. The drain of the deep N-well NMOS transistor is coupled to the drain of the first PMOS transistor. The gate of the deep N-type well NMOS transistor is coupled to the second end of the integrated circuit. The P-well region of the deep N-well NMOS transistor is coupled to the source of the deep N-well NMOS transistor. The deep N-well region of the deep N-well NMOS transistor is used to cover the P-well region. The deep N-well region of the deep N-well NMOS transistor is coupled to a first voltage source.

Please refer to Figures 2 and 3. Fig. 2 is a schematic view showing an electrostatic protection circuit 200 according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view of the electrostatic protection circuit 200. In Fig. 3, N ⁺ represents n-type doping, and P ⁺ represents P-type doping. In the second figure, the electrostatic protection circuit 200 is coupled between the first end T ₁ and the second end T _{2 of the} integrated circuit 101 to prevent the integrated circuit from being damaged by static electricity. The first terminal T _{1 of the} integrated circuit 101 is for receiving the input signal S _IN , and the second terminal T _{2 of the} integrated circuit 101 is coupled to the voltage source V _SS . The electrostatic protection circuit 200 includes a PMOS transistor Q _P1 and a deep N-well NMOS transistor Q _DN . The PMOS transistor Q _P1 includes a drain (D), a gate (G), a source (S), and an N-well (W). The source of the PMOS transistor Q _P1 is coupled to the first terminal T _{1 of the} integrated circuit 101 , the drain of the PMOS transistor Q _P1 , the gate, and the N-well region are coupled to the deep N-well NMOS. Crystal Q _DN . The deep N-type well region NMOS transistor Q _DN includes a drain (D), a gate (G), a source (S), a P-well (W), and a deep N Well area. The drain of the deep N-well NMOS transistor Q _DN is coupled to the drain of the PMOS transistor Q _P1 . Deep N-well region of the NMOS transistor Q _DN of the P-type well region coupled to the source of the N-type deep well region of the NMOS transistor Q _DN extremely deep N-type well region Q _DN of the NMOS transistor source and gate are coupled Connected to the second terminal T _{2 of the} integrated circuit 101. As shown in FIG. 3, the deep N-type well region of the deep N-type well region NMOS transistor Q _DN covers the P-type well region and is coupled to a high-potential voltage source (for example, voltage source V _DD ).

Please refer to Figures 4 and 5. 4 and 5 are schematic views illustrating the operation of the electrostatic protection circuit 200 to eliminate static electricity. In Figure 4, it is assumed that positive static + ESD is generated from the input terminal END _IN . Since the potential of positive static + ESD is very high, the parasitic bipolar transistor BT _{QDN of the} deep N-type well NMOS transistor Q _DN Turn on. In this way, the positive electrostatic + ESD flows through the turned-on parasitic diode D _QP1 and the turned-on parasitic bipolar transistor BT _QDN to the voltage source V _SS , so that the electrostatic protection circuit 200 can eliminate the positive static + ESD. Similarly, in Fig. 5, it is assumed that the negative electrostatic-ESD is generated from the input terminal END _IN , and since the potential of the negative static-ESD is very high, the parasitic bipolar transistor BT _{QDP1 of the} PMOS transistor Q _DP1 is turned on. In this way, the positive charge from the voltage source V _SS through the turned-on parasitic bipolar transistor BT _QDP1 and the turned-on parasitic diode D _QN flow to the input terminal END _IN to neutralize the negative electrostatic-ESD, so that the electrostatic protection circuit 200 can Eliminate negative static - ESD.

Please refer to Figure 6 and Figure 7. 6 and 7 are diagrams for explaining the voltage operation range in which the electrostatic protection circuit 200 increases the input signal S _IN of the integrated circuit 101. In Fig. 6, it is assumed that the input signal S _IN is 1.5 V, and at this time, the parasitic diode D _{QP1 of the} PMOS transistor Q _P1 is turned on. However, since the parasitic diode D _{QDN of the} deep N-type well region NMOS transistor Q _DN is reversely connected to the parasitic diode D _QP1 , the parasitic diode D _{QDN is} turned off. Thus, the input signal S _{IN is} input to the integrated circuit 101 through the first terminal T ₁ and is not affected by the electrostatic protection circuit 200. In Fig. 7, it is assumed that the input signal S _IN is -6 V, and at this time, the parasitic diode D _{QDN of the} deep N-type well region NMOS transistor Q _DN is turned on. However, since the parasitic diode D _{QP1 is} reversely connected to the parasitic diode D _QDN , the parasitic diode D _{QP1 is} turned off. Thus, the input signal S _{IN is} input to the integrated circuit 101 through the first terminal T ₁ and is not affected by the electrostatic protection circuit 200. From the above description, regardless of the potential of the input signal S _IN is higher or lower than source voltage V _SS V _SS voltage provided by the input signal S _IN can be accessed via a first input terminal T ₁ to the integrated circuit 101, not It is affected by the static electricity protection circuit 200. In other words, the electrostatic protection circuit 200 increases the voltage operation range of the input signal S _IN compared to the electrostatic protection circuit 100 of the prior art, and further, the first end T ₁ and the second end T _{2 of the} integrated circuit 101 can be avoided. A leakage current is generated between them.

Please refer to Figure 8, Figure 9, and Figure 10. Fig. 8 is a circuit diagram showing an electrostatic protection circuit 700 according to a second embodiment of the present invention. Compared with FIG. 2, in FIG. 8, the second terminal T _{2 of the} integrated circuit 101 is coupled to the high voltage source V _DD . Fig. 9 is a circuit diagram showing an electrostatic protection circuit 800 according to a third embodiment of the present invention. Compared to FIG. 2, FIG. 9, the product of the second end 101 of the T circuits ₂ for receiving the input signal S _IN, and a first end of the T integrated circuit ₁₀₁₁ is coupled to a voltage source V _SS. Fig. 10 is a circuit diagram showing an electrostatic protection circuit 900 according to a fourth embodiment of the present invention. Compared with FIG. 2, in FIG. 10, the second terminal T _{2 of the} integrated circuit 101 is used to receive the input signal S _IN , and the first terminal T _{1 of the} integrated circuit 101 is coupled to the voltage source V _DD . The structure and working principle of the electrostatic protection circuits 700, 800, and 900 are similar to those of the electrostatic protection circuit 200, and therefore will not be described again. The electrostatic protection circuits 700, 800, and 900 can increase the voltage operating range of the input signal S _IN and can avoid leakage current between the first terminal T ₁ and the second terminal T _{2 of the} integrated circuit 101.

Please refer to Figure 11. Fig. 11 is a view showing the electrostatic protection circuit 1000 according to the fifth embodiment of the present invention. Compared with the electrostatic protection circuit 200, the electrostatic protection circuit 1000 further includes a driving circuit 1010 coupled to the gate of the deep N-type well NMOS transistor Q _DN . The driving circuit 1010 includes a capacitor C and a resistor R. The first end of the capacitor C is coupled to the first end T _{1 of the} integrated circuit 101, and the second end of the capacitor C is coupled to the gate of the deep N-type well NMOS transistor Q _DN . The first end of the resistor R is coupled to the gate of the deep N-type well NMOS transistor Q _DN , and the second end of the resistor R is coupled to the second terminal T _{2 of the} integrated circuit 101 . When positive static + ESD is generated from the input terminal END _IN , since the static electricity is a high frequency, the capacitance C can be regarded as a short circuit. At this time, the gate of the deep N-type well region NMOS transistor Q _DN can receive a high potential voltage through the capacitor C. Thus, the deep N-well NMOS transistor Q _{DN is} turned on, and the speed at which the positive static +ESD flows to the voltage source V _SS increases. Therefore, the electrostatic protection circuit 1000 can eliminate positive static electricity + ESD faster than the electrostatic protection circuit 200.

Please refer to Figure 12. Fig. 12 is a schematic view showing an electrostatic protection circuit 1100 according to a sixth embodiment of the present invention. Compared with the electrostatic protection circuit 200, the electrostatic protection circuit 1100 further includes a driving circuit 1110 coupled to the gate of the deep N-type well NMOS transistor Q _DN . The driving circuit 1110 includes an inverter INV, a capacitor C, and a resistor R. The inverter INV includes a PMOS transistor Q _PINV and an NMOS transistor Q _NINV . The PMOS transistor Q _PINV well region (Well) coupled to the source of PMOS transistor Q _PINV electrode, the source of PMOS transistor Q _PINV electrode coupled to a first terminal T ₁ of the integrated circuit 101, PMOS transistor Q _PINV The drain is coupled to the gate of the deep N-well NMOS transistor Q _DN . NMOS transistor Q _NINV well region coupled to the NMOS transistor Q _NINV the source, the source of the NMOS transistor Q _NINV is coupled to the second terminal 101 of integrated circuit T _2, NMOS Q _NINV crystals of electrically drain The gate is coupled to the deep N-well NMOS transistor Q _DN . The first end of the resistor R is coupled to the first terminal T _{1 of the} integrated circuit 101 , and the second end of the resistor R is coupled to the gate of the PMOS transistor Q _{PINV and} the gate of the NMOS transistor Q _NINV . The first end of the capacitor C is coupled to the gate of the PMOS transistor Q _{PINV and} the gate of the NMOS transistor Q _NINV , and the second end of the capacitor C is coupled to the second terminal T _{2 of the} integrated circuit 101 . When positive static + ESD is generated from the input terminal END _IN , since the static electricity is a high frequency, the capacitance C can be regarded as a short circuit. At this time, the gate of the PMOS transistor Q _{PINV and} the gate of the NMOS transistor Q _NINV pass through the capacitor C to receive the voltage V _SS (0 V), so that the PMOS transistor Q _{PINV is} turned on, and the NMOS transistor Q _{NINV is} turned off. Thus, the inverter INV outputs a high potential voltage, so that the deep N-type well region NMOS transistor Q _{DN is} turned on. Similarly, at this time, the deep N-type well region NMOS transistor Q _DN increases the velocity of positive electrostatic + ESD flow to the voltage source V _SS . That is, the electrostatic protection circuit 1100 can eliminate positive static electricity + ESD faster than the electrostatic protection circuit 200.

In summary, the electrostatic protection circuit provided by the present invention is coupled between the first end and the second end of the integrated circuit to prevent the integrated circuit from being damaged by static electricity. One of the first end and the second end of the integrated circuit is used to allow the integrated circuit to receive an input signal and the other end to be coupled to a voltage source. The electrostatic protection circuit provided by the present invention comprises a PMOS transistor and a deep N-well NMOS transistor. The electrostatic protection circuit can eliminate static electricity through the PMOS transistor and the parasitic diode and parasitic bipolar transistor of the deep N-type well NMOS transistor, and is connected in reverse to the deep N-type well by the parasitic diode of the PMOS transistor. The parasitic diode of the NMOS transistor can avoid leakage current between the first end and the second end of the integrated circuit. Thus, the electrostatic protection circuit can prevent the integrated circuit from being damaged by static electricity and increase the voltage operation range of the signal input to the integrated circuit.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

101. . . Integrated circuit

100, 200, 700, 800, 900, 1000, 1100. . . Electrostatic protection circuit

1010, 1110. . . Drive circuit

BT _QDN , BT _QDP1 . . . Parasitic bipolar transistor

C. . . capacitance

D. . . Bungee

D _QP1 , D _QN1 , D _QN . . . Parasitic diode

END _IN . . . Input

G. . . Gate

I _L1 , I _L2 . . . Leakage current

INV. . . inverter

Q _P1 , Q _N1 , Q _DN , Q _PINV , Q _NINV . . . Transistor

R. . . resistance

S. . . Source

S _IN . . . input signal

T ₁ , T ₂ , 1, 2. . . End point

V _DD , V _SS . . . Voltage

W. . . Well area

+ESD, -ESD. . . Static electricity

Fig. 1 is a circuit diagram showing a prior art electrostatic protection circuit.

Fig. 2 is a view showing the electrostatic protection circuit according to the first embodiment of the present invention.

Fig. 3 is a cross-sectional view showing the electrostatic protection circuit of Fig. 2.

Fig. 4 and Fig. 5 are schematic diagrams showing the operation principle of the static electricity protection circuit of Fig. 2 for eliminating static electricity.

Fig. 6 and Fig. 7 are schematic diagrams showing the voltage operating range of the input signal of the integrated circuit in the electrostatic protection circuit of Fig. 2.

Figure 8 is a circuit diagram showing an electrostatic protection circuit in accordance with a second embodiment of the present invention.

Figure 9 is a circuit diagram showing an electrostatic protection circuit in accordance with a third embodiment of the present invention.

Fig. 10 is a circuit diagram showing an electrostatic protection circuit according to a fourth embodiment of the present invention.

Figure 11 is a view showing the electrostatic protection circuit according to the fifth embodiment of the present invention.

Figure 12 is a schematic view showing an electrostatic protection circuit in accordance with a sixth embodiment of the present invention.

101. . . Integrated circuit

200. . . Electrostatic protection circuit

D. . . Bungee

END _IN . . . Input

G. . . Gate

Q _P1 , Q _DN . . . Transistor

S. . . Source

S _IN . . . input signal

T ₁ , T ₂ . . . End point

V _SS . . . Voltage

W. . . Well area

Claims (7)

An electrostatic protection circuit is coupled between a first end and a second end of an integrated circuit to prevent electrostatic damage to the integrated circuit, the electrostatic protection circuit comprising: a first P-type metal oxide semiconductor ( The P-type channel metal oxide semiconductor (PMOS) transistor includes: a drain; a source coupled to the first end of the integrated circuit; and a gate coupled to the first PMOS transistor The drain electrode; and an N-well (N-well) coupled to the drain of the first PMOS transistor; and a deep N-well N-type metal oxide semiconductor (N a NMOS transistor, comprising: a source coupled to the second end of the integrated circuit; a drain coupled to the drain of the first PMOS transistor; a gate coupled to the second end of the integrated circuit; a P-well (P-well) coupled to the source of the deep N-well NMOS transistor; and a deep N-well The area is used to cover the P-type well region and is coupled to a first voltage source. The electrostatic protection circuit of claim 1, wherein the first voltage source provides a high potential voltage. The electrostatic protection circuit of claim 1, wherein the first end of the integrated circuit is configured to receive an input signal, and the second end of the integrated circuit is coupled to a second voltage source. The electrostatic protection circuit of claim 1, wherein the second end of the integrated circuit is configured to receive an input signal, and the first end of the integrated circuit is coupled to a second voltage source. The electrostatic protection circuit of claim 1, further comprising: a driving circuit coupled to the gate of the deep N-well NMOS transistor. The electrostatic protection circuit of claim 5, wherein the driving circuit comprises: a capacitor comprising a first end coupled to the first end of the integrated circuit, and a second end coupled to the deep N-type The gate of the well NMOS transistor; and a resistor including a first end coupled to the gate of the deep N-well NMOS transistor, and a second end coupled to the integrated circuit Second end. The electrostatic protection circuit of claim 5, wherein the driving circuit comprises: an inverter comprising: a second PMOS transistor comprising: a drain; a source coupled to the integrated circuit a first end; a gate, and an N-type well region coupled to the source of the second PMOS transistor; and a first NMOS transistor, including: a source coupled to the integrated circuit a second end; a drain coupled to the drain of the second PMOS transistor; a gate coupled to the gate of the second PMOS transistor; and a P-well region coupled The first NMOS transistor is coupled to the source of the first NMOS transistor; a resistor comprising: a first end coupled to the first end of the integrated circuit; and a second end coupled to the second PMOS The gate of the crystal and the gate of the first NMOS transistor; and a capacitor comprising: a first end coupled to the second end of the resistor; and a second end coupled to the product The second end of the body circuit.