TWI441451B - Output buffering circuit, amplifier device, and display device with reduced power consumption - Google Patents

Description

Low power consumption driving device, amplifier device, and display device

The embodiments described herein relate to a display device, and more particularly to an output buffer circuit for a driver device, an amplifier device, and a display device using the output buffer circuit.

In general, the development of precision, lightweight, low-power, and high-quality display devices requires low-power loss, high-speed, high-resolution, and large output range liquid crystal display (LCD) devices. It is growing day by day. LCD drivers are commonly composed of a source driver, a gate driver, a controller, and a reference power supply. These source drivers play a particularly important role in meeting these needs, and these source drivers include scratchpads, data latches, digital-to-analog converters (DACs), and output buffers. Device. These output buffers determine the source driver's rate, resolution, voltage range, and power consumption. Since a single wafer has a large number of (typically hundreds) of output buffers built in, each output buffer must occupy only a small area of the wafer while its power consumption must be low enough.

Figure 1 is a schematic illustration of a conventional source driver device. In FIG. 1, a conventional source driver device 100 includes an output buffer circuit 102 and a switching circuit 104.

The output buffer circuit 102 includes a first amplifier circuit 110 and a second amplifier circuit 120. The first amplifier circuit 110 receives the first input signal SI1 input from a D/A converter (not shown) and provides a first output signal SO1 to drive one of the source lines of a display panel. Similarly, the second amplifier circuit 120 receives the second input signal SI2 input from the D/A converter and provides a second output signal SO2 to drive another source line of the display panel.

The first amplifier circuit 110 is coupled between a higher power supply VDDA and a lower power supply VSSA. Typically, the first amplifier circuit 110 includes an input stage (not shown), such as a differential pair, for receiving the first input signal SI1 and the first output signal SO1, and an output stage ( Not shown) for providing the first output signal SO1, wherein the input stage and the output stage are both coupled between the higher power supply VDDA and the lower power supply VSSA. Similarly, the second amplifier circuit 120 is coupled between the higher power supply VDDA and the lower power supply VSSA. The second amplifier circuit 120 typically includes an input stage (not shown), such as a differential pair, for receiving the second input signal SI2 and the second output signal SO2, and an output stage (not The second output signal SO2 is provided, wherein the input stage and the output stage are both coupled between the higher power supply VDDA and the lower power supply VSSA. Therefore, both the first and second amplifier circuits 110 and 120 can drive the display panel over an output driving range between VSSA and VDDA.

Suppose that for a long time, < i _{ch arg e 1} 〉=< i _{disch arg e 1} 〉, where < i _{ch arg e 1} 〉 and 〈 i _{disch arg e 1} 〉 respectively represent the average charging current and the average discharge current, then The average power consumption of the output stage of an amplifier circuit 110 can be expressed as:

< P 〉=< i _{ch arg e 1} 〉×( VDDA−V _{O 1} )+< i _{disch arg e 1} 〉×( V _{O 1} - VSSA )=< i _{ch arg e 1} 〉×( VDDA−VSSA )

Where V _{O 1} represents the voltage of the first output signal SO1.

It is also assumed that for a long time, < i _{ch arg e 2} 〉=< i _{disch arg e 2} 〉, where < i _{ch arg e 2} 〉 and 〈 i _{disch arg e 2} 〉 represent the average charging current and the average discharge current, respectively. The average power consumption of the output stage of the second amplifier circuit 120 can be expressed as:

< P 〉=< i _{ch arg e 2} 〉×( VDDA−V _{O 2} )+< i _{disch arg e 2} 〉×( V _{O 2} - VSSA )=< i _{ch arg e 2} 〉×( VDDA−VSSA )

Where V _{O 2} represents the voltage of the second output signal SO2.

The switching circuit 104 includes a first switch SW1 and a second switch SW2, both of which are controlled by a control signal SCTRL. The first switch SW1 controls the coupling between the first amplifier circuit 110 and the source line on the display panel. Similarly, the second switch SW2 controls the coupling between the second amplifier circuit 120 and the source line on the display panel. By switching the control signal SCTRL between different levels, the first and second amplifier circuits 110 and 120 can alternately drive different source lines on the display panel.

In general, the constraints considered when designing the source driver device 100 may include: the drive capability of the source driver for a large load on the display panel, the dynamic and steady state power consumption of the source driver device 100, and the design of the source driver 100. Complexity with manufacturing, and/or other features of the structure/operation of the buffer circuit. However, the source driver device 100 described above does not ideally meet all of the above design constraints, particularly power consumption.

Here, a buffer circuit of a driver device having low power consumption, an amplifier device, and a display device to which the buffer circuit is applied are described.

According to one aspect, an output buffer circuit of a driver device for a display includes a first amplifier circuit including a first input stage coupled between a higher power supply and a lower power supply, and including a a first output stage coupled between the higher power source and a first intermediate power source, wherein the first intermediate power source is higher than the lower power source, and including a second amplifier circuit including a second input stage It is coupled between the higher power source and the lower power source, and includes a second output stage coupled between a second intermediate power source and the lower power source, wherein the second intermediate power source is lower than the comparison High power supply.

According to another aspect, an amplifier device includes an input stage coupled between a first and a second power source, and an output stage coupled between the third and fourth power sources, wherein the third and fourth power sources At least one of them is different from any of the first and second power sources.

The above and other features, aspects, and embodiments are described in the following embodiments.

2 is a schematic diagram of an example of a source driver device in accordance with an embodiment. In FIG. 2, a source driver device 200 can be configured to drive a display panel (not shown) and can include an output buffer circuit 202 and a switching circuit 204.

The output buffer circuit 202 can include a first amplifier device 210 and a second amplifier device 220. The first amplifier device 210 can be configured to receive the first input signal SI1 output by a D/A converter (not shown), and provide the first output signal SO1 at a first output node O1. The display panel is driven on the output drive range (ie, the voltage range of the first output signal SO1). Similarly, the second amplifier device 220 can be configured to receive the second input signal SI2 output by the D/A converter, and provide the second output signal SO2 at a second output node O2 for the second output. The display panel is driven over the drive range (ie, the voltage range of the second output signal SO2). In a preferred case, the first output driving range occupies an upper portion of an overall output driving range, and the second output driving range occupies a lower portion of the overall output driving range. In a better case, the first and second output drive ranges respectively occupy an upper half and a lower half of an overall output drive range.

In FIG. 2, switching circuit 204 can be coupled between first and second amplifier circuits 210 and 220 and the display panel, and can be configured to control the first and second amplifier circuits 210 and 220 and the display panel The coupling between the source lines. For example, the switching circuit 204 can be implemented as a multiplexer including a first switch SW1 and a second switch SW2, and the first and second switches SW1 and SW2 are controlled by a control signal SCTRL. When the control signal SCTRL corresponds to the first level, the first switch SW1 can be coupled to the first source line input FIRST_IN on the display panel, and when the control signal SCTRL corresponds to the second level, the first switch SW1 can A second source line input SECOND_IN coupled to the display panel. Conversely, when the control signal SCTRL corresponds to the first level, the second switch SW2 can be coupled to the second source line input SECOND_IN on the display panel, and when the control signal SCTRL corresponds to the second level, the second switch SW2 can be coupled to the first source line input FIRST_IN on the display panel. Since the control signal SCTRL is switched between the first and second levels, the first and second amplifier circuits 210 and 220 can be alternately coupled to different source lines between the first and second source line inputs FIRST_IN and SECOIND_IN. Input to drive different source lines.

The first amplifier 210 can include a first input stage 212 and a first output stage 214. The first input stage 212 can include a higher power supply node P11 that can be coupled to a higher power supply VDDA and a lower power supply node P12 that can be coupled to a lower power supply VSSA.

The first output stage 214 can include a higher power supply node P13 that can be coupled to the higher power supply VDDA and that includes an intermediate power supply node P14 that can be coupled to a first intermediate power supply VCA1. The level of the first intermediate power source VCA1 may be higher than the level of the lower power source. For example, the first intermediate power source VCA1 can be between VSSA and VDDA, and is preferably equal to (VDDA + VSSA)/2.

Additionally, the first input stage 212 can include a non-inverting input node IN1(+) coupled to the first input signal SI1 and including an inverting input node IN1(-) coupled to the first Output node O1. Here, for example, the first amplifier circuit 210 can be configured to have a unity gain (Unity Gain).

The first input stage 212 is configurable to operate in accordance with the voltage level of the non-inverting input node IN1 (+) and the inverting input node IN1 (-). In addition, a first input stage 212 coupled between the higher power supply VDDA and the lower power supply VSSA can be configured to operate in an operating range, and the operating range can be from the higher power supply VDDA and the lower power supply VSSA To be limited. For example, the first input stage 212 can include an amplifying circuit, such as a differential amplifier including a differential pair. In the case where the first amplifier circuit 210 is constructed as an amplifier constituting unity gain, the input transistor of the first input stage 212 can be optimized to operate in the first output drive range described above. For example, the differential pair can include N-type differential input transistors that can operate over a first output drive range that occupies an upper portion of the overall drive range.

A first output stage 214, which may be coupled directly or indirectly to the first input stage 212, may be configured to provide a first output signal SO1 to drive a display panel. For example, the first output stage 214 can include a drive circuit that drives the display panel based on one of the output signals of the first input stage 212. The first output stage 214 can include a charging path between the higher power supply node P13 and the first output node O1, and a discharge path between the first output node O1 and the intermediate power supply node P14. Therefore, the first output stage 214 used to drive the first output driving range of the display device, that is, the driving range of the first output signal SO1, can be limited by the first intermediate power source VCA1 and the higher power source VDDA.

The charging path can be practiced as a current source that provides a current flowing from the higher power supply node P13 to the first output node O1 to charge the first output node O1. The discharge path can be practiced as a current sink that allows current to flow from the first output node O1 into the intermediate power supply node P14 to discharge the first output node O1.

For example, when the level of the first input signal SI1 at the non-inverting input node IN1(+) is higher than the first output signal SO1 coupled to the inverting input node IN1(-), the first output stage 214 The charging path is turned on, and the output load on the display panel is charged to raise the level of the first output signal SO1. Conversely, when the level of the first input signal SI1 at the non-inverting input node IN1(+) is lower than the first output signal SO1 coupled to the inverting input node IN1(-), the discharge path of the first output stage 214 It will conduct and discharge the output load on the display panel, thereby lowering the level of the first output signal SO1.

The second amplifier 220 can include a second input stage 222 and a second output stage 224. The second input stage 222 can include a higher power supply node P21 that can be coupled to the higher power supply VDDA as described above and a lower power supply node P22 that can be coupled to the lower power supply VSSA.

The second output stage 224 can include a higher power supply node P23 that can be coupled to a second intermediate power supply VCA2 and that includes an intermediate power supply node P24 that can be coupled to the lower power supply VSSA. The level of the second intermediate power source VCA2 may be lower than the level of the higher power source. For example, the second intermediate power source VCA2 can be between VSSA and VDDA, and is preferably equal to (VDDA + VSSA)/2. Here, for example, the output stages 212 and 224 can share a common power source that is equidistant from the higher and lower power supplies.

The second input stage 222 can include a non-inverting input node IN2(+) coupled to the second input signal SI2 and including an inverting input node IN2(-) coupled to the second output node O2. Here, for example, the second amplifier circuit 220 can be configured to have a unity gain.

The second input stage 222 is configurable to operate in accordance with the voltage level of the non-inverting input node IN2(+) and the inverting input node IN2(-). In addition, a second input stage 222, coupled between the higher power supply VDDA and the lower power supply VSSA, can be configured to operate in an operating range, and the operating range can be from the higher power supply VDDA and the lower power supply VSSA To be limited. For example, the second input stage 222 can include an amplifying circuit, such as a differential amplifier including a differential pair. In the case where the second amplifier circuit 220 is constructed as an amplifier that constitutes a unity gain, the input transistor of the second input stage 222 can be optimized to operate in the second output drive range described above. For example, the differential pair can include a P-type differential input transistor that can operate over a second output drive range that occupies a lower portion of the overall drive range.

A second output stage 224, which may be coupled directly or indirectly to the second input stage 222, may be configured to provide a second output signal SO2 to drive the display panel. For example, the second output stage 224 can include a driver circuit for driving the display panel according to one of the output signals of the second input stage 222. The second output stage 224 can include a charging path between the second intermediate power node P23 and the second output node O2, and a discharge between the second output node O2 and the lower power node P24. path. Therefore, the second output stage 224 is used to drive the second output driving range of the display device, that is, the driving range of the second output signal SO2, which can be limited by the second intermediate power source VCA2 and the lower power source VSSA.

The charging path can be practiced as a current source that provides a current flow from the intermediate power supply node P23 to the second output node O2 to charge the second output node O2. The discharge path can be practiced as a current sink that allows current to flow from the second output node O2 into the lower power supply node P24 to discharge the second output node O2.

For example, when the level of the second input signal SI2 located at the non-inverting input node IN2(+) is higher than the second output signal SO2 coupled to the inverting input node IN2(-), the second output stage 224 The charging path is turned on, and the output load on the display panel is charged to raise the level of the second output signal SO2. Conversely, when the level of the second input signal SI2 at the non-inverting input node IN2(+) is lower than the second output signal SO2 coupled to the inverting input node IN2(-), the discharge path of the second output stage 224 It will conduct and discharge the output load on the display panel to lower the level of the second output signal SO2.

Benefiting from the power arrangement described above for the first output stage 214, the first amplifier circuit 210 can be driven by the output of the first amplifier circuit 110 (FIG. 1) due to its output drive range (limited between VCA1 and VDDA). The range (limited between VCCA and VDDA) is small and is reduced in dynamic power consumption. More specifically, the input stages of both the first amplifier circuits 110 and 210 operate at an operating range limited between VDDA and VSSA and thus have the same power consumption. On the other hand, the first output stage 214 of the first amplifier circuit 210 can have the same dynamic power consumption for the charging process, but has a lower power consumption for the discharging process. In general, the first amplifier circuit 210 can operate with a smaller total power consumption.

In FIG. 2, the first input stage 212 occupies a lesser role in the total power consumption of the first amplifier circuit 210 because the first output stage 212 operates with a steady state current, as compared to The steady state current can be much lower in terms of the operating current of the first output stage 214 that the display panel must have sufficient drive capability. Since the first output stage 214 contributing to the reduction in dynamic power consumption is the dominant position of the total power consumption of the first amplifier circuit 210, the total power consumption of the first amplifier circuit 210 can be saved in a considerable proportion. .

For example, in the case of VCA1=(VDDA+VSSA)/2, and assuming long time, < i _{ch arg e 1} 〉=< i _{disch arg e 1} 〉, where < i _{ch arg e 1} 〉 And < i _{disch arg e 1} > represents the average charging current and the average discharging current, respectively, and the average power consumption of the first output stage 214 in the first amplifier circuit 210 is:

< P 〉=< i _{ch arg e 1} 〉×( VDDA−V _{O 1} )+< i _{disch arg e 1} 〉×( V _{O 1} - VCA 1)=< i _{ch arg e 1} 〉×( VDDA-VCA 1 )=< i _{ch arg e 1} 〉×( VDDA-VSSA )/2.

As a result, the first output stage 214 can have only half the power consumption compared to the output stage of the first amplifier circuit 110 (in FIG. 1).

Similarly, benefiting from the power arrangement described above for the second output stage 224, the second amplifier circuit 220 may be driven by its output drive range (limited between VSSA and VCA2) than the second amplifier circuit 120 (FIG. 1). The output drive range (limited between VCCA and VDDA) is small and is reduced in dynamic power consumption. More specifically, the input stages of both of the second amplifier circuits 120 and 220 operate at a range limited to between VDDA and VSSA and thus have the same power consumption. On the other hand, the second output stage 224 of the second amplifier circuit 220 can have the same dynamic power consumption for the discharge process, but has a lower power consumption for the charging process. In general, the second amplifier circuit 220 can operate with a smaller total power consumption.

In FIG. 2, the second input stage 222 occupies a lesser role in the total power consumption of the second amplifier circuit 220 because the second input stage 222 operates with a steady state current, as compared to The steady state current can be much lower in terms of the operating current of the second output stage 224 that the display panel must have sufficient drive capability. Since the second output stage 224 contributing to the reduction in dynamic power consumption is the dominant position of the total power consumption of the second amplifier circuit 220, the total power consumption of the second amplifier circuit 220 can be saved by a considerable proportion. .

For example, in the case of VCA2=(VDDA+VSSA)/2, and assuming that for a long time, < i _{ch arg e 2} 〉=< i _{disch arg e 2} 〉, where < i _{ch arg e 2} 〉 And < i _{disch arg e 2} > represents the average charging current and the average discharging current, respectively, and the average power consumption of the second output stage 224 in the second amplifier circuit 220 is:

< P 〉=< i _{ch arg e 2} 〉×( VCA 2- V _{O 2} )+< i _{disch arg e 2} 〉×( V _{O 2} - VSSA )=< i _{ch arg e 2} 〉×( VDDA-VCA 2 )=< i _{ch arg e 2} 〉×( VDDA-VSSA )/2.

As a result, the second output stage 224 can have only half the power consumption compared to the output stage of the second amplifier circuit 120 (in FIG. 1).

In summary, since the first output stage 214 has the above-described discharge path coupled to the first intermediate power source VCA1 instead of being coupled to the lower power source VSSA, the dynamic power consumption of the first amplifier circuit 210 during the discharge process can be effectively saved. Moreover, since the second output stage 224 has the above-described charging path coupled to the second intermediate power source VCA2 instead of being coupled to the higher power source VDDA, the dynamic power consumption of the second amplifier circuit 220 charging process can be effectively saved. Overall, the total power consumption of the source driver device 200 can be effectively reduced compared to the conventional source driver device 100.

Although the first and second amplifier circuits 210 and 220 described above are shown as unity gain amplifier circuits, other configurations are possible. The only requirement may be that one of the amplifier circuits includes an input stage coupled to VSSA and VDDA and an output stage coupled between VCA1 (greater than VSSA) and VDDA, and the other amplifier includes an input stage coupled to VSSA and VDDA. And an output stage coupled between VSSA and VCA2 (below VDDA). Therefore, a variety of different amplifier circuits, such as inverting amplifier circuits, can be used.

Figure 3 is another example source driver device in accordance with another embodiment. In FIG. 3, a source driver device 300 can be configured to include an output buffer circuit 302 including a first amplifier circuit 310 and a second amplifier circuit 320, and a switching circuit 204. Here, the source driver device 300 can be substantially similar to the source driver device 200 (in FIG. 2), except that the first and second amplifier circuits 310 and 320 can be configured as inverting amplifier circuits instead of unity gain amplifiers. Circuits 210 and 220 (in Figure 2). Similar elements and nodes in Figures 2 and 3 are labeled with the same reference numerals and symbols.

Substantially similar to the first and second amplifier circuits 210 and 220 (in FIG. 2), the first amplifier circuit 310 can be configured to provide a first output signal SO1 for a first output drive limited by VCA1 and VDDA. Above the range, a display panel is driven, and the second amplifier circuit 320 can be configured to provide a second output signal SO2 to drive the display panel over a second output drive range limited by VSSA and VCA2.

The first amplifier circuit 310 can include two resistors R11 and R12, and an amplifier circuit 210. The resistor R11 can be coupled between a first input signal SI1 and one of the inverting input nodes IN1(-) of the first amplifier circuit 210. Resistor R12 can be coupled between the inverting input node IN1(-) and one of the output nodes O1 of the first amplifier circuit 210. Therefore, the first amplifier circuit 310 can have a gain that depends on the resistors R11 and R12.

The second amplifier circuit 320 can include two resistors R21 and R22, and an amplifier circuit 220. The resistor R21 can be coupled between a second input signal SI2 and one of the inverting input nodes IN2(-) of the first amplifier circuit 220. Resistor R22 can be coupled between the inverting input node IN2(-) and one of the output nodes O2 of the second amplifier circuit 220. Therefore, the second amplifier circuit 320 can have a gain that depends on the resistors R21 and R22.

Since the first and second amplifier circuits 320 and 330 hold the first and second amplifier circuits 210 and 220, respectively (in FIG. 2), the power consumption of the source driver device 300 (in FIG. 3) can be used for similar reasons. And lower.

Figure 4 is a schematic block diagram showing an exemplary display device in accordance with one embodiment. In FIG. 4, a display device 400 can employ the source driver device 200 or 300 described above, and can include a source driver 410 and a display panel 420. The display panel 420 can include a plurality of source lines including source lines SL1 and SL2, and a plurality of gate lines, that is, GL1 to GLn, where n is a non-zero integer. The source driver 410 can be configured to drive the source lines on the display panel 420, and can utilize the source driver device 200 (in FIG. 2) or the source driver device 300 (in FIG. 3). ) to practice. Specifically, the source driver 410 can include an output buffer circuit 420, which can be implemented as the output buffer circuit 202 (in FIG. 2) or the output buffer circuit 302, and the switching circuit 204 described above (in the second Figure or Figure 3).

Although the source driver devices 200 and 300 in accordance with the above exemplary embodiments are described as being used to drive a display panel, the source driver devices 200 and 300 can also be used in a variety of different applications.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100‧‧‧Source driver device

102‧‧‧Output buffer circuit

104‧‧‧Switching circuit

110‧‧‧First amplifier circuit

120‧‧‧Second amplifier circuit

200‧‧‧Source driver device

202‧‧‧Output buffer circuit

204‧‧‧Switching circuit

210‧‧‧First amplifier circuit

212‧‧‧First input stage

214‧‧‧First output stage

220‧‧‧Second amplifier circuit

222‧‧‧second input stage

224‧‧‧second output stage

300‧‧‧Source driver device

302‧‧‧Output buffer circuit

310‧‧‧First amplifier circuit

320‧‧‧Second amplifier circuit

IN(-), IN1(-), IN2(-)‧‧‧ Inverting input nodes

IN(+), IN1(+), IN2(+)‧‧‧ non-inverting input nodes

FIRST_IN‧‧‧First source line input

P11, P13, P21‧‧‧high power nodes

P12, P22, P24‧‧‧ lower power nodes

P14, P23‧‧‧ intermediate power node

R11, R12, R21, R22‧‧‧ resistance

SCTRL‧‧‧ control signal

SECOND_IN‧‧‧Second source line input

SI1‧‧‧ first input signal

SI2‧‧‧ second input signal

SO1‧‧‧ first output signal

SO2‧‧‧ second output signal

SW1‧‧‧ first switch

SW2‧‧‧second switch

VCA1‧‧‧ first intermediate power supply

VCA2‧‧‧second intermediate power supply

VDDA‧‧‧high power supply

VSSA‧‧‧lower power supply

The various features, functions, and embodiments of the present invention may be best understood from the foregoing detailed description, Block diagram of the device.

Fig. 2 is a timing chart showing an embodiment of a waveform of a representative signal of the display device 100 of Fig. 1.

Figure 3 is another example source driver device in accordance with another embodiment.

Figure 4 is a schematic block diagram showing an exemplary display device in accordance with one embodiment.

200. . . Source driver device

202. . . Output buffer circuit

204. . . Switching circuit

210. . . First amplifier circuit

212. . . First input stage

214. . . First output stage

220. . . Second amplifier circuit

222. . . Second input stage

224. . . Second output stage

IN1(-), IN2(-). . . Inverting input node

IN1(+), IN2(+). . . Non-inverting input node

FIRST_IN. . . First source line input

P11, P13, P21. . . Higher power node

P12, P22, P24. . . Lower power node

P14, P23. . . Intermediate power node

SCTRL. . . Control signal

SECOND_IN. . . Second source line input

SI1. . . First input signal

SI2. . . Second input signal

SO1. . . First output signal

SO2. . . Second output signal

SW1. . . First switch

SW2. . . Second switch

VCA1. . . First intermediate power supply

VCA2. . . Second intermediate power supply

VDDA. . . Higher power supply

VSSA. . . Lower power supply

Claims (16)

An output buffer circuit of a driver device for a display, comprising: a first amplifier circuit comprising: a first input stage coupled between a higher power source and a lower power source; a first output stage, The first intermediate power source is coupled to the first intermediate power source and the first intermediate power source is higher than the lower power source; the first resistor is coupled to the first input signal and the first input Between the stages; and a second resistor coupled between the first input stage and the first output stage; and a second amplifier circuit comprising: a second input stage coupled to the second input stage Between the high power source and the lower power source; and a second output stage coupled between the second intermediate power source and the lower power source, the second intermediate power source being lower than the higher power source; a third resistor The third resistor is coupled between a second input signal and the second input stage; and a fourth resistor coupled between the second input stage and the second output stage. The output buffer circuit of the driver device of claim 1, wherein the first and second input stages are configured to receive the first and second input signals, respectively. number. The output buffer circuit of the driver device of claim 2, wherein the first and second output stages are configured to respectively provide a first output signal on the first output driving range and a second output driving range. The second output signal. The output buffer circuit of the driver device of claim 3, wherein the first output driving range is limited by the first intermediate power source and the higher power source, and the second output driving range is determined by the lower power source With this second intermediate power source is limited. The output buffer circuit of the driver device of claim 1, wherein the first and second intermediate power sources are a universal power source equidistant from the higher and lower power sources. The output buffer circuit of the driver device of claim 1, wherein the first output stage and the second output stage alternately drive different source lines of a display panel. The output buffer circuit of the driver device of claim 1, wherein the first output stage comprises: an output node to provide a first output signal; and a discharge path from the output node to the first Intermediate power supply. An output buffer circuit of a driver device as claimed in claim 1 The second output stage includes: an output node to provide a second output signal; and a charging path including a current source, the current source providing a current flowing from the second intermediate power source to the output node. The output buffer circuit of the driver device of claim 1, wherein the first output stage provides a first output signal on an upper half of the overall output drive range, and the second output stage provides a first output stage a second output signal on the lower half of the overall output drive range. The output buffer circuit of the driver device of claim 1, wherein the output buffer circuit is further coupled to a switching circuit configured to control the first and second amplifier circuits of the output buffer circuit Coupling between a plurality of source lines of a display panel. A display device comprising: a display panel having a plurality of source lines; and a source driver having an output buffer circuit, the output buffer circuit comprising: a first amplifier circuit comprising: a first An input stage coupled between a higher power source and a lower power source; a first output stage coupled to the higher power source and a first Between the intermediate power sources, the first intermediate power source is higher than the lower power source; a first resistor coupled between a first input signal and the first input stage; and a second resistor, the second resistor a second resistor coupled between the first input stage and the first output stage; and a second amplifier circuit comprising: a second input stage coupled between the higher power source and the lower power source; a second output stage coupled between a second intermediate power source and the lower power source, the second intermediate power source being lower than the higher power source; a third resistor coupled to a second input Between the signal and the second input stage; and a fourth resistor coupled between the second input stage and the second output stage. The display device of claim 11, wherein the first and second input stages are configured to receive the first and second input signals, respectively, and the first and second output stage configurations are respectively provided to provide a first output signal on the output drive range and a second output signal on the second output drive range. The display device of claim 12, wherein the first output driving range is limited by the first intermediate power source and the higher power source, and the second output driving range is determined by the lower power source and the second The intermediate power supply is limited. The display device of claim 11, wherein the first and second intermediate power sources are a universal power source equidistant from the higher and lower power sources. The display device of claim 11, wherein the source driver further comprises a switching circuit configured to control coupling between the first and second amplifier circuits and the plurality of source lines of the display panel . The display device of claim 11, wherein the second output stage comprises: an output node to provide the second output signal; and a charging path including a current source, the current source providing a The current from the intermediate power supply to the output node.