TWI440146B - A semiconductor package structure that avoids mold leakage and contamination to a built-in heat sink - Google Patents

Description

A semiconductor package structure that avoids mold leakage and contamination to a built-in heat sink

The present invention relates to packaging techniques for semiconductor devices, and more particularly to a semiconductor package construction that avoids mold contamination contamination to a built-in heat sink.

With the continuous advancement of semiconductor process technology, the processing speed and functional requirements of the wafer are also increased. The size of the wafer is not only smaller and smaller, and the heat generated during operation is relatively increased. For example, the heat generated during the operation of the wafer cannot be effectively released. Will significantly affect the performance and service life of semiconductor wafers. Moreover, the semiconductor package is coated with a mold with a poor thermal conductivity of the mold, and it is easy to affect the reliability of the wafer due to the inefficient heat dissipation.

In order to improve the heat dissipation efficiency of the semiconductor package structure, a technique of attaching a heat sink (heat sink, heat block) to the semiconductor package structure has been proposed. As shown in FIG. 1 , a conventional semiconductor package structure 100 having a heat sink mainly includes a substrate 110 , a wafer 120 disposed on the substrate 110 , a molding compound 160 , and a bonding layer 160 . The heat sink 150. The substrate 110 has an upper surface 111 and a lower surface 112. The active surface of the wafer 120 has a plurality of pads 123. The wafer 120 is disposed on the upper surface 111 of the substrate 110, and the pads 123 are electrically connected to the substrate 110 by a plurality of bonding wires 130, and the wafer 120 is coated with the molding compound 160. The bonding wires 130 and the upper surface 111 of the substrate 110. After the molding compound 160 is molded, the bottom surface 153 of the heat sink 150 is attached to the outer surface of the molding compound 160 by an adhesive layer 140, and the top of the heat sink 150 is attached. The face 152 and the peripheral side 151 are exposed outside of the molding compound 160.

However, the semiconductor package structure 100 described above still has several disadvantages, one of which is that the peripheral side surface 151 of the heat sink 150 is exposed outside the mold sealing body 160, and the heat sink 150 is easily produced at the joint with the mold sealing body 160. Peeling phenomenon. In addition, the heat sink 150 of the semiconductor package structure 100 is disposed after the array molding process, and a large-sized heat sink is attached to the mold-sealing gel after the molding, and then the monomer is further processed. The singulation step, so the cutting blade is directly cut into a large-sized heat sink. Since the heat sink is made of a copper or aluminum heat-conducting metal, the cutting knife may cause wear when the cutting time and the number of times are accumulated.

In addition, a semiconductor package structure having a built-in heat sink having a pin is proposed. For example, in Chinese Patent Publication No. 387117, the peripheral edge of the heat sink is provided with a pin, and the pin of the heat sink is made of conductive rubber or silver glue. Connected to the substrate, and the central heat sink portion of the heat sink is supported above the wafer and the substrate. After the molding operation, the peripheral edge of the heat sink is covered in the mold sealing body, but the top surface of the central heat dissipation plate portion of the heat sink should expose the molding adhesive to improve the heat dissipation efficiency. However, during the molding operation of forming the molding compound, the top surface of the central heat dissipation plate portion of the heat dissipation fin is not easily flattened to the mold cavity due to the work tolerance generated by the heat sink fixed on the substrate, thereby causing the mold flow to overflow to the heat dissipation. The film is exposed on the top surface, and the phenomenon of flash is generated, which not only affects the appearance of the finished product, but also reduces the heat dissipation area and reduces the heat dissipation efficiency. Furthermore, the heat sink is formed by a stamping method, and the heat sink may form an unnecessary roll on the edge after the forming, which may cause the exposed top surface of the heat sink to be uneven, and may also affect the exposed top surface. In the sealing operation, it closely adheres to the top surface of the cavity of the upper mold. Some people have tried to set the peripheral ring groove on the exposed top surface of the built-in heat sink. Although the formation area and shape of the overflow glue can be controlled, the mold discharge will also flow into the surrounding ring groove, causing contamination of the exposed top surface of the heat sink. The change in metallic color, if further processed by the overflow of the glue, will increase the packaging cost and lead to an increase in process complexity.

In view of the above, the main object of the present invention is to provide a semiconductor package structure that avoids the leakage of the mold over-filled to the built-in heat sink, and can avoid the molding overfill of the mold-molding gel to the top surface of the built-in heat sink, and improve the overflow. The phenomenon of glue.

A second object of the present invention is to provide a semiconductor package structure that avoids contamination of a mold overfill to a built-in heat sink, so that the heat sink does not have a pin, and the wire can be prevented from being affected by the mold flow to generate a punch line.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure for avoiding contamination of a mold to a built-in heat sink, and mainly comprises a substrate, a wafer, a plurality of bonding wires, a coating layer, a built-in heat sink and a molding compound. The wafer is disposed on the substrate, and the wafer has an active surface and a plurality of pads on the active surface. The bonding wires electrically connect the pads to the substrate. The blanketant layer is formed on the wafer. The built-in heat sink is disposed above the wafer by the wire coating layer, and the peripheral side surface of the built-in heat sink is embedded in the wire coating layer. The mold encapsulation system is formed on the substrate to cover the wafer and the bonding wires to expose a top surface of the built-in heat sink, and the coating adhesive layer is spaced apart between the built-in heat sink and the molding compound Between the two, the top surface of the built-in heat sink is prevented from being contaminated by the molding gel which forms the molding compound.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor package structure, the line coating layer may have an exposed side surface surrounding the peripheral side of the built-in heat sink so that the mold sealing body does not directly contact the built-in heat sink.

In the foregoing semiconductor package structure, the peripheral side surface of the built-in heat sink may be partially covered by the wire coating layer to form a gap of the glue not on the top surface.

In the foregoing semiconductor package construction, the wire coating layer can have a smaller Young's modulus and better thermal conductivity than the molding compound system.

In the aforementioned semiconductor package structure, the built-in heat sink may not have a bonding leg supported by the substrate.

In the foregoing semiconductor package structure, the top surface of the built-in heat sink may be smaller in size than an upper surface of the substrate covered by the mold seal.

In the foregoing semiconductor package structure, the material of the built-in heat sink may be selected from one of copper, aluminum, and germanide.

In the foregoing semiconductor package structure, the wire bonding layer is adhered to the active surface of the wafer and partially covers the bonding wires.

In the above semiconductor package structure, the substrate may have a slot through which the bonding wires are electrically connected to the substrate, and the bonding layer is adhered to the back surface of the wafer.

It can be seen from the above technical solution that the semiconductor package structure of the present invention for avoiding the contamination of the overmold to the built-in heat sink has the following advantages and effects:

First, the special combination of the coating layer, the built-in heat sink and the molding compound can be used as one of the technical means, and the formation of the coating layer can be avoided by spacing the coating layer between the built-in heat sink and the molding compound. The die seal of the molding compound is contaminated to the top surface of the built-in heat sink to affect the heat dissipation efficiency and the package appearance.

Second, the special combination of the covered glue layer, the built-in heat sink and the molding gel can be used as one of the technical means, and a part of the bonding wire is covered by the coating glue layer and the heat sink is embedded in the coating layer. Therefore, the covering glue layer can effectively support the built-in heat sink without the pins, and can ensure that the bonding wire is not affected by the mold flow to generate the punching line.

Third, the special combination of the built-in heat sink and the molding gel can be used as one of the technical means, wherein the top surface of the built-in heat sink is smaller than the surface of the substrate covered by the molding gel, in the singulation cutting step It does not cut into the heat sink without wearing the cutting tool.

Fourthly, the special combination of the wafer, the built-in heat sink and the overlying adhesive layer can be used as one of the technical means, and the built-in heat sink and the active surface adhered to the wafer are covered by the covered adhesive layer instead of the conventional one. The poor thermal conductivity of the mold encapsulant covers the heat sink and the wafer, and the thermal energy of the wafer can be directly discharged from the active surface to the built-in heat sink to achieve higher heat dissipation efficiency.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to a first embodiment of the present invention, a semiconductor package structure for avoiding mold leakage contamination to a built-in heat sink is illustrated in a cross-sectional view of FIG. 2 and a top plan view of FIG. The semiconductor package structure 200 mainly includes a substrate 210, a wafer 220, a plurality of bonding wires 230, a coating layer 240, a built-in heat sink 250, and a molding compound 260. The built-in heat sink 250 refers to a heat sink that is simultaneously molded with the wafer, and is built in the mold seal 260 to expose only the top surface of the heat sink, instead of being installed in the mold after the mold is sealed. The encapsulant 260 has the entire exposed external heat sink.

As shown in FIG. 2, the substrate 210 has an upper surface 211 and a lower surface 212. The upper surface 211 is formed by the molding compound 260. The lower surface 212 can be provided with a plurality of external terminals 270, for example. Solder balls for bonding to the external surface. Typically, the substrate 210 is a printed circuit board and is provided with a single-sided or double-sided electrically conductive line. When the substrate 210 is a multi-layer board, a plurality of plated through holes (not shown) may be further included. In addition, the substrate 210 can also be selected from a printed circuit board, a lead frame, a circuit film, or various wafer carriers.

As shown in FIG. 2, the wafer 220 is disposed on the upper surface 211 of the substrate 210, and can utilize a double-sided PI tape, a liquid epoxy adhesive, a pre-form, a B-stage adhesive, or It is a Die Attach Material (DAM) to adhere the wafer 220 to the upper surface 211 of the substrate 210. The wafer 220 has an active surface 221, a back surface 222 and a plurality of pads 223 on the active surface 221. The material of the wafer 220 can be tantalum, gallium arsenide or other semiconductor materials. The active surface 221 is formed with various integrated circuit components and electrically connected to the pads 223. The wafer 220 generates thermal energy during operation. The pads 223 can be disposed on a single side, two corresponding sides, four sides, or a central position of the active surface 222 of the wafer 220. In this embodiment, the pads 223 are disposed on the two corresponding sides, and the pads 223 are electrically connected to the substrate 210 by using the bonding wires 230. The bonding wires 230 may be formed by a metal wire formed by a wire bonding process, and may be made of gold or a similar highly conductive metal material such as copper or aluminum.

The film over wire adhesive 240 is formed on the wafer 220. In this embodiment, the wire bonding layer 240 is adhered to the active surface 221 of the wafer 220 and partially covers the bonding wires 230, that is, the bonding wires 230 are located above the active surface 221 and are easily punched. The arc of the line. Therefore, the thickness of the coating layer 240 should be higher than the line arc height of the bonding wires 230. The wire coating layer 240 can be a polymer adhesive material. When formed on the wafer 220, it can be in a liquid or gel state, but cannot be completely cured. Therefore, under the condition of the appropriate temperature adjustment control and the local heating, the wire bonding layer 240 has the same bonding wire, the built-in heat sink 250 is fixed before the molding, and the built-in heat sink 250 is maintained between the wafers 220. The role of the gap.

Further, as shown in FIG. 2, the built-in heat sink 250 is disposed above the wafer 220 by the wire coating layer 240, and can discharge the heat generated by the wafer 220. In particular, the peripheral side surface 251 of the built-in heat sink 250 is embedded in the wire coating layer 240, and only one top surface 252 of the built-in heat sink 250 is exposed, but the lines of the bonding wires 230 are The arc system can be spaced from the built-in heat sink 250 without being in contact with the built-in heat sink 250 to avoid contact short circuits. In addition, since the built-in heat sink 250 is of a built-in type, that is, it is accommodated in the cavity of the upper mold forming the mold-molding body during molding, the top surface 252 of the built-in heat sink 250 is generally not more than The upper surface of the mold 260 is molded.

In detail, the material of the built-in heat sink 250 may be selected from one of copper, aluminum, and bismuth, or other metal material having good thermal conductivity, to dissipate heat generated when the wafer 220 operates. In the atmosphere. The built-in heat sink 250 may have any shape, such as a rectangle of FIG. 3 or other flat metal shapes such as a circular or circular arc, and the top surface 252 is flat. Preferably, the built-in heat sink 250 does not have a bonding leg supported by the substrate 210, but the built-in heat sink 250 is supported by the wire bonding layer 240, and can be fixed on the wafer 220. There is no need to provide the bonding legs on the substrate, and the bonding legs of the heat sink and the heat sink stamping step can be omitted. In addition, the peripheral side surface 251 of the built-in heat sink 250 may be a vertical surface to facilitate depression and depression in the wire coating layer 240. In another preferred embodiment, the peripheral side surface 251 of the built-in heat sink 250 may also be an inclined surface that is reduced inward to reduce the resistance when the built-in heat sink 250 is pressed down to the wire coating layer 240. In addition, the wire bonding layer 240 can have a smaller Young's modulus and better thermal conductivity than the molding compound 260, and the bottom surface of the built-in heat sink 250 is covered by the wire coating layer 240. The peripheral side surface is adhered to the active surface 221 of the wafer 220, instead of the conventionally sealed epoxy resin, the thermal energy of the wafer 220 can be directly discharged from the active surface 221 to the built-in heat sink 250. Higher heat dissipation efficiency.

As shown in FIG. 2, the molding compound 260 is formed on the upper surface 211 of the substrate 210 to cover the wafer 220 and the bonding wires 230 to expose the top surface 252 of the built-in heat sink 250. The wire coating layer 240 is spaced between the built-in heat sink 250 and the molding compound 260 to prevent the molding gel 260 from forming the molding compound 260 from contaminating the top surface 252 of the built-in heat sink 250. Thermal efficiency and package appearance. In this embodiment, the cover tape layer 240 completely covers the peripheral side surface 251 of the built-in heat sink 250, so that the wire coating layer 240 is blocked between the built-in heat sink 250 and the mold sealing body 260. Therefore, the mold sealing body 260 does not contact the built-in heat sink 250. Specifically, as shown in FIGS. 2 and 3, the wire coating layer 240 may have an outer ring surface 241 surrounding the peripheral side surface 251 of the built-in heat sink 250, so that the molding compound 260 does not directly The built-in heat sink 250 is in contact, and there is no overflow phenomenon after the molding operation. As shown in FIG. 2, the exposed annular surface 241 is exposed to the molding compound 260, and the exposed annular surface 241 is flush with the top surface 252 of the built-in heat sink 250. In detail, the top surface 252 of the built-in heat sink 250 may be smaller than the upper surface 211 of the substrate 210 covered by the molding compound 260 to expose the exposed annular surface 241. For example, the top surface 252 of the built-in heat sink 250 may be approximately the same size as the wafer 220.

Referring to the cross-sectional views of the components in the process of FIGS. 4A to 4D, the present invention further illustrates the process of the built-in heat sink 250 disposed on the wafer 220 to demonstrate the efficacy of the present invention.

As shown in FIG. 4A, in the case of mass production, the substrate 210 can be in the form of a substrate strip, and the plurality of substrates 210 are integrally arranged in a matrix on a substrate strip, and each substrate 210 is provided with a strip. The wafer 220 can perform the molding operation on two or more semiconductors at the same time in the subsequent process, thereby increasing the output and saving the equipment cost of the molding operation. After the packaging operation, each substrate 210 can be fabricated into a semiconductor construction.

After the step of bonding and bonding, the coating layer 240 can use a dispensing needle (not shown) to dispense a liquid or gel-like coating layer 240 in a dispensing manner. Formed on the active surface 221 of the wafer 220 and partially covered the bonding wires 230. In other embodiments, the blanketant layer 240 can also be formed by vacuum printing or other means.

Next, as shown in FIG. 4B, the built-in heat sink 250 is disposed above the wafer 220 by the capping layer 240. Herein, the installation of the built-in heat sink 250 by the wire coating layer 240 is temporary, and after the molding step, the wire bonding layer 240 and the molding compound 260 must be cured to be firmly combined. Built-in heat sink 250. Since the wire coating layer 240 is not fully cured in this step, the built-in heat sink 250 can be embedded in the wire coating layer 240 by applying a suitable pressing pressure to the built-in heat sink 250 and heating. In actual operation, the top surface 252 of the built-in heat sink 250 may be adsorbed by a pick-and-place fixture (not shown), and the built-in heat sink 250 may be horizontally pressed into the line covering layer 240, but not The built-in heat sink 250 is brought into contact with the bonding wires 230, and after being pressed down, the peripheral side surface 251 of the built-in heat sink 250 is embedded in the wire coating layer 240, but the top surface 252 is still exposed. . In another modified embodiment, as shown in FIG. 5, the depth of depression of the built-in heat sink 250 can be appropriately controlled by using the pick-and-place head of the die-bonding machine, so that the peripheral side 251 of the built-in heat sink 250 can be The overlying adhesive layer 240' is partially covered rather than finished to form an overflow gap 253 that is not on the top surface 252. The overflow gap 253 can be filled by the molding compound 260 or its molding overflow after the molding operation, but does not contaminate the top surface 252.

Preferably, as shown in FIG. 4B, after the built-in heat sink 250 is stacked, the wire coating layer 240 can exhibit a B-stage (or semi-cured state) for the molding operation. Among them, the so-called B-stage is a viscous body in which the viscose can be heated to a fluid state in a state where it is not fully cured, and can exhibit a solid or jelly-like property after being cooled, and has reversibility.

Next, as shown in FIG. 4C, the molding compound 260 is overlaid on the upper surface 211 of the substrate 210 by a transfer molding technique. That is, the substrate 210 and the stacked wafer 220 and the built-in heat sink 250 are received by the upper mold 10 to form a cavity 11 having a space for filling the glue. . Since the wire coating layer 240 can correct the level and height of the built-in heat sink 250, the top surface 252 of the built-in heat sink 250 can be flattened to the top surface 12 of the upper mold 10 to achieve closeness. The exposed toroidal surface 241 of the wire coating layer 240 also conforms to the top surface 12 of the cavity. In actual operation, the top surface 12 of the cavity can slightly press the flat top surface 252 to achieve a close topping. In addition, during the molding operation, since some of the wire segments of the bonding wires 230 are embedded in the wire coating layer 240, the bonding wires 230 are not affected by the molding flow of the molding compound 260 (impact The problem of the punching line is not caused by the adjacent bonding wires 230 contacting each other and causing an electrical short circuit.

Thereafter, as shown in FIGS. 4C and 4D, the mold precursor 260 can be filled into the cavity 11 under appropriate temperature rise conditions and injection pressure to seal and protect the wafer 220. The line 230 and the wire coating layer 240 expose the top surface 252 and the exposed ring surface 241 of the wire coating layer 240. Thereafter, it is suitably baked to cure form to protect the internal components from damage and corrosion by external forces, moisture or other substances.

In addition, in another variation, as shown in FIG. 5, the peripheral side surface 251 of the built-in heat sink 250 is partially covered by the wire coating layer 240, and the overflow gap 253 which is not on the top surface 252 is formed. . When the overflow gap 253 is in the molding operation, the mold flow of the molding compound 260 is gradually filled to the overflow gap 253. At this time, the mold flow will be reduced due to the flow space and absorbed by the upper mold 10, thereby increasing The viscous flow of the mold stream causes the flow rate to slow down, and then the mold flow will continue to flow slowly into the overflow gap 253, thereby preventing the mold overflow from contaminating the top surface 252 of the built-in heat sink 250. Thereafter, the molding compound 260 is completely cured, and the curing of the coating layer 240 can be simultaneously completed.

Finally, as shown in FIG. 4D, the die cutter 260 and the substrate 210 may be cut along the cutting line 201 of the semiconductor package structure by a cutting blade 20 such as a mechanical cutter or laser light to complete the singulation. Since the size of the top surface 252 of the built-in heat sink 250 is smaller than the surface 210 of the substrate 210 covered by the molding compound 260, the built-in heat sink 250 is not cut during the singulation cutting step, and The cutting tool 20 will be worn.

In accordance with a second embodiment of the present invention, another schematic diagram of a semiconductor package construction that avoids contamination of the overfill with a built-in heat sink is illustrated in FIG. The same elements as those in the first embodiment will be denoted by the same reference numerals and will not be described again. The semiconductor package structure 300 mainly includes a substrate 210, a wafer 220, a plurality of bonding wires 230, a coating layer 240, a built-in heat sink 250, and a molding compound 260.

In this embodiment, the substrate 210 can have a slot 313. The active surface 221 of the wafer 220 faces the substrate 210. The pads 223 are disposed at a central position of the active surface 221 of the wafer 220. The bonding wires 230 are electrically connected to the pads 223 of the wafer 210 via the slots 313 to the substrate 210 . The bonding layer 240 is adhered to the back surface 222 of the wafer 220 . The built-in heat sink 250 is disposed above the wafer 220 by the wire coating layer 240. The peripheral side surface 251 of the built-in heat sink 250 is embedded in the wire coating layer 240, and is only exposed. The top surface 252 of the built-in heat sink 250 is removed. Since the built-in heat sink 250 and the wafer 220 do not have a bonding wire, the depth of the built-in heat sink 250 can be further reduced, and the package volume can be reduced, and the heat transfer path can be shortened.

In addition, the molding compound 260 is formed on the substrate 210, and also fills the slot 313 to cover the bonding wires 230 to provide proper package protection to prevent electrical short circuit and dust pollution.

Therefore, the semiconductor package structure 300 can be formed between the built-in heat sink 250 and the mold sealing body 260 by the coating of the soldering layer 240, thereby preventing the molding of the molding compound 260 from contaminating the built-in heat sink. The top surface 252 of the sheet 250 affects heat dissipation efficiency and package appearance.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

10. . . Upper mold

11. . . Cavity

12. . . Cavity top surface

20. . . Cutting tool

100. . . Semiconductor package construction

110. . . Substrate

111. . . Upper surface

112. . . lower surface

120. . . Wafer

123. . . Solder pad

130. . . Welding wire

140. . . Adhesive layer

150. . . heat sink

151. . . Peripheral side

152. . . Top surface

153. . . Bottom

160. . . Molded sealant

161. . . Molded plane

170. . . External terminal

200. . . Semiconductor package construction

201. . . Cutting line

210. . . Substrate

211. . . Upper surface

212. . . lower surface

220. . . Wafer

221. . . Active surface

222. . . back

223. . . Solder pad

230. . . Welding wire

240. . . Overlay layer

240’. . . Overlay layer

241. . . Exposed torus

250. . . Built-in heat sink

251. . . Peripheral side

252. . . Top surface

253. . . Overflow gap

260. . . Molded sealant

261. . . Molded surface

270. . . External terminal

300. . . Semiconductor package construction

313. . . Slot

Fig. 1 is a schematic cross-sectional view showing a conventional semiconductor package structure having a heat sink.

2 is a schematic cross-sectional view showing a semiconductor package structure for avoiding contamination of a mold overfill to a built-in heat sink according to a first embodiment of the present invention.

Figure 3 is a top plan view of a semiconductor package structure in accordance with a first embodiment of the present invention.

4A to 4D are views showing a cross-sectional view of an element in a process of fabricating a semiconductor package in accordance with a first embodiment of the present invention.

Fig. 5 is a cross-sectional view showing a semiconductor package structure having another heat sink embedded state according to a variation of the first embodiment of the present invention.

Figure 6 is a cross-sectional view showing another semiconductor package structure for avoiding contamination of the overmold to the built-in heat sink according to the second embodiment of the present invention.

200. . . Semiconductor package construction

210. . . Substrate

211. . . Upper surface

212. . . lower surface

220. . . Wafer

221. . . Active surface

222. . . back

223. . . Solder pad

230. . . Welding wire

240. . . Overlay layer

241. . . Exposed torus

250. . . Built-in heat sink

251. . . Peripheral side

252. . . Top surface

260. . . Molded sealant

261. . . Molded surface

270. . . External terminal

Claims (9)

A semiconductor package structure for preventing a mold from overflowing to a built-in heat sink, comprising: a substrate; a wafer disposed on the substrate, the wafer having an active surface and a plurality of pads on the active surface; a bonding wire electrically connecting the pads to the substrate; a coating layer is formed on the wafer; and a built-in heat sink is disposed above the wafer by the coating layer The peripheral side of the built-in heat sink is embedded in the wire coating layer; and a molding compound is formed on the substrate to cover the wafer and the bonding wires to reveal one of the built-in heat sinks The cover layer is spaced between the built-in heat sink and the molding compound, and the wire coating layer surrounds the flat bottom surface and the peripheral side surface of the built-in heat sink and has a surface exposed on the molding compound. The exposed torus surface is such that the molding compound does not contact the built-in heat sink to prevent the molding gel which forms the molding compound from contaminating the top surface of the built-in heat sink. The semiconductor package structure of the built-in heat sink is partially covered by the wire covering layer to form a non-top surface of the built-in heat sink according to the first aspect of the invention. There is a gap in the glue. Avoiding overmolding according to item 1 or 2 of the patent application scope A semiconductor package structure that is contaminated to a built-in heat sink, wherein the wire bond layer has a smaller Young's modulus and better thermal conductivity than the die seal system. The semiconductor package structure for preventing contamination of the overfilled metal to the built-in heat sink according to claim 1 or 2, wherein the built-in heat sink does not have a bonding leg supported on the substrate. The semiconductor package structure of the built-in heat sink according to claim 4, wherein the size of the top surface of the built-in heat sink is smaller than an upper surface of the substrate covered by the mold sealant. . The semiconductor package structure of the built-in heat sink is selected from the group consisting of copper, aluminum and telluride according to the first or second aspect of the patent application. The semiconductor package structure of the built-in heat sink is prevented from being contaminated by the mold leakage according to claim 1 or 2, wherein the wire coating layer is adhered to the active surface of the wafer and partially covers the bonding wires. . The semiconductor package structure of the built-in heat sink for avoiding the contamination of the overfilled metal according to claim 1 or 2, wherein the substrate has a slot through which the soldering wire is electrically connected The substrate is adhered to the back side of the wafer. The semiconductor package structure of the built-in heat sink for avoiding contamination of the overfilled rubber according to claim 1 or 2, wherein the overcoat layer is a service layer, and the top surface of the built-in heat sink is One of the molding surfaces of the molding compound is coplanar.