TWI338231B - A single chip protocol converter - Google Patents

Description

1338231 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a network processor device and a storage area network. More specifically, the present invention relates to an architecture for providing a protocol conversion. A system and method that spans multiple network protocols that are built into a single ic chip or constructed as a sub-processor core component in a conventional s〇c, Dsp, FpGA, or similar integrated circuit subsystem. [Prior Art] As the market changes toward storage area networks (sANs) and network attached storage (NAS) systems, and with the tremendous expansion of the Internet, new demands for vocabulary and storage design have emerged. Storage attached via parallel SCSI connections is replaced by Fibre Channel (FC) storage area networks (s AN) and other emerging network connectivity architectures such as iSCSI and IP Fibre Channel (FC-IP). Iscsi involves the transfer of block data over a TCP/IP network, usually built around Gigabit Ethernet, and FC-IP is an Internet Protocol (IP) based on storage network connectivity technology. It enables FC information to be transmitted by tunneling data between SAN facilities over an IP network. Generic CPUs do not meet the computational needs of network protocol conversions or are too expensive in terms of unit cost, space, and power. This has caused many network connections and protocol processing functions to be offloaded from the host processor to the host bus adapter (HBA) or network interface controller (NIC). Initially, most HBAs and NICs were built into ASICs using hardwired logic. But when there is a need to construct a complex network protocol such as TCP/IP or iSCSI 98784.doc 1338231, the stylized solution has become more attractive with its many advantages: it can adapt to different developments. Agreement for change; it can be easily upgraded via a program change; it provides faster time to market. Existing SANs are typically physically far away 'sometimes at larger distances, and often use multiple network architectures. In order to consolidate existing SANs and to take advantage of existing WAN and LAN infrastructures, there is a need for network protocol conversion in the data communications and telecommunications fields. The contract conversion will allow seamless integration and operation of all the different parts of the system.

Brocade Communications Systems has released a system-level protocol converter product for multiprotocol fabric routing services [http://biz.yahoo.com/prnews/031028/sftulOO-l.html] Fibre Channel to Fibre Channel (FC-FC), iSCSI to FC bridging, and Fibre Channel to FC_Ip translation.

An existing protocol converter integrates multiple chips onto a card to obtain the desired logic function, or more typically, the card is a host φ bus adapter (HBA) card that is plugged into an existing host system, or is the primary host I The daughter card on the /O card results in a bulky product that is more expensive in terms of unit cost, space and power. In addition, existing protocol converters are not programmable or have very limited programmability' and are not easily upgradeable to accommodate different protocols or new agreements. In addition, there is a physical layer access module or chip, which is usually a special physical layer protocol to optimize its embodiment and circuit technology, so that when a new physical layer protocol is required at a glance, it is necessary to replace the entire host bus. Adapter (HBA) card or several components. It is not the usual conversion of the same entity 1/〇 card, and the conversion is not within the single-chip solution or as an embedded core within the SoC 987S4.doc 1338231 semiconductor device. A system wafer design 20 in accordance with the prior art is illustrated in FIG. It includes a processing element such as PPC 440 (Power PC) 25, a regional processor bus (PLB) 21, an on-wafer peripheral bus (OPB) 24, and numerous components such as SRAM 15, DDR controller 18, PCI. -X bridge 22, DMA 26 and DMA controller 28, Ethernet media access control (MAC) protocol device 50, processor core timing employed to provide a data link layer for an Ethernet LAN system The interpolator 33 and the interrupt controller 35, and an OPB bridge 29 coupled to the OPB bus 24 and the PLB 21, utilize the IBM embedded PowerPC 440 processor core and the prior art embodiment depicted in FIG. CoreConnect zone bus, but similar configurations using other enemy processor cores, such as ARM (see, for example, http://www.arm.com/products/70penDocument), MIPS (see http://) Www.ce.chalmers.se/~thomasl/inlE/mips32 MIPS at the 4Kp brief.pdf: "MIPS32 4ΚΡ -Embedded MIPS Processor Core") Processing core and more. As shown in FIG. 1, other means for engaging the peripheral bus bar 24 on the wafer includes one or more of the following: a RAM/ROM peripheral controller 45a, an external bus master 45b, a UART device 45c, 1C busbar (I2C) interface 45d, general purpose I/O interface 45e, and gateway interface 45f. A related reference describing the design of the SoC processor and component includes: US Patent No. 6,331,977 describes a system wafer (SoC) containing interleaved switches between several functional I/Os within the wafer ( Crossbar switch), and a number of external connection pins, where the number of pins is less than the number of internal I/O. 98784.doc U.S. Patent No. 6,262,594 describes an apparatus and method for constructing a configurable interleaved switch for a pad group of system wafers. U.S. Patent No. 6,038,630 describes an apparatus and method for constructing an interleaved switch that provides an integrated system for accessing a plurality of functional units of an external structure on a plurality of data busses. Shared access control device. US Patent Application No. US 2002/01 84419 describes an ASIC that uses a universal busbar system to enable the use of different components of a system wafer, and describes functional units for different speeds and data widths to achieve a common confluence A compatible package. U.S. Patent No. US 2002/0176402 describes an octagonal interconnection network for linking functional units on a SoC. The functional units on the internetwork are grouped into loops and use a number of interlinked data links for the halfway coupling components. US Patent Application No. US 2001/0042 147 describes a system resource router for s〇C interconnections, which includes a connection cache memory (D_cache memory) and instruction cache memory ( I-cache memory) two channel jacks. Also included are external data transfer initiators, two internal M-channel busses, and a % channel controller to provide interconnection. U.S. Patent Application Serial No. US 2002/0172197 describes a communication system for connecting a plurality of transmission and reception devices in a point-to-point manner via an interleaved switch embedded in a wafer. 98784.doc 1338231 US Patent Application No. US 2001/0047465 describes several variations of an invention that provides a scalable architecture (typically a SOC or ASIC) for a communication system to divide the transmission into The individual gates are individually transmitted, the computational complexity of each transmission task is determined, and the computational complexity is minimized based on the number of MIPS per circuit. In A. Brinkmann, J.C. Niemann, I. Hehemann, D.

Langen, M. Porrmann and U. Ruckert, entitled "On-Chip Interconnects for Next Generation System-on-Chips", Proceedings of ASIC 2003, September 26-27, 2003, Rochester, New York In reference, an SoC architecture that utilizes an active switch box to connect processor units to enable packet network communication is described. This paper does not mention or describe a processor core with multi-threading capability.

In Kyeong Keol Ryu, Eung Shin and Vincent J. Mooney, entitled "A Comparison of Five Different Multiprocessor SoC"

Bus Architectures",proceedings of Euromicro Symposium on Digital System Design (DSS'01), September 4, 2001, W, W, Warsaw, Poland, describes a multiprocessor SoC bus architecture that includes global busses I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Queue Architecture (BFBA), Interleaved Switch Bus Trunking Architecture (CSBA), and Core Connection Bus Architecture (CoreConnect Bus)

Architecture) (CCBA). A single embedded processor-based approach provides a cost-effective, integrated solution for some applications, but it may lack the computational power required by higher-demand applications 98784.doc 1338231, and for contract conversions or future agreements Increased speed flexibility, for example, 2.5 Gbps Fibre Channel to 10 Gbps Fibre Channel. In recent years, in many network connectivity applications, by adding a dedicated processor core (accelerator) 39 attached to a general bus (PLB) (as shown in Figure 2, operating in parallel with processor core 25) The computing power of the SoC of Figure 1 is enhanced. Such additional dedicated processor cores 39a, 39b, etc., typically have a smaller area as a result of eliminating many of the features found in typical general purpose processors (e.g., memory management units for supporting virtual addressing, etc.). An example of such a method is IBM's PowerNP (see, for example, by M. Heddes, "IBM Power Network Processor architecture", Proceedings of Hot Chips 12, Palo Alto, CA, USA, August 2000, IEEE Computer The Society's reference) and NEC's TCP/IP offload engine (see, for example, http://www.tensilica.com/litml/pr_2003_05_12.html titled "NEC's New TCP/IP Offload Engine Powered by · 10 Tensilica Xtensa Processor Cores") Although these systems are programmable and therefore more flexible than fixed-line accelerators, they suffer from several drawbacks: a) When the bus must support instruction and data flow to the processing immediately Accelerator, which induces additional traffic on the SoC bus (eg, PLB 2 1), which can result in bandwidth competition and limit system performance; b) in SoC systems, usually not multiprocessor performance Optimizing the SoC bus for compatibility with standardized components and connection protocols; and c) processor accelerator 39 typically only constructs a very limited set of instructions and uses a combined language, thus enabling operation The development and maintenance of applications on processor accelerators is extremely difficult and expensive. The third type of SoC design 75 is a 98784.doc connected via an interleaved switch. 1338231 Intrusive Processing|§ Core, such as M〇t〇r 〇lai MPC 5554 Micr〇c〇n Plus (Design News, November 3, 2003, page #38), a block diagram of which is depicted in Figure 3. As illustrated in Figure 3, M〇t〇r〇 The la s〇c design consists of many components similar to the SoC design of Figure 1 and Figure 2, which consists of the p〇werpc processor core, memory and bus interface, however, more significantly, the construction of 3 X 5 parent error The parental switcher 72 acts as an alternative to one of the regional busbars. By incorporating the interleaved switch 72 into the SoC design, the processor core communication can be operated simultaneously by the two (3) lines. It happens quickly, to solve the bandwidth competition problem to a certain extent. However, S〇C is still not supported for multi-processor, or optimized for higher-level functions such as protocol conversion in a single SoC chip, or high-speed interface. The 1/0 communication within the chip is limited by the interleaved switch and still needs Communicating with the external bus interface and host system bus limits the performance and flexibility of the microcontroller (SoC chip) for any future upgrades. Any contract conversion will need to be performed outside the wafer, in several stages or in a wafer. In addition, you cannot place the instructions placed on the bus of the host system and • decouple the data packets. In the example of Figure 3, for example, a convention for the FlexCan (CAN Protocol: "Control Area Network") data stream typically used in automated applications, and such as DSPI (or " tandem peripheral interface, Or other protocols of eSCI (Enhanced Serial Communication Interface) are now built into the Motorola MPC 5554 chip via an external 1/〇 bridge 78, where each protocol or 1/〇 specific stream passes through an I/O bridge, Interleaved switches, and typically an internal wafer bus or external bus interface to the system bus. (Currently - there is no protocol conversion in today's single-chip, and there is no independent agreement or 98784.doc 12 1338231 agreement version level conversion to full new agreement or version by embedded core attached to internal wafer bus Level agreement conversion method. The current protocol conversion only occurs at the system or card level, which involves multiple wafers as mentioned earlier. One example is the Brocade Silkworm Fabric Application Server mentioned earlier for SAN networks (eg See http://www.brocade.com/san/ending_v alueof_S ANs.jsp) as shown in Figure 4. In the prior art Brocacje system 1 概念 conceptually depicted in Figure 4, for example, Fibre Channel to Fibre Channel (FC to FC) routing 102, iSCSI to FC bridging 104, and Fibre Channel to FC_Ip translation capability. 01_〇 Designed as an improvement to today's existing technology, the improvement is: Fiber]/Leica can support multiple protocols and can even migrate from one agreement to another on the same 1/Leica without interfering with traffic on other ports in the system. Data and control frames from the packet processing function, several streamlined RISC processors (in-line RISC pr〇Cessor) chips with area s replies and frame buffers, software preprocessors, and processor cards This is done with the translation engine within φ. This is an improvement on the standard single HBA card, which allows two network protocols within a single HBA card, eliminating the cost and space, changing the flexibility of the agreement (and not doing 35) The communication traffic on the main system bus), the data transfer consumption 'and the main system processor memory Zhao Shangzhi memory competition. The multiprocessor in the Brocade method is completely pipelined and attached to the area memory. Incorporating this power in a single chip rather than a single HBA card or bridge card enables the transfer of the correct protocol conversion in a single wafer, processing of data and control frames within the protocol conversion to confluence to the area排排或系统98784.doc •13· The hoistway delivers a one-component packet. This will enable savings in the card's further/potentially-hardened body (chip S mesh), less bandwidth competition, memory competition, and Enable Achieving higher protocol speeds and more processors within the SqC wafer (or attached to the -area system bus), and higher yields. [Invention] It is an object of the present invention to provide a self on a single wafer. The inclusion protocol converter or provides it as an embedded SgCe# that performs protocol conversion processing within the single wafer or within the embedded macro embodiment without the need for host system resources. According to one aspect of the present invention, an efficient protocol converter is provided on a single semiconductor wafer or provided as a single-chip embedded cooperative conversion for the S(C) type design. The s〇c macro embodiment can convert a communication protocol into a separate, new communication protocol, and/or can convert a communication protocol version level to another communication minus version level. For example, an embedded protocol converter macro or a single-chip protocol converter can be configured to convert a packet from a protocol version level (eg, 'Fibre Channel 2 (5) S) within the single chip or within the embedded SqC macro. Into another-protocol version level (such as Fibre Channel 10 called or self-contracted to - completely different agreement (for example, Fibre Channel converted to Ethernet or 匸 "etc.). Whether constructed as a single chip or constructed as Embedded macros, protocol conversions are all t- or multiple processor core assemblies, (iv) one processor core assembly r. Two or more microprocessor devices capable of performing operations to construct protocol conversion capabilities: An area storage device associated with the two or more microprocessor devices to store at least one of data and instructions 98784.doc 1338231 in each processor core assembly; or more Configurable interface device capable of receiving and transmitting communication packets in accordance with - or a plurality of communication protocols; and - an interconnecting member 'for enabling two or more microprocessor devices and the interfaces Connect between devices Therefore, advantageously, the single-wafer protocol converter and the Syrian macro design include a means for scaling the type design to a much higher protocol speed, and including incorporating a plurality of processors into one s〇 c. Capabilities within the embodiment. • Single-wafer or embedded protocol converter functionality can be implemented by using a full-featured, multi-threaded, multi-processor chip design in which area memory is incorporated into the wafer (or The s〇c attach macro) handles all the functions of the protocol conversion (resize, reformat, control, split) to deliver a completed packet to the regional bus. Preferably, the single-chip protocol converter and the embedded giant The set design performs most of the protocol processing without the need for host system bus resources (that is, the processing takes place in a SoC attachment cluster), meaning that when needed, then • place any contracted conversion packets on The area S〇C or the system bus. The protocol processing instructions are fully executed within the soc protocol macro or in the protocol conversion chip for stand-alone design purposes. The convergence of the good bus performance 'system bandwidth, the number of systems increased, and the host bus bar attachment card is significantly reduced or eliminated. Because of the single-chip embedded macro, it is used in the agreement conversion application The main system daughter card, thus reducing costs and increasing performance. In addition, the SoC embedded protocol converter macro or single-chip protocol converter architecture can be easily reconfigured from a function (meaning 'convention conversion) to full New 98784.doc 1338231 features (TCP/IP offload, accelerator', firewall function, etc.). So the operational functions of the single chip or embedded protocol converter macro can be modified to - completely new operational functions, the complete The new operational functions can be independent or different from • The first operational function (for this function, the single-chip or embedded protocol converter macro can be initially programmed). This operational function change can be based on a number of factors including, but not limited to, the number of processor core assemblies in the chip (processing clusters) 'the number of processors within the clusters, the regions within the clusters The number of memory (eg, cache memory) and the amount of area memory (SRAM, DRAM, etc.) associated with each cluster. According to another embodiment, a single-chip protocol converter integrated circuit (1C) or SoC protocol conversion macro core embodiment utilizes sufficient area memory, control logic, collection and operation queues, An interleaved parent exchange or other switching subsystem, protocol control, interface, and bus, multi-threaded, pipelined, multi-processor core that bridges 1 § I/O functions. By incorporating standard bus-bridge I/O functionality into the system-on-a-chip (s〇c) area bus, the embedded protocol converter macro additionally enables higher density, efficiency, and improved host processor performance. , bandwidth, and memory competition improvement, consumption reduction. In a multi-threaded approach, pipeline operations, a smaller number of instructions, a simple processor architecture, embedded memory, and a context that is not deep into the processor can make a protocol converter chip or embedded giant The set is highly adaptable and configurable for multiple protocol, version level, and even standalone network connectivity functions compared to the original protocol converter chip or embedded s〇c macro originally used. Advantageously, the SoC Embedded Compact Converter Macro or Single Chip Association 98784.doc 16 1338231 converter of the present invention can be applied to self-SAN networks, servers, home networks, automatic networks, industrial, and telecommunications to Many applications of simple I/O protocol data streams. [Embodiment] As will be referred to herein, the term "agreement" refers to any specific input/output (I/O) communication material entity laminar flow, usually specified by a standard ontology, or may be a proprietary interface within a company, which has many Examples, including but not limited to: Fibre Channel, Ultra High Speed Ethernet, iSCSI, IP, TCP/IP, FC/IP, ESCON, FCON, CAN, SAMBA, DSL, VoIP, MPLS, GMPLS, and More. In the described embodiment, the agreement is a communication protocol, such as Fibre Channel, Ethernet, iSCSI, ESCON, FCON, IP layered protocols, or encapsulation protocols such as FC/IP, IP/MPLS, and the like. Data communication protocols typically have data bits in a byte, block or group, frame, and packet configuration with control characters such as the beginning of the frame, the end of the frame, the source agreement, the target agreement, etc. Etc; and the actual resources in the payload of the bit stream. The protocol converter of the present invention employs a special processor and is constructed as a stand-alone or integrated SoC (system chip) type design. A block diagram of a basic protocol converter die 350 that can be used as a macro of a SoC embodiment is illustrated in FIG. U.S. Patent Application Serial No. 10/604, filed on Jul. 25, 2003, which is hereby incorporated by reference in its entirety, the "Self-Contained Processor Sub-component for System-on-Chip design" The basic structure and operation of this core is described in 491, and its operation is described in this article. 98784.doc 1338231 Jane 5, as shown in Figure 5, the protocol converter on a single chip (or s〇c Ganyin macro core) is a self-contained, processor-based child dedicated to protocol conversion System 350, but reconfigurable to other network functions, including one or more processor clusters 200, one or more regions for storing data and/or instructions, and a construct A regional interconnect member 22 or other similar switching member of an interleaved exchanger (or, may utilize a construction exchanger, or an MP bus). The single-wafer protocol converter design of the present invention includes a number of simple processor cores with reduced common instruction sets from the PowerPC architecture. Each processor cluster 200 includes one or more processing cores 2, 5 each having A four-level deep pipeline single-issue architecture in which each processor core 2〇5 has its own scratchpad file 226, arithmetic logic unit (ALU) 225, and instruction sequencer 227. In the single-wafer protocol converter depicted in FIG. 5 and the embodiment of the SoC embedded macro for co-transformation depicted in FIG. 8, eight processor cores 205 are connected to the same instruction cache. The body 208 is packaged in a processor cluster 2〇〇. h Make the size of the cache suffix - design options, such as 3 2 make ugly enough for network applications. An area SRAM memory unit 230 associated with at least two processor cores 205 via a regional bus is additionally provided. The exact number of processor clusters 200 (e.g., one, two, or even six processor clusters (including 1 28 cores) in the protocol converter 350 to support sufficient computing power depends on the application needs. For example, constructing a function for a Fibre Channel network protocol requires less than a more complex computational power of the terminal, IP, or computational power for an iSCSI protocol conversion embodiment. 98784.doc -18- 1338231 rate . - Another feature of the processor-based subsystem protocol converter 35 of the present invention is the use of embedded memory 215 for storing information about applications, current control information, and applications. A sufficient amount of memory to provide smooth operation under normal operating conditions is placed in a contract converter order without excessively increasing its size. Another advantage of embedded memory compared to conventional off-chip memory is that it provides shorter and predictable access times, and φ accurately takes into account these accesses in the time budget estimation of packet processing. time. All of the components in the co-transformer chip 350 are interconnected via an interleaved switch 220 that specifically interconnects the processor cluster 2, the shared memory block 215, and the network. Protocol layer hardware assist device or embedded MAC interface 175, 185. When constructed as an embedded macro in the SoC (such as described herein with respect to Figures 8-10), the interleaved switch 22 is then connected or directly attached to the s by a bridge macro (bus) 224. 〇c at the φ processor area bus 2 1 0 or external system bus 223 (for example, pci or PCI-X, etc.). The bridge can be adapted to accommodate different speeds, busbar widths, machine numbers' and signalling agreements. In the macro s〇c embodiment, the standard between the co-author converter macro 350 and the embedded processor area bus 210 (eg, PLB in IBM CoreConnect or ARM, MIP in ARMBA, etc.) The advantage of the interface is that it allows the integration of the contract converter into a macro in the soC component library. At the lower level of the network protocol, a hardware accelerator for the high time-critical function is further constructed, which handles the low-level 98784.doc 19 1338231 protocol task 'such as data encoding/decoding, serialization /Deserialization, link deficiencies, and CRC and checksum calculations. These tasks are performed on each byte of the transmitted packet and are computationally expensive if constructed in soft. The hardware embodiments of these functions are provided as hardware accelerators built in the fiber channel network interface 175 and in the ultra high speed Ethernet us. The network interface 175 and the ultra high speed Ethernet 185 are only required. The smaller and smaller areas are joined to individual Fibre Channel and ultra-high speed Ethernet g communication links 190, 195, respectively. The additional advantages resulting from the separation of the negotiated converter core 350 from the processor bus (single-chip embodiment of the SoC processor area bus or system bus) are: 1) the protocol core and the s〇c system or system The only communication traffic between busbars is data stream traffic (data reception and transmission), thus minimizing bandwidth competition; and 2) subsystem interconnection architecture (ie, switch) does not need to adapt to the total SoC Standard component interface and connection protocol, other processors attached to the switch fabric, or the main system bus itself, providing the best high-performance solution for the agreed φ core, allowing for higher protocol conversion speeds, in a single More agreement between SoC or host bus adapter card processing, and less competition on the main system bus. β is now described when constructed as a protocol converter (single-machine single-chip or as an embedded S 〇C macro) The operation of the processor subsystem. In one embodiment, single-chip protocol converters 350 (or embedded macros of SoC designs) provide Fibre Channel (FC) to ultra-fast Ethernet (GE) conversion. It should be understood that this design considers many combinations 'such as Fibre Channel to IP, Fibre Channel to iscsI, Fibre Channel to Infiniband, TCP/IP to iSCSI, and any of 98784.doc • 20· 1338231 mentioned herein. Other Agreements In fact, this embodiment is not limited to communication protocols, but can be constructed in an automated network, home, or industrial environment, such as the Motorola MPC5554 Microcontroller for automatic networks such as CAN, or for home use. Application of the samba network. 6 is an illustrative illustration of the single-wafer protocol core 35 of FIG. 5 configured from a 'cross-channel' to a super-faceted Ethernet single-chip protocol converter 300 » the core of the agreement not shown in FIG. In this case, the required endpoint functions are constructed, as well as the size and re-formatting of the packets required for the conversion between the two associations. The basis of this structure is the division of the operation of the agreement so that it can be handled by different resources on the wafer. - Each protocol operation of the processor (or group of processors) (except for some time-critical functions close to the network entity interface) is constructed by hardware acceleration. Referring now to Figure 6, the packet and processing flow is as follows. The DMA logic transfers the received packet and some status information from the incoming FIFO buffer to the embedded memory. The DMA logic has received from a free buffer list. An indicator of the empty memory area. By obtaining control information from the memory or if the packet is the first one of the new exchange, the packet header is checked by generating new control information to determine the packet environment and switch the current dilemma as needed. In addition, the received packet is verified to ensure that it follows the switching service category to which it belongs. A acknowledgment packet is generated if the acknowledgment of the received packet (ackn〇wUdgment) is sent back to the source protocol (eg, Class 2 service in Fibre Channel). Combine the corresponding header information of the acknowledgment packet and send the packet to the outgoing Fibre Channel network interface. In this specification, a packet is defined as a collection of data bits that contain at least the target protocol information' and are typically used for communication packets and also for headers. 98784.doc -21 - 1338231 and 5 generated a super-fast Ethernet packet header for the received packet, = SuperSpeed Ethernet protocol changed the size of the packet. The newly formed • = l (or multiple packets) is transmitted to the Ethernet (EMAC) interface hardware module, and the soap FIFO buffer. A similar task occurs to perform the reverse protocol conversion, ie, the packet is transmitted from the Ethernet to the Fibre Channel network. Figure 6 shows the logical representation of this prototype single-wafer Fibre Channel/Ethernet protocol converter implementation. This embodiment uses 14 processors, where they participate in the Fibre Channel, (FC) to Ethernet conversion depicted in the processing block shown in Figure 6, where at processor η Receiving the redundant input ί packet is the same as the day, and the reverse conversion process is depicted in the processing block 27〇 in FIG. The assignment of the protocol task to the hardware resource is performed according to the process flow depicted in FIG. 6, where the execution is as follows: the processor 管理1 manages the Fibre Channel into the DMA machine, (setup) and the target memory area assignment; the processor is based on The packet header is sent to one of the four processors p3 to %, and the packet header information is required to perform environment switching, packet verification, and confirmation packet generation, and the processing P7 performs the Ethernet network road sign. Generated, transmitted to Ethernet

After the network interface, the A #枓's establishment is returned and the memory area block that is no longer linked to the free buffer is selected. Similarly, the L-data machine from the Ethernet to the Fibre Channel network is handled by the process of stealing P8 to P14 as described in FIG. The indicator of the packet to be transmitted to the Ethernet is placed in the queue 249 and the indicator of the packet to be sent on the Fibre Channel is placed on the Fibre Channel outbound queue 259. Other network protocols or protocol conversions can be constructed in a similar manner. For example. 'In the construction of the lScSWTcp / ip agreement, you can use the existing program code of the 98784.doc -22· 1338231 2:::uniprocessor embodiment, only need to adapt: ° and effort to adapt it to Architecture. More specifically, it is necessary to construct -. Distribute and collect (marked as ^ and marked as ρ9^] 4 processing write. ^ for receiving path and transmission (four)) task, but the network protocol is adapted to: mark There is almost no change and ordering on the processor from W〇 to P13. The number of parallel running protocol tasks, the number of devices, must be scaled to meet timing needs based on task complexity. For example, in the example depicted in Figure 6, the 'lSCSI protocol conversion may require " to perform a single-wafer protocol conversion with _. Processing benefits, packet processing on multiple processor cores can be performed by: following the subscription to completion method (run_to_completi〇n _(10) called a single processor where = packet m performs all processing operations or via pipeline operation The packet processing operation is divided into a plurality of pipeline stages assigned to the independent processor. In the embodiments described herein, the pipelined method provides: better utilization of hardware resources such as cache memory. Examples of network operations for the second-level line are header processing, packet verification, exact response generation, packet reordering, and message composition, and end-to-end control: The scheduling of the agreed tasks assigned to the processor is statically executed during the period, meaning that each processor 2〇5 performs the same group operation on various packets: as such, to avoid association with dynamic memory management such as garbage collection ((10)agec〇lleCtl〇n) consumes 'using static memory management. Initializes all used memory structures during system startup. 23 These structures are included in the storage data block. The memory area 275, the memory 280 for the existing network connection = 98784.doc • 23 · !33823l and the status information, the code 285 . ~ : The various memory structures used in the architecture The provision of the two diagrams allows all sub-processes of the packet-contraction conversion to be included in the design of the SoC-type design: saponins transfer the final completed packet to the system bus or into the system: ^ and the sink can be as shown in Figure 7. As shown in the figure, the data packet will be stored. The key is cleared (4). The incoming field obtained from the link list is composed into a free buffer. In the packet processing period::: The lower-body area indicator is in the processor. Transfer between. _== The memory pack of the packet is transmitted to the outbound network interface, and the buffer = after the packet is processed, the seal is sealed. 欸 The thief returns to the free buffer clear as further depicted in Figure 7, ::: Γ 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在The index of the second packet. When it is processed, it is listed as I: Yes, it is placed in the pipeline. τ- locking thread of execution work. In order to ensure the proper functioning ⑽ body access to the conflict, the use of

The second consideration is that all pipelines need to be viewed according to the packet environment and == outside: the processing time at each pipeline level depends on whether the packet is:: the I packet at the sequence packet, whether it carries the link control information, and Whether it is a request message of 'S 98784.doc -24- 1338231. If _4. in the pipeline stage is slower than the other stages, then its working Y-column may become overloaded, thus changing λ k to a bottleneck. This is remedied by using several processors (e.g., round ports, P1 to P4) operating in parallel at the same pipe level. Since the processing time in the pipeline stage can vary between packages, all processing benefits cannot be fully utilized. The reality is to produce a match between the pipeline stages by providing sufficient buffering and decoupling logic.

Work (4) Assignment of multi-processors with tasks requires invocation-task assignment processing (10) such as 'Figure 7 for the processing of ΙΙΡ5« as "MT"). The packet assignment method is simpler so that it is executed in a shorter processing time' and does not result in performance degradation due to resource contention and locking. Real If is 'for Fibre Channel embodiments, the binary classification algorithm that causes all packet processing to belong to the same environment group by a single processor to store the information about the backup domain into the cache of the processor In the case of the building, the resource competition is reduced and the average access for obtaining this information is maintained at a lower level by using the simple hash function. In the embodiment - the packet classification and processor assignment tasks only introduce about 50 commands. However, it should be understood that this visual design choice changes and can be arbitrarily changed within the range of 35 to 200 instructions. In the depicted embodiment, as few instruction sets as possible 'e.g.' are used to vary within the range of 35 to 5 instructions. In a typical network traffic at any given time, there may be more active environments than the processor, and several different environments can be assigned to a single processor at the same time. In the worst case, it is possible to assign all packets to only one processor, causing them to be overloaded. However, the network that runs the actual application is not a problem. The single-wafer protocol conversion architecture is cellular, allowing the design to be scaled (cust°m). In the meter, the number of processor cores and embedded memory blocks can be easily adapted to the needs of the application without significant design changes. For example, in the following network applications, the computing power required for a multi-processor protocol converter operating at a line speed of 10 Gb/s can be varied, as will be described below. It should be noted that in this respect, the protocol converter design actually processes and delegates to the network of each sub-processor and the division of the agreed resources by layer design, embedded memory, by different processing. "Applicable to" other network processing functions, without limitation, means that the processor is independent of a special network function, which differs from the prior art in that each processor only has a given potential function. Such as TCP/IP offload function, frame classifier function, pre-processing function, hardware accelerator, (4) C or data processing function, etc. In the single-chip protocol converter 350 of the present invention, or as an embedded macro core 55 Well, as long as there is enough processing power to scale the intended operation, the same processor and area memory can perform different network functions (ie, operation ^ some examples are listed below: one charm-conversion: 14 Processor (ie, two 8-core processor clusters). One includes 64-bit tubyte memory, 64 κ-bit data SRAM, P〇werPC440 (or other processor), and circle 5 The other macro chips shown in Figure 6 would require approximately 35 square millimeters in a 13 m ASIC technology. T.CP/JP#p . 3 2 processors, meaning four processor clusters, 98784 .doc -26- 1338231 Assuming the m κ byte of _ cache memory and i28 〖 byte of SRAM, this will require 5 〇 square millimeters in the above technology. 128 processors (estimated) That is, 16 processor cores. Heart, t set. Assuming 5UK bytes! _ cache memory and SRAM bit SRAM, the resulting chip will be about 15 〇 square millimeter. Or when the market conditions change, the same basic architecture (we can build # more sub-processors within the chip required for a given application or as a s〇c embedded macro) is applicable. For example The architecture is adapted to reconfigure the wafer into a firewall processor, or, a protocol converter " or even reconfigure into a completely new design or agreement that is still unconstructed. Therefore, a basic The design scales to many applications and potential functions. It can be selected by simply redesigning the wafer. The number of processors and memory units, followed by the appropriate software code or version level to change the core or network function of the chip or embedded macro. By statistical simulation of the core performance of the intended new function, select The number of selected processors and memory cells for the new protocol function. As mentioned earlier, the protocol converter can be constructed as a stand-alone integrated circuit chip on a separate semiconductor substrate, or embedded as a type of s〇c A macro of design, FPGA, DSP, etc. An example of a co-transformer constructed as an embedded macro core in SoC (system wafer) design 400 in accordance with a second aspect of the present invention is depicted in FIG. . It should be understood that since all required is only a standard bus interface or bridge for transmitting the completed data packet (converted or unconverted), the macro is not limited to the Soc design, but may also be constructed. Standard SP 4 controller, fpga 'ASIC' and microprocessor. The term "s〇c, · 98784.doc • 27· 1338231 is generally used to define a system on a wafer having at least one processing element, a memory element, an I/O interface, and attached to a regional bus or multiple The core of the bus on the wafer. As shown in FIG. 8, one embodiment of a SoC 400 including an embedded protocol converter macro core 550 (also depicted in FIG. 5 as a stand-alone wafer design) includes a CPU or MPU component 425 (here illustrated as IBM) PowerPC 440, however, it should be understood that in addition to PowerPC, other SoC processor cores such as ARM, MIP, and the like can be constructed); a regional SoC bus 210 (illustrated in Figure 8 as IBM CoreConnect PLB 210 ( Processor area bus)); an optional slow bus (illustrated in Figure 8 as IBM's on-wafer bus or OPB 240); and any number of SoC components (cores) such as those shown in Figure 1, It includes an SRAM 415, a DDR controller 418, a PCI-X bridge 422, a DMA 426 and DMA controller 428, an OPB bridge 429, and the like. The OPB 240 is connected to other devices including one or more of the following devices: a RAM/ROM peripheral controller 445a, an external bus master 445b, a UART device 445c, an inter-bus (I2C) interface 445d, and a general-purpose I/O interface 445e. And gateway interface 445f. The embodiment depicted in FIG. 8 includes a self-contained, processor-based protocol converter 550 that is integrated into a single-chip protocol converter or embedded macro core in SoC system 400, and via bridge 224 and PLB. 210 communicates with the processor core 425 bus. As depicted, the processor-based protocol converter macro core 550 includes one or more processor clusters 200, one or more regional memory banks 215 for storing data and/or instructions, such as the depicted implementations. The area interconnecting member of the interleaved exchanger 220 in the example, or equivalently 98784.doc -28-1338231 a construction or χX exchanger and the like, and at least for at least two network protocols Two media access control (MAC) interface units 175, 185 (media access control). As shown in Figure 8, there are individual externals that can be physical layer wafers (PHYs), SoC embedded MAC or PHY functions, or external protocol chips.

The MAC units 175, 185 of the MAC interface devices 475, 485 are separated from the SoC or host card. That is, the MAC 475, 485 shown in FIG. 8 may include a Fibre Channel hardware assist core and an Ethernet 1/1 〇〇/1 G EMAC, however, may include an interface for any protocol, and The outside of the wafer is integrated into a separate MAC or PHY device (solid layer wafer) or integrated outside the wafer on the area card. In today's slow applications such as automated applications or home network connections, this may be what we need. Figure 9 illustrates the processing flow for a contracted conversion of a single packet to an external protocol interface within the embedded s〇C. When the area memory control packet processing and DMA transfer in the macro set, the packet may be transferred from the interface to the second I/O interface or output to the s〇c bus line 21 after the protocol is converted from the macro. And eventually to the host system bus 223 (eg, PCI-X 133 MHz or similar equalizer as depicted in Figure 9). Preferably, the communication is dupiex, meaning "including a link capable of communicating in the direction of transmission and reception. With the example depicted in Figure 9, the display into 8 packet conversion has a packet according to the first protocol, for example, where the external protocol chip, macro 4EMAC (external Ethernet/〇) in S〇c The interface 485 receives the 1G Ethernet packet, and forwards the 1 (3 Ethernet packet to the EMAC 185 internal FIF port of the converter macro, and enters the interior of the macro on the error exchanger 220. In memory 215, the internal memory (SRAM, DRAM, etc.) of the macro collects 98784.doc • 29-Ether shoulder package, and the controller function on the chip passes the interleaved switch. The network packet is transmitted as shown in Figure 9, and the sub-sector of the cluster should understand that, as described in this paper, due to parallelism, pipeline operation, and multi-threading, the protocol conversion process is implemented in the embedded protocol conversion for protocol conversion. The macro of the macro 55G is equally suspended in several sub-processors, and the conversion process is matched with a processor. Therefore, even if there is only one round, for example, A is drawn from "proc.i" to "pr〇c". 3"and go to "B", but in fact the packet is already in; It is split among several processors. Although the protocol A to B packet conversion is depicted in Figure 9, the alternative processing will be included on the other side of "B completion" to make the agreement B, the packet enters and is agreed to #] ( Exit on the eight sides. It should be understood that the b, and A' processing flow will be on the other side of the two-way duplex link. The actual agreement is enforced on the processing elements included in the embedded protocol converter macro core 550. The conversion code. The macro has a number of parallel running processes P0, the group is used for each direction (ie, each of the processes of receiving and transmitting, etc. is mapped to be labeled Proc.0' Pr〇cj, Pr One of the macro processing elements of 〇c 2, etc. Three different processes are provided in the embodiment to operate on the processor of the embedded SoC macro, the processing spoons including: i 1 'Gold: Processing Tasks to the Processor 2. 1 Processing: Agreement Processing Task 3. Up_1_: Set the DMA SoC controller to transfer the packet from the internal memory of the core, and execute some memory after the packet has been transferred Management function. ~ between these processes The communication system is completed via a work queue such as the basic dedicated area in memory 98784.doc -30· 1338231 depicted in Figure 7. The idle process determines whether it has an application order by periodically polling its work queue. The work of the Coordination Hub core builds all the specific protocol tasks required, such as splitting the data into a series of 1 packets, generating 1 packet headers, generating Ethernet packets, etc., and moving the packets back to B. Too much network MAC macro. If there is a need for a retransmission packet, as defined by the agreement, this will occur without interference from the s〇c area, (4) packet/data transmission request or actual data. The transfer to external DMA or DDR memory requires that after the protocol "A" to B protocol conversion, the packet is transferred back to the macro on the regional wafer. It is hidden, and one end of the data is a signal. From there, the regional macro memory and embedded area DMA controllers transmit the converted packets via interleaved switches, Fibre Channel interfaces, and finally external I/O interfaces. Alternatively, the fiber channel interface can have an embedded controller to transmit the final converted packet. If desired, the external SoC DDR 41 8 or DMA 426 can additionally request that the packet be transferred to the regional s〇c bus via the bus bridge and ultimately to the host system bus 223, which is sent with the self-protocol converter interface The packet is relative. Similarly, host bus 223 can send a packet or packets for protocol conversion to the macro and receive a converted complete packet or transmit to external protocol interface 475, 485 depending on the individual protocol and packet type. Figure 10 illustrates an exemplary process flow for a contracted conversion of a single packet received from host bus 223 and transmitted to an external sc: interface 485 for transmission. For example, in the example process flow illustrated in FIG. 10, the slave system bus 223 is sent (from the host system bus 223) - the Fibre Channel protocol packet is sent to the SoC protocol converter macro 35. Transfer to the external Ethernet interface 1 G EM AC interface 485 for conversion and 98784.doc -31 - 1338231. As shown in FIG. 1 , the SoC main processor (P〇werpc 44〇) sets a data processing request and sends the request and the indicator of the data in the external Ddr memory to the protocol converter via the bus bridge 224. The core of the macro is 550. An interrupt signal is generated in the depicted embodiment, but this can be constructed by writing data to a dedicated register or a pre-pointed location. The embedded protocol converter macro core 55 identifies the request and launches the dma engine to transfer the data from the external host or SoC area memory to the macro area 6 memory. Data (e.g., 'packet #B) is transmitted to the regional memory 215 of the macro via the regional s〇C bus and the bridge bus. When all the data is transferred, the SoC processor is notified that the task is completed. This can be constructed by sending to the PowerPC 44 an interrupt or writing some pre-defined locations periodically polled by the p〇werp C44. The Fibre Channel packet (8) is self-assembled by packet partitioning as described herein by a work queue, a collection sequence, and a processor as a task dispatch processor (MT) (as shown in Figure 7). The area memory is transferred to multiple sub-machines to complete the protocol conversion, for example, from the agreement "b" (fiber-optic type) to the agreement A" (ultra-high-speed Ethernet type), then the completed packet is The interleaved switch 22 is transferred back to the memory of the regional macro. The area DMA request transfers the packet, Α, and memory from the macro to the external Ethernet interface 485 for transmission and conversion. The methods described herein take into account a reduced number of reduced I/O cards and chips, greatly improved flexibility, higher density of network functions (more processors attached to a zone or host bus), higher Agreement processing speed 'improved frequency 98784.doc -32- 1338231 wide, less memory competition, end system user flexibility, network design / upgrade easy' and compared to today's existing agreement conversion Improved agreement conversion. Although the present invention has been particularly shown and described with respect to the embodiments of the present invention and the embodiments of the present invention, it should be understood by those skilled in the art In the case of a versatile mouth, the foregoing and other changes in form and detail may be made therein. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a typical SoC employing a single processor in accordance with the prior art; FIG. 2 is a block diagram depicting a typical SoC employing a processing accelerator on the market today according to the prior art; FIG. To depict a block diagram of a M〇tor〇ia MPC5554 microcontroller (incorporated with an interleaved switch SoC) according to the prior art; FIG. 4 is a diagram depicting Brocade's φ SilkwormTM construction application for s an network according to the prior art. FIG. 5 depicts an exemplary general view of a single wafer protocol converter core design in accordance with an embodiment of the present invention; FIG. 6 is configured from a fiber channel to an embodiment of the present invention to Illustrative illustration of a protocol core of an ultra-high speed Ethernet single-chip protocol converter; FIG. 7 illustrates an exemplary memory configuration within a single-wafer protocol converter in accordance with an embodiment of the present invention; FIG. One of the second aspects of the protocol converter chip configured 98784.doc • 33 - 1338231 into an embedded macro in the SoC design; Figure 9 depicts the self-SoC macro set according to the present invention to Figure 8 External system I / SoC packet data protocol converter stream of O; and Figure 10 depicts the present invention from the host bus to an external apparatus SoC interface seal embodiment of the packet transfer protocol converter SoC exemplary packet data flow. [Main component symbol description]

15 ' 230 ' 415 Area SRAM Memory Unit 18 , 418 DDR Controller 20 System Chip Design 21 Area Processor Bus (PLB) 22 ' 422 PCI-X Bridge 24 Wafer Peripheral Bus (OPB) 25 PPC 440 (Power PC) 25 processor core / PPC440 26, 426 DMA 28, 428 DMA controller 29 ' 429 OPB bridge 33 processor core timer 35 interrupt controller 39 dedicated processor core (accelerator) 39a, 39b additional dedicated processing Core 45a ' 445a RAM/ROM Peripheral Controller 45b, 445b External Busbar Master 45c, 445c UART Device 98784.doc • 34- 1338231

45d ' 445d Inter-IC Bus (I2C) Interface 45e ' 445e Universal I/O Interface 45f > 445f Gateway Interface 50 Media Access Control (MAC) Protocol Device 72 Interleaved Switch 75 SoC Design 78 External I/O Bridge 100 Brocade System 102 Fibre Channel to Fibre Channel Routing 104 iSCSI to FC Bridging 110 Fibre Channel to FC-IP Translation 175, 185 Media Access Control (MAC) Interface Unit 190 Fibre Channel Communication Link 195 Ultra High Speed Ethernet Communication Link 200 Processor Cluster 205 Processor Core 208 Instruction Cache Memory (I-Cache Memory) 210 SoC Processor Area Bus 215 Area Memory Group 220 Interleaved Switch 223 External Host System Bus 224 Bus Cascade Macro 225 Arithmetic Logic Unit (ALU) 226 Register File 98784.doc -35- 1338231 227 Instruction Sequencer 240 249 259 260 270 275 280

285 290 300 350 400 425 OPB Worklist Lists Work Lines Processing Blocks Processing Blocks Memory Area Memory Codes Work Array Fibre Channel to Ultra High Speed Ethernet Single Chip Protocol Converter Basic Compact Converter Chip SoC (System Chip) Design CPU or MPU Component

475, 485 550 External MAC Interface Device Protocol Converter Macro Core 98784.doc 36-

Claims (1)

1338231 Patent Application No. 094100086 Replacement of Chinese Patent Application (99-Year) X. Patent Application Range: 1 · A single-wafer protocol converter integrated circuit (IC) comprising: an embedded circuit for protocol conversion System-on-a-chip (soc) core; a microprocessor; and a regional system communication bus, the embedded system-on-chip (SoC) core for protocol conversion includes: a processor-based subsystem comprising two Or more than two processor cluster assemblies, each processor cluster assembly comprising: one or more sub-processing cores, each of which is capable of performing an operation of constructing a protocol conversion capability; and one of the processor cluster assemblies The area storage device associated with the sub-processing core for storing at least one of data and instructions in each processor cluster assembly; and a region interconnecting component located at each of the processor clusters The assembly is configured to enable communication of instructions and data between the area storage device and the or the sub-processing cores; or a plurality of interface devices, Enabling to receive and transmit a communication packet in accordance with one or more communication protocols; and a second area interconnecting member located in the embedded core for enabling two or more processors Communicating between the cluster and the interface device or between two or more sub-processor cores within the -processor cluster and the interface device; and - bridging device 'is enabled to enable Transmitting and receiving data communication between the second area interconnecting member of the dormant SoC core for protocol conversion and the regional system communication bus of the single-chip protocol transfer 98784-990811.doc 1338231 converter ic The 1f interface device is configured as an incoming network interface adapted to receive a plurality of packets generated according to a first protocol type for forwarding to the stylized Processing a protocol conversion in a processor cluster assembly or a processor cluster assembly of the processor to construct a protocol conversion, and the interface device is configured as an output interface device to output: the second protocol Packet type of the plurality of the converted, thereby completely integrated in the single protocol conversion process performed within the circuit chip. 2. 3. 4. The single-wafer protocol converter IC of claim 1, wherein the interface device comprises one or more from the group consisting of:: a customizable media access control interface device (MAC), and - a protocol interface accelerator device for receiving a packet of a particular agreement. a single processor, wherein the processor or the processor, the corresponding component, the component, and the interface device: "the two-region interconnection protocol and the first heart can perform the first weight Fixed frame. a. The size of the packet required for the conversion is changed and the single-chip protocol converter design is additionally adapted to enable the conversion of the packet in a single protocol. Receiving the single-chip protocol #1 of the request item 1, the first type of 4+ h IC, the hunting is to divide the received one of the packets into a #% f β processor core, 1 in the seven-. One or more sub-processes and the specific processor core run the same set of instructions and /, special agreement processing pairs. 98784-990811.doc 5 · Such as the single-chip protocol converter Ic, where the received The instructions for the contract conversion are completely contained in a processor cluster assembly, and the processing includes sub- (4) materialization operations to be processed by the different resources on the single-chip protocol conversion benefit IC. Wafer protocol converter 1 (:, where the second The area interconnecting member includes an interleaved switch. 7. The single-chip protocol converter Ic, for example, further includes a one for adapting the single-yang film to the fixed-turn & Or a component of a plurality of functions. 8. A single-chip protocol converter Ic, such as a μ, wherein the protocol conversion processing is included in the core of the embedded SoC protocol conversion macro. a wafer protocol converter Ic, wherein the single-chip protocol converter 1C includes a plurality of components for protocol conversion processing, the components including receiving one of a communication packet to be converted and storing a protocol conversion from one or more interface devices An embedded memory storage component of the application, the control information, and one of the materials used by the application. 10. The single-chip protocol converter ic of claim 1, wherein the configurable interface device is capable of Receiving communications in accordance with a network communication protocol, including one or more of the group consisting of: Fibre Channel, Gb Ethernet ( Ethernet), Infimband, iSCSI, FC-IP, TCPHP, IP, MPLS, VoDSL, CAN, and SAMBA. 11. An SoC integrated circuit (IC) device including a processor component, an area memory storage component, and A regional communication bus, and a 1-sided component for receiving and outputting multiple communication packets for the root type 98784-9908ll.doc 1338231, and an embedded SoC protocol converter giant core "' The SoC Collaboration Core "includes" the ability to receive multiple packets, process the packets, construct a protocol conversion, and generate - a plurality of packets converted for output by the first-fourth (four) type, wherein The embedded second, SoC protocol converter macro core contains ·· Λ ^ 7 to. A processor-based subsystem that includes two or more processing state cluster assemblies 'per-processor cluster assembly. - or multiple sub-processing cores, each of which has a contract conversion capability; Constructing a regional storage device that is associated with at least one of the data and instructions in the storage-per-processing assembly of the embedded protocol converter core or the sub-processing core; and Dn-fruit- a first-region interconnecting member 'which is located in each of the processes' for enabling communication of instructions and data between the area storage device and the or the core; one or more interface devices capable of Receiving and transmitting a communication packet according to - or a plurality of communication protocols; and a second area interconnecting member 'which is located in the embedded protocol converter' for enabling processing in the two or more Between the assembly and the interface device or within a processor cluster: one or more of τ, ^ , where the core and the interface are in communication, ΒΊ where the interface is Configured as one Into the Tan network interface, the entry network 98784-990811.doc & "face" work is suitable for receiving multiple packets generated according to the -----type of the package - it is used to transfer to the program to handle the packets a processor assembly or a sub-processing core within the processor cluster assembly to construct a protocol conversion 'and the interface m is configured as an out-of-interface device to output a converted plurality of packets of a second protocol type , by which the single integrated circuit chip is completely processed in the protocol conversion process. 12. The s〇c IC device of claim 11, wherein the interface component comprises one or more from the group consisting of: - a programmable media access control interface device (MAC), and - a protocol interface accelerator The device, the protocol interface accelerator device, receives the packet from the external link and forwards the packet to the interface device of the embedded protocol converter core device. 13. The device of claim 12, wherein the or the configurable interface device comprises one or more from the group consisting of: a programmable media access control interface device (MAC) And a protocol interface accelerator device for receiving a packet of a specific agreement from the s〇c(1). ^, such as a requesting UiSoc IC device, wherein the processor cluster assembly, storage device, interconnecting component, and interface The device cooperatively enables resizing and reformatting of the packets required to perform the conversion between the first protocol and the second protocol, the single-chip protocol converter core device being additionally adapted to enable a single Converting the received packet between different version levels of the protocol type. 15. The SoC IC device of claim 11 to partition one of the received first type packets into one of the embedded protocol converter cores or a plurality of sub-offices 98784-990811.doc 1338231, wherein each processor device runs an identical set of instructions and is paired with a specific protocol process, wherein the group for the agreed conversion The instructions are completely contained within a processor cluster assembly, the process comprising splitting the protocol operations for processing by different resources on the single-chip protocol converter Ic. 16 as claimed in the uisoc ic device, where Or the configurable interface device monthly fc* is capable of receiving communications according to a network communication protocol comprising one or more of the group consisting of: Fibre Channel, Gb Ethernet, Lnfiniband, iSCSI, FC-IP, TCP/IP, IP, MPLS 'VoDSL, CAN and SAMBA. 17. The soc IC device of the item 14 is configured as a co-processing, hybrid ASIC, or other network. In one embodiment of the method, the processor component includes a network processing device for interconnecting the embedded protocol converter core device with the network processor device. Item 17 of the SoC 1C device, wherein the network processor embodiment —PCI-X Bridge 'A direct memory (OPB)〇 98784-990811.doc 20. The version of the package is available for output. ~ Long: The S〇C iC device, which or the sub-processor core within the processor cluster assembly performs one or more tasks including the following tasks: read, body control, packet transmission, header And tail generation or manipulation, reload size re-adjustment, and packet collection to convert a packet or a plurality of packets of a first agreement type into a second packet or a plurality of packets of a second protocol type, The packet of the second protocol type or the packets are transferred to a second foreign network interface device in the protocol converter chip for transmission. 98784-990811.doc