TWI336184B - An ofdm system employing pilot symbol and cyclic prefix to achieve synchronization - Google Patents

Description

1336184 IX. Description of the Invention: [Technical Field] The present invention relates to an orthogonal frequency division multiplexing system, and more particularly to an orthogonal frequency division multiplexing system that achieves synchronization by pilot signals and cyclic prefixes. [Prior Art] Orthogonal Frequency Division Multiplexing (OFDM) is a digital communication technology that uses multi-carrier modulation, and the bandwidths of the majority of sub-carriers used overlap each other. And they have orthogonality with each other, and the bandwidth use efficiency is greatly improved. Figure 1 is a conventional OFDM system by D. Landstr6m, SK Wilson, J.-J. van de Beek, P. 0dling, and P. 0. B6rjesson, 2002, in the journal "IEEE Trans. Commun." The published paper "Symbol Timing Offset Estimation in Coherent OFDM" is disclosed. The transmitter 8 of the OFDM system of FIG. 1 includes a modulation unit 81, an inverse fast Fourier transform unit 82, and a cyclic prefix addition unit 83. The receiver 9 of the OFDM system includes a time synchronization unit 91. The modulation unit 81 receives a bit-stream and uses a Quadrature Phase Shift Keying (QPSK) to group the signal of the bit stream every 2 bits. The signals of each group are converted into one of 22=4 modulated signals in four quadrants on the complex coordinate plane. 6 1336184 For example, if the signal of the bit stream is [Ο, Ο, Ο, Ι, Ιβ, 1"]', the QPSK modulation unit 81 signals the signal [0, 0], [in the bit stream] 0,1], [1,〇] and [1,1 ] are converted to modulated signals, respectively, and the values are equal to 1+ζ·, -Ι+i·, -1- jf and ι_ζ· on the complex coordinate plane, respectively. . It should be noted that among the set of modulated signals (with #pen signals) output by the modulation unit 81, only one of the (^&lt;" data signals is converted from the bit stream to other signals. It is a pilot signal known to the transmitter 8 and the receiver 9. Therefore, in fact, only one of the modulated signals is actually transmitted with the message to be transmitted, and the pilot signal has no message and these The pilot signal is interposed between the data signals on average. The inverse fast Fourier transform unit 82 converts the modulated signals into a corresponding time domain by using an inverse fast Fourier transform (IFFT). The cyclic prefix adding unit 83 receives the time domain signals in the form of parallels, and converts the time domain signals into a serial form, and the JV in the time domain signals - Ι ~ ΑΓ -7 signals < a total of Z and / ^ copied to the front of the time domain signal as a cyclic prefix. Then the loop prefix adding unit 83 sequentially outputs the added loop at a frequency of ί〆 Time domain t number 'To generate an OFDM symbol and output the OFDM symbol to the receiver through the transmission channel in a symbol duration. The receiver 9 transmits the transmitter through the transmission channel. Each OFDM symbol is sent, and the receiver 9 receives a signal of a fdm symbol at a frequency of 7. 7 There is a multiple it minus 4 in the transmission channel between the transmitter 8 and the receiver 9. Μ&quot;1111 -111), causing a time offset, causing the receiver 9 to find the starting point signal for each -0FDM symbol. "The time offset estimate proposed by D· Landstr0m is the transmission of the transmitter $ scoop. The § number is divided into two parts, namely, assuming that a transmitted symbol is 戴, a child is wearing a wave, and one of them is a pilot symbol. Γ is am solid: a collection of ^. The first part of the transmitted signal contains a signal subcarrier, and the mathematical model can be written as: χ 1 N-\ jlmk 5(&quot;)=VF Σχ^6~

Viv neiO^Nl^r where 'cafe is' the data symbols transmitted on subcarriers, the average energy is ~=E{|jc(8)12b. The second part contains one pilot symbol subcarrier, and the mathematical model can be written as j2mk (10) The pilot symbol transmitted on the subcarriers is assumed to be σ^2=Ε{|ρ(")| 2} in the average monthly t&gt;. Under the accommodative Gaussian white noise (AdditiveG (10) to capture Noise 'AWGN) channel, the receiving signal kiss is: r(k) = [s(ke) + m(ke)] +w(k) ” The time offset of the unknown integer value, the average value of the statistical property (Mean) is 0, and the variance (Variance) is ~ 2. The time synchronization unit 91 uses two characteristics of the received signal for estimating the time offset: 5 (8) The statistical characteristics and the known information of the ring. It is assumed that the statistical characteristic of the time domain signal S (9) is a Gaussian program with a variogram of ασ/(β=泽%, usually a subcarrier using a large number of transport data in the OFDM system (% &lt;&lt;7\〇»When the system uses the cyclic prefix, the end of the # sampling points of the transmitted signal is copied to the front end of the symbol, ie for ke [0, LU, φ) =φ+Ν),m(k) = m(k+N). According to the above mathematical model, the autocorrelation function of the received signal is: 1, k = l Ρ, k — l = ~N,k^[e , Θ + L- A 〇, k l l other = ^Je[e, θ + Ll]

Cr(^j) = where ασ) aSNR «σ; + a2w ~ aSNR + 1 The time offset estimate 0 can be obtained by the maximum log likelihood function Λ(0), ie: Λ Θ = argmax{A( ^)} where ' Λ(0) can be expressed as: λ(θ)=ρλ»+(ι-ρ)λ,) where: θ+χ-\

Ac/,W = Re{ + η two θ

(j Θ+LX -y ζ 卜 (8)|2 + 卜 (“ + Α〇|2 represents the contribution of the cyclic prefix redundancy to the estimated value of time offset 0 0+: L-\ AP(^) = (l + p)Re{ (n)m(n ~Θ)} η—θ e+i~\ ~ pRe{ ^(r(n) + r(n + N)Ym(n -Θ)} η= θ ~(θ) represents the contribution of the information carried by the pilot data to the estimated value of the time offset θ. The time synchronization unit 91 gives the weight of the cyclic prefix and the pilot data differently according to the magnitude of the value of ρ, and the value is based on the signal. The odds ratio (hereinafter referred to as snr) and the number of pilot data are determined. See Figure 2'. Figure 2 is the case of α = 〇 · 〇 9, SNR = 8dB and # = 544, Acp (9), Λ ρ ^ and eight (9) The relationship with the time index. And Λ^(θ) is essentially the correlation operation of the signals from the # sampling points. Because the characteristics of the OFDM symbols themselves can be found at the starting point of the symbol - a clear However, the time point is roughly estimated, and ~(θ) can be regarded as a filter action, taking the pilot symbol that the receiver 9 has known in advance to the receiver 9: matching operation 'because the pilot data is evenly spaced, Will get multiple 3 unclear but obvious (Distinet) peaks Value. Using the appropriate weights to properly combine the two likelihood functions, a significant peak can be produced. ~(9): The resulting peak 疋 is used to fine tune the approximate estimate of ~(θ) to get a more accurate symbol. The starting point. I have to pay attention to the fact that when the SNR is very high, the estimated value is mainly dominated by the circulatory word; when the SNR is very low (1), the estimation is mainly based on the information of the pilot data. 'λ Most communication systems will suffer from the chopping frequency offset H ϋ The representation of the received signal kiss can be corrected to 10 (1) 6184 r(k)={s(ke)+m(k-ey^e(j2lcekw (k) At this time, the operation performed by the time synchronization unit 91 is similar to the above, and the next day (4) is replaced by the operation of the absolute value, but the operation of the real part of the likelihood function is replaced by the operation of the absolute value. (10)) The peak constructive contribution is the third. Since the SNR is unknown at the receiver 9, the SNR must be designed to be SNRf. η, ii tc into τη, ^ f, xed逋* SNRnXed is Determined by the simulation. The estimated time offset value g becomes: Λ Θ = armax{pAcp(e)+(lp)Ap($)} where ' p is a design parameter whose value is p=聪(五)―(snr(五)+ι). Λςρ(θ) Σ^(«Μ« + λγ) γΣΚ«)| +Κ«+τν)| θ+Ll Λρ (6)=( 1 +p) ΣΓ*(η)ιη(η-0) θ+Li Ρ X(r(n) + r(n + N))*m(n-0) Conventionally, the transmitter 8 of this system sends out In the signal, not all of the signals based on the bit stream are interspersed with some pilot signals, which makes the bandwidth use efficiency poor. In addition, in the case of (4) lower (ie weight (four)), the estimated value of the starting point of the symbol depends largely on the information of the pilot signal. Therefore, the estimated value of the time offset is only related to Λρ(9), and the way according to the pilot signal is inserted. In the symbol interval, there will be several peaks of the same size (11 1336184 as shown in Figure 2, _ ρ), so it is impossible to know which peak is the correct one, so it is easy to cause the estimated starting point. [Invention] [4] The present invention (4), that is, provides an orthogonal frequency division multiplexing system that effectively utilizes the bandwidth and accurately estimates the time offset. Eight, the present invention uses pilot signals and cycles. The orthogonal orthogonal frequency-frequency multiplex system with a prefix includes a transmitter and a receiver. The transmitter includes a modulation circuit, a pilot signal generating circuit, an adder, an inverse fast Fourier transform unit, and a The loop prefix is added to the unit. The modulation circuit receives a bit stream, and the bit stream is transformed into a set of modulated signals. The pilot signal generating circuit generates a set of pilot signals having the same number as the modulated signal. And The periodic autocorrelation function of the group pilot signal has a distinguishable peak. Knife addition 1 § superimposes the set of modulated signals with the set of pilot signals to generate a set of composite signals. The converting unit receives the combined signals and converts them into a set of conversions. a cyclic prefix adding unit adds a partial signal of the set of converted signals to a prefix of the set of converted signals to form a symbol. The receiver includes a time synchronization unit, and the time synchronization unit is based on the pilot signal. The distinguishable peak of the periodic autocorrelation function estimates the time offset of the received symbol to obtain the starting point of each symbol. [Embodiment] The foregoing and other technical contents, features and effects of the present invention are related. It will be clearly shown in the following detailed description of a preferred embodiment with reference to the drawings. 12 1336184 ▲ Participation 3' The present invention achieves synchronous orthogonal frequency division multiplexing system with pilot signals and cyclic prefixes. The preferred embodiment includes a transmitter i and a receiver 2. The transmitter 1 includes a modulation unit u, a straw adjustment, an early detection 11, and an inverse fast Fourier transform. ': 2 and a cyclic prefix are added to the unit 13, the receiver 2 includes a time synchronization unit 21 and a frequency synchronization unit 22. The modulation unit it U includes a modulation circuit (1), a pilot signal generation circuit 112, a first multiplier 113, a second multiplier 114 and an adder 115. The modulation circuit Ui receives the signal of the one-bit stream and uses the _ modulation technique to divide each of the one-bit stream signals into two The bits are a group of signals, which are converted into # mutated signals in parallel form, which are signals transmitted corresponding to the moxibustion subcarriers. The modulation circuit lu can also be other techniques such as quadrature amplitude modulation. (QAM) modulates the signal of the bit stream. The modulation circuit 111 is similar to the conventional modulation unit 81 (refer to FIG. 1), and therefore will not be described here. The first multiplier 113 will modulate the modulation. The # modulated signals outputted by the circuit 111 are respectively multiplied to output a signal S(k\/\ - β, which is entangled in a side-by-side form, where ^ is a proportional parameter. The pilot signal generating circuit 112 outputs # pilot signals in a side-by-side form. In the preferred embodiment of the present invention, the pilot signal generating circuit 112 generates a transparent sequence iY^) (A: = 0 Α /_&quot; as the pilot signal. For the introduction of the transparent sequence, please refer to the paper "Semi-Blind 13 1336184" by CP Li and WC Huang in "Proc· Vehic. Techno" in 2006.

Channel Estimation Using Superimposed Training Sequences with Constant Magnitude in Dual Domain f〇r 〇fdm Systems” The transparent sequence iY illusion~ can be expressed as equation (2_l): p{k)=eJl^L] (2-1) K N )

The second multiplier 114 multiplies the pilot signals by #, and outputs # semaphores in a side-by-side form. The first plus Fayi 115 adds the j signals of the output of the second multiplication method 114 (none) \/?~to 0 to the #signal S{k\j\ output by the first multiplier 113, respectively. - β, ~ #-7, and output # conjugated form of the composite signal meaning ~ to the inverse fast Fourier transform unit 12, so the β hai special synthesis signal ~ &quot; can be expressed as the following equation (2_2): 2·2) The inverse fast Fourier transform unit 12 outputs the first adder 115

#合合成信号X印)~Do the inverse fast Fourier transform to get the conversion letter I χ(〇)~Χ(Ν-1). The cyclic prefix adding unit 13 adds the converted signal X)) to the cyclic prefix to become an 0FDM symbol x=[;cW W+Lchuan, and transmits the 0FDM symbol through the transmission channel; Transferred to the receiver 2, where 'in particular the length of the cyclic prefix. The j-time synchronization unit 21 estimates the time offset of the received symbol to obtain the starting point of the s-symbol, and uses the principle of the method and the prior art to sell the s. because of the pilot signal generating circuit of the present invention. 112, the characteristics of the pilot letter 14 1336184 are generated, so the time synchronization unit 21 can more accurately determine the time offset, and the detailed judgment manner is as follows. Under the AWGN-affected channel, the signal A/n) received by the time synchronization unit 21 of the receiver 2 can be expressed as Equation (2-3): r(n)=x(n-6)'^e^2Ken&quot; N)+w(n)

= [s(n-9) 4^^+ρ(η-θ) 4JVe(j2lten^N)+w(n) Equation (2-3) where 0 is the magnitude of the time offset and e is the frequency offset The size is the time domain signal of the AWGN noise, the mean (mean) is equal to 0 and the variance is equal to ~2. And as shown in equation (2-4): jlmk

N Equation (2-4) where the average energy a/ of the signals ~ can be expressed as the following equation (2-5): σ/=Ε{|5Υ^|2} Equation (2-5) λ/? &quot; as shown in equation (2-6):

_ \~Ω Ν-ι il7mk

Ρ(η)^ = λ ^ΣΗ^ N Equation (2-6) The transparent auto-correlation function i?(T) of the transparent sequence iY illusion~ corresponding time domain signal 可 can be expressed as follows Equation (2-7): N-1 ^(τ)~ ^hp(m)p*(mod(m + τ,Ν)) Equation (2-7) m=0 _ X r = 0 0, τ ^Ο 15 1336184 Figure 4 shows the relationship between the value of τ and 沢(7) for g 12 , so the periodic autocorrelation function of the time domain signal corresponding to the transparent sequence ΖΥΑτΜϋΟ has perfect characteristics. The statistical property of the time domain signal is a Gaussian program of variability, in the case where the transmitter 1 uses the cyclic prefix, for an OFDM symbol X and &amp; "error", "day {〇乂 7}. Therefore s(n)=s(n+N>l ρ(η卜ρ(η+Ν).

The autocorrelation function of the signal received at the same time as d is:

C Χκι) ρ,ρ,〇, kl = -N,k^[e, θ + Ll] ^~1 = Ν,Ιε[θ, e + L~l] Others _ilz^L_= (1-burning _ (1 -β)σ]+α-pysmX\ defines 5ΝΙΙ=σΛσι/.

The time offset is not obtained by the maximum likelihood function Λ(0) estimated by the time synchronization unit 21, that is, Q = argmax{A(^)} where Λ(0) can be expressed as Λ(θ) = ρΛ卬(8) + (1 — ρ)Λ»

0+Χ—I Λ“θ) = Re{ £]〆〇〇,〇 + Λ〇} η=Θ

Θ+L—X—quaw ΣΚ»)|2+Κ«+λ〇|2 I η^Θ 16 1336184 ΛΦ (θ) shows the contribution of the cycle prefix redundancy to the estimation of time error

Ap(^) = (l + ^)Re{ Υν(η)ρ{η-Θ)} η~Θ 0+1-1 -/? Re{ 2](r(n) + r(n + N) )*p(n - Θ)} Λρ(Θ) indicates the contribution of the information carried by the pilot symbol to the estimation of the time error

The method proposed in the pre-domain technique can also adjust the estimation side. The time offset estimated by the time synchronization unit 21 is not as follows: Q - argmax{p Acp(θ) + (1-ρ)Αρ (θ)} , : two = parameter, its value, one by one, Λςρ(0)= + n=fi Q 〇+L-\ - γ guest kw|2+K«+A〇|2

^p(^) = (! + /?)

Θ+L-X jy(n)p(n-0)

P 0+L~\ Σ(Κη) + r(n + N))*p(n-0) Referring to FIG. 5, FIG. 5 is the condition of the dice 1, SNMdB and material 44 in this embodiment. Diagram of the (9), and gossip time indicators. Compared with the relationship between Fig. 5 + ΛΜ and time index, because of the perfect characteristics of the periodic autocorrelation function of the transparent sequence in the time domain, the relationship between gossip (7) and time index will only be clearly visible in one symbol period. The peak value, and its value is large relative to Λ, 〆". The time synchronization unit 21 uses 17 1336184 appropriate /? This two likelihood functions eight (10), Λ Zheng Ji combined to get _, Λ time index The relationship can be generated - clear and obvious 'and with the time index corresponding to the peak appearing as the time offset, so the SNR is very low, and the situation of misjudgment is not caused as is conventional. Figure 6 is to achieve the above. The embodiment of the circuit block diagram of the time synchronization unit 21, but not limited to this circuit, other circuit design methods capable of performing the above method are also within the scope of the present invention. - The time synchronization unit 21 of FIG. 6 includes The maximum value circuit 211, the f-three multiplier 212, the fourth multiplier 213, a second adder, and a cyclic prefix first time shift synchronization circuit shift synchronization circuit 217. The time offset synchronization circuit 215 generates a contribution from the redundancy estimation of the time error. The sub-header. The time-of-arrival synchronization of the hai hai k abundance synchronization is generated by the carrier of the pilot symbol (time) estimated (four) two third The multiplier 212 shifts the time of the cyclic prefix to the synchronization circuit to the signal source. The fourth multiplier 213 multiplies the output signal by the multi-synchronization circuit 217 by the - coefficient ( / / The multiplication 214 adds the output signal of the third multiplier 212 to the output signal of the fourth ^ 3. The maximum value circuit 2 ιι is used to find the maximum value of the output signal (4) of the second addition 4 to obtain The estimated implementation of the time offset, 7 is the time offset synchronization 215 of the current cycle of the cycle - but not the embodiment. The shift synchronization circuit is used to calculate the Λ (9) seven money ten count ~ (9), and including - taking the conjugator 2151 18 1336184 delay 2152, a first energy device 2156, a second energy device 2157, a first accumulator 2154, a second accumulator 2159, a first absolute value 2155, a first absolute value 2160, two multipliers 2153, 2161 and two adders 2158, 2162 The fetcher 2151 takes the received signal as its conjugate complex number. The delay 2152 delays the received signal by a predetermined time. The multiplier 2153 outputs the output signal of the delay 2152 and the output of the coherent 2151. The signal is multiplied. The first accumulator 2154 accumulates the output signals of the first multiplier 2153 by L time points. The first-take absolute value 2155 takes the output signal of the first accumulator 2154 to an absolute value. 2156, the delay device 2152 is used to perform the energy operation. The second energy device 2157 performs the action of the energy calculation on the received signal. The first adder 2158 outputs the first energy device 2156 output signal and the second energy device 2i57. The signal does the addition. The second accumulator 2159 accumulates the output signal of the first adder 2158 by one time point. The second taking absolute value program performs the action of taking the output signal of the second accumulator 2159 as an absolute value. The second multiplier 2161 multiplies the second absolute value 2160 output (4) by the coefficient _*. The second adder 2162 adds the output signal of the first absolute value 2155 to the output signal of the second multiplier 2161, and outputs the result. Figure 8 is an embodiment of a time offset synchronization circuit 217 that implements the pilot signal, but is not limited to this embodiment. The pilot shift synchronization circuit 217 of the pilot signal is used to calculate the 〆^. In Fig. 8, the 'first-collector' 2171 takes the received signal as its total complex number. The first delayer 2i72 delays the received signal - a predetermined time ❹. The second 19 1336184 takes the coherent device 2173 to take the signal of the first delayer 2172 to its common complex. The second delay H 2174 delays the pilot signal - a predetermined time. The first adder 2175 adds the output signal of the first take-up conjugate 2171 to the output signal of the second take-up conjugate 2173. The first multiplier Μα multiplies the output signal of the first fetcher 2171 and the output signal of the second delay 2174. The second multiplier 2177 multiplies the output signal of the first adder 2175 by the output signal of the second delay 2m. The first-accumulator 2178 accumulates the output signals of the first multiplier 2176 for W time points. The second accumulator 2179 accumulates the output signals of the second multiplier 2177 for a time point. The first take-up absolute value 2 just takes the output signal of the first accumulator 2178 as an absolute value. The second fetch, 'bar counter 218' takes the action of taking the output signal of the second accumulator 2179 to an absolute value. The third multiplier 2182 multiplies the output signal of the first-pass absolute value 218〇 by the coefficient /+p. The fourth multiplication _ 2183 multiplies the output signal of the second absolute value 2181 by the coefficient _p. The second adder 2184 adds the output signal of the third multiplier 2182 and the output signal of the fourth multiplier 2183, and outputs the result. Regression refers to Figure 3, in addition, because the transmission channel is not ideal and the relative velocity between the transmitter 1 and the receiver 2 is caused by the Doppler effect or the operating clock (not shown). The error, the frequency of the signal received by the receiver 2 / the frequency of the output signal of the transmitter 1 (the frequency offset e = 7 between y / is generated, so the frequency synchronization unit 22 calculates the magnitude of this frequency offset. It is noted that since the time synchronization unit 21 of the present invention can accurately detect the correct symbol starting point, especially when the SNR is low, the frequency synchronization unit 22 can use the frequency error. The estimated redundant information is sufficient to further improve the accuracy of the estimation and improve the lack of sensitivity to frequency errors in the 〇FDM system.

The frequency synchronization unit 22 receives the time offset 0 estimated by the time synchronization unit 21 and uses PH M〇ose in a paper published in the journal "mEE Trans. Commun." in 1994 "A Technique plus nh〇g 〇nai

Frequency Division Multiplexing Frequency Offset Correction, "The disclosed equation calculates the magnitude of the frequency offset ^ and substitutes α Υ&quot; of equation (2-3) to calculate the magnitude of the frequency offset ε: ε 2π tan' + Ν)] η^ θ__J乞9ψ*· («&gt;(« + #)] where '[[]] means the real part, 3[·] means the imaginary part, the length. Equation (2-8) is the end of the loop An embodiment of the frequency synchronization unit 22 is implemented, but is not limited to this embodiment. The frequency synchronization unit 22 includes a fetching unit 221, a delay unit 222, an accumulator 223, and an angle finder 224. And two multipliers 225, 226. The fetching conjugate 221 takes the signal transmitted by the time synchronizing unit 21 into a conjugate complex. The delay 222 delays the signal transmitted by the time synchronizing unit 21 by a predetermined time. The first multiplier 225 multiplies the output signal of the fetcher 221 and the delay H 222. The accumulator 223 accumulates the output signal of the first multiplier 225 for several time points. The rim production station of the accumulator 223 ~ a takes the angle 224 of the wheel magic = angle. The second multiplication 226 will be worth noting that the above 杳-/, the mountain is in the first reading of the example 'Although the pilot signal is used to generate the circuit m with transparent timing of the shape 1 ** 4» "But actually, The pilot signal _ can be used as the pilot signal for other sequences, as long as the period auto-correlation function of the sequence--domain 仏 has a perfect period from the /-off function to have a distinguishable peak. In the conventional service system, the pilot signal occupies the bandwidth of the subcarrier, and the present invention superimposes the pilot signal on the signal converted from the bit stream to become a composite signal, so that the pilot signal does not occupy the subsystem of the system. The bandwidth of the wave, thus improving the bandwidth usage efficiency of the system. Older, because of the characteristics of the periodic autocorrelation function of the pilot signal used, the period of the signal received by the receiver 2 during the - symbol period The autocorrelation function will only have a maximum value or a clearly distinguishable peak value, so the starting point signal of the _Μ symbol can be synchronized correctly, even more, because the correct judgment is made. The starting point signal, so the frequency can also be relatively synchronized. The above is only the preferred embodiment of the present invention, and the scope of the present invention cannot be limited thereto, that is, the scope of patent application according to the present invention And the simple equivalent changes and modifications made by the description of the invention are still within the scope of the invention. [Fig. 1 is a circuit block diagram of a conventional OFDM system; 22 1336184 FIG. 3 is a circuit block diagram of an embodiment of an OFDM system of the present invention: and FIG. 4 is an OFDM system of the present invention. FIG. 3 is a circuit block diagram of an embodiment of the OFDM system of the present invention. FIG. Periodic autocorrelation function of the transparent sequence output by the pilot signal generating unit

5 is a diagram of a relationship between an eight-input (9)), an eight-in-one, and a go-in time index calculated by the OFDM system of the present invention; FIG. 6 is a circuit block of an embodiment of a time synchronization unit of the receiver of the present invention; Figure 1 is a circuit block diagram of one embodiment of a circuit; Figure 8 is a circuit block diagram of one embodiment of a time + circuit of a pilot signal of the time synchronization unit; and Figure 9 is a connection (4) of the present invention.

Circuit block diagram. The doorstep is early...Example 23 1336184

[Description of main component symbols] 1 ........ Transmitter 2152 ...··Delayer 11........• Modulation unit 2153 ••...Multiplier 111·.&quot; - Modulation circuit 2154 .... • The first accumulator 112 ·····. The pilot signal generates electricity 2155 * a * u * one takes the absolute road device 113 ..... •• first multiplier 2156 ..... first energy device 114 · ·.. •• second multiplier 2157 ...·· Second energy device 115°··*· •-First adder 2158 ...·.Adder 12..••Anti-fast Fourier turn 2159 ••...Second accumulator change unit 2160 ... .. second take absolute 13.. • • cycle prefix first into single unit 2161 •... multiplier 2 · receiver 2162 ..... adder 21....... • Time Synchronization Unit 2171 .....% Take a common 211 .... · Take the maximum value 2172 ... · First delay 212 ... ·. · Multiplier 2173 .... Yoke 213 ... •• Multiplier 2174 ····. Second retarder 214 ···· • Adder 2175 ..... Adder 215 .'... •• When the word is first 2176 ••... Multiplier offset synchronization circuit 2177 ...··multiplier 217 ••... •• pilot signal timing 2178 •....first accumulator inter-set offset synchronization circuit 2179 ...··second accumulator 2151 ... •• Consumable 2180 ••...first absolute value 24 1336184 2181 ·...second absolute value 222·°,*° •• retarder 2182 · ...multiplier 223 ..... •• accumulator 2183 ...multiplier 224 * * * * •• Angler 2184 · ...Adder 225 Multiplier 221 ··· Take the Common Roller 226 Multiplier

25

Claims (1)

X. The scope of application for patents: 1. The type of orthogonal frequency division multi-channel that achieves synchronization by pilot ki and m-word, including: 'a transmitter, including: a modulation circuit' is connected to one bit stream, and Transforming the bit stream into a set of modulated signals; a pilot signal generating circuit generating a set of pilot signals having the same number as the modulated signal, and the periodic autocorrelation function of the set of pilot signals has a distinguishable peak; An adder 'superimposes the set of modulated signals with the set of pilot signals to generate a set of composite signals; an inverse fast Fourier transform unit 'receives the combined into signals' and converts into a set of converted signals; and a cyclic prefix is added to the unit And a part of the signal of the set of converted signals is added to the prefix of the set of converted signals to form a symbol to be sent: and a receiver, comprising: a time synchronization unit, based on the periodic autocorrelation function of the pilot signal The peak value is differentiated, and the time offset of the received symbol is estimated to obtain the starting point of each symbol. 2. The orthogonal frequency division multiplexing system in which the pilot signal and the cyclic prefix are synchronized according to the first aspect of the patent application scope, wherein the pilot signal generated by the pilot signal generating circuit is a transparent sequence signal. 3. According to the scope of claim 1 of the patent application, the pilot signal and the cyclic prefix 26 1336184 reach a synchronous orthogonal frequency division multiplexing system, wherein the pilot signal generating circuit generates a periodic autocorrelation function of the pilot signals generated by the pilot signal generating circuit. Only one peak will appear in a symbol interval. 4. The orthogonal frequency division multiplexing system in which the pilot signal and the cyclic prefix are synchronized according to item 3 of the patent application scope, wherein the pilot signal generating circuit generates the period autocorrelation function of the group of pilot signals The peak occurs where the index value is zero and is zero at other index values. 5. The orthogonal frequency division multiplexing system in which the pilot signal and the cyclic prefix are synchronized according to the scope of the patent application scope, wherein the transmitter further comprises a first multiplier and a second multiplier, The first multiplier first multiplies the set of modulation apostrophes by a first proportional parameter and then sends the same to the adder, and the second multiplier multiplies the set of pilot signals by a second proportional parameter and then sends the same to the adder. And the sum of the squares of the first and second proportional parameters is equal to 1 〇 6. According to the scope of claim 1 of the scope of the invention, the pilot-divided signal and the cyclic prefix reach the synchronization of the orthogonal frequency division multiplexing system 'where the receiving The machine further includes a frequency synchronization unit that estimates the frequency offset for the symbol that has obtained the time offset estimate. 7. The orthogonal frequency division multiplexing system in which the pilot signal and the cyclic prefix are synchronized according to item 6 of the claim patent scope, wherein the frequency synchronization unit comprises: a fetching unit is to be used by the time synchronization unit The transmitted signal takes a conjugate complex; a delayer delays the signal transmitted by the time synchronization unit by a predetermined time; a first multiplier multiplies the fetcher and the number: an output of the delay The accumulator, the first multiplication point; the rounding signal of the estimator is accumulated when the angle is taken, the angle of the output signal of the accumulator is taken; and the second multiplier is used to output the angle finder. The chirp is multiplied by a factor of 8 to estimate the frequency offset. According to Shen Qing's patent scope, the 户 户 ^ ^ ^ ^ 达到 7 舭 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 唬 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交 正交The first time offset synchronization circuit generates a contribution from the first error of the cyclic word to the time error estimate; the time offset synchronization circuit of the signal = generates a contribution of the information carried by the pilot symbol to the time error estimate; - the first-multiplier 'multiplies the time-shifted signal of the cycle prefix' by the coefficient - the first multiplier of the 〆玉硌, multiplies the time-shifting synchronization circuit of the pilot signal by the multiplier-coefficient (1-P a normalizer adds the output signal of the first multiplier to the output signal of the second multiplier; and 5: a value circuit, the output signal of the first adder is searched for its maximum value to obtain a time offset Estimate. 9 · According to the scope of application for patents 笫 8 brothers 8 as the pilot signal and the cycle prefix 28 1336184 to achieve synchronous orthogonal frequency division multiplexing system, where μ偬狡m falls into the first time shift The synchronizing circuit comprises: ~ taking a conjugator, taking the received signal to its conjugate complex number; ~ delaying the delay of the received signal by a predetermined time. H-stator's the output of the delay of the delay Multiply out the signal; /, yoke ~ first accumulator, the first multiplier is also I-column J-collar k-additive add# The time point '\ is the length of the cycle prefix; ~ the first - take the absolute value, the absolute value of the first accumulator; the mountain L is taken ~ the first energy device, the delay output signal is used for energy calculation; a second energy device that performs an action of receiving a signal as an energy operation; a first adder, an action of adding the first energy device output signal to the output signal of the second moon battery; - a second accumulation , accumulating the output signal of the first adder by # time points, \ is the length of the cycle prefix; g ― the second taking the absolute value, and taking the output signal of the second accumulator as an absolute value; 1 , a second multiplier, multiplying the second absolute output signal by a coefficient - £; and 2 = - a second adder, the output signal of the first absolute value and the first multiplier The output signal is added, and the result is rounded out. According to the scope of claim 8th, the pilot signal and the cycle prefix 29 1336184 reach the synchronous orthogonal frequency division multiplexing system. The time offset synchronization circuit of the pilot signal includes: a first - taking a conjugate, taking the received signal as its conjugate complex number, the first delay, delaying the received signal - predetermined time #; a second taking the conjugate, taking the first delay to take the signal Conjugating a plurality of conjugates; a second delayer delaying the pilot signal by a predetermined time. - a first adder that adds the output signal of the first fetcher and the output signal of the second co-clamp Action: - a multiplier that multiplies the rounded signal of the first take-up lighter with the output signal of the second delay; - the second multiplier 'rounds the first adder The action of multiplying the signal by the output signal of the second delay; - the first accumulator 'accumulates the round-out signal of the first multiplier by iV + a time point; the summation of the signal - the second accumulator The second multiplier is input at a time point; the rounding signal of the adder is a first absolute value, the first absolute value is taken; the second second absolute is used to accumulate the second The round-out signal of the device takes the action of taking the absolute value; - the second multiplier, the first The absolute value is "wheel signal by multiplying the factor 1 + / 7; - a fourth multiplier 'is the absolute value of the second output signals are multiplied 301336184 J The upper coefficient -/&gt;; and the _ second adder add the output signal of the third multiplier to the output signal of the fourth multiplier, and output the result. 31