1335793 九、發明說明： 【發明所屬之技術領域】 本發明有關一種降低時脈訊號電磁干擾方法，尤其是 關於1C半導體晶片中降低時脈訊號所產生電磁干擾的方 法。 【先前技術】 隨著數位科技的發達，數位系統為了能夠支援高密度 及高速度的資訊傳輸，需要一可靠及精確的時脈產生器以 產生高頻的時脈訊號，作為資料訊號傳輸速率的參考°。典 型系統計時時脈的產生與分配，係由一系列功能元件所組 成，這一系列功能元件可為元件晶片組或獨立封裝高度整 合兀件等1C半導體晶片，而該等IC半導體晶片對於電.磁 分敏感。1335793 IX. Description of the Invention: [Technical Field] The present invention relates to a method for reducing electromagnetic interference of a clock signal, and more particularly to a method for reducing electromagnetic interference generated by a clock signal in a 1C semiconductor wafer. [Prior Art] With the development of digital technology, in order to support high-density and high-speed information transmission, digital systems require a reliable and accurate clock generator to generate high-frequency clock signals as data signal transmission rate. Reference °. The generation and distribution of typical system timing clocks consists of a series of functional components, which can be 1C semiconductor wafers such as component chipsets or individually packaged highly integrated components, and such IC semiconductor wafers for electricity. Magnetic sensitive.
上，仍有問題亟待解決。 干擾（Electrical Magnetic Interference,簡稱 EMI)十 :僅降二低 5 1335793 【發明内容】 本發明之一目的在提供一種降低時脈訊號電磁干擾方 法，藉由將時脈訊號函數轉換為單位函數，降低時脈所產 生的能量，以減少電磁干擾。 本發明另一目的在提供一種降低時脈訊號電磁干擾方 法’利用至少一單位函數之運算產生一個有效的頻率，以 提供適當的時脈訊號。 本發明再一目的在提供一種降低時脈訊號電磁干擾方 法’利用邏輯運算方式產生低能量的時脈訊號，降低電磁 干擾及產品成本。 為了達到前述發明的目的，本發明之降低時脈訊號電 磁干擾方法，首先由一時脈產生器產生一時脈訊號，擷取 時脈訊號’形成一時脈函數，再將時脈函數進行拉氏轉換 成單位。函數，接著以至少一單位函數之運算，形成有效時脈 訊號，隶後輪出有效時脈訊號，作為數位系統傳輸資料訊號的計 時參考。 ' 【實施方式]On, there are still problems to be solved. Interference (Electrical Magnetic Interference, EMI) 10: only lowers 2 low 5 1335793 SUMMARY OF THE INVENTION One object of the present invention is to provide a method for reducing electromagnetic interference of a clock signal, which is reduced by converting a clock signal function into a unit function. The energy generated by the clock to reduce electromagnetic interference. Another object of the present invention is to provide a method for reducing the electromagnetic interference of a clock signal by using at least one unit function to generate an effective frequency to provide an appropriate clock signal. Still another object of the present invention is to provide a method for reducing the electromagnetic interference of a clock signal by using a logic operation to generate a low-energy clock signal, thereby reducing electromagnetic interference and product cost. In order to achieve the object of the foregoing invention, the method for reducing the electromagnetic interference of the clock signal of the present invention firstly generates a clock signal by a clock generator, extracts a clock signal to form a clock function, and then converts the clock function into a Lagrangian. unit. The function then performs an operation of at least one unit function to form an effective clock signal, and then rotates the effective clock signal to serve as a timing reference for the digital system to transmit the data signal. 'Embodiment'
有關本發明為達成上述目的，所採用之技術手段及I 功效丄茲舉較佳實施例，並配合圖式加以說明如下。 ，參考圖丨，為一時脈產生器所產生脈衝的時脈訊號 該k脈訊號的能量較大，如未加處理，將對數位系統内存 產生電磁干擾。為降低時脈訊號的能量，處理時脈言 號時，首先將時脈訊號形成一時脈函數，並定義該時历 函數δ (t)為： " 〇〇 ⑴ <5 (ϊ)ξ Φ 6 1335793 其中，t為時間。 再將前述（1)式之時脈函數5 (t)，利用拉氏轉換 (Laplace Transform)進行轉換，轉換的運算如下：The present invention has been made in accordance with the preferred embodiments of the present invention in order to achieve the above object, and is described below with reference to the drawings. Referring to the figure 丨, the pulse signal of the pulse generated by the clock generator is large. If the signal is not processed, electromagnetic interference will be generated to the digital system memory. In order to reduce the energy of the clock signal, when processing the clock signal, the clock signal is first formed into a clock function, and the time history function δ (t) is defined as: " 〇〇(1) <5 (ϊ)ξ Φ 6 1335793 where t is time. Then, the clock function 5 (t) of the above formula (1) is converted by Laplace Transform, and the conversion operation is as follows:
Q ε lim —厂 {w ⑺一w(i — 〇}汾 g Jo lim — {L{u(f)} - L{u(t- ^)}} ε lim £->0 ———Qs s c 1 v l-e~s 0 —lim-λ — S ㈠Q ε 0 lim se S 1 ⑵ 其中，S為S域（domain)函數； ε為很小的時間； u(t)為單位函數。 由（2)式的轉換，將時脈函數<5 (t)轉換為一單位函數 u(t)，並定義單位函數u(t)為： ， 1 t = 0 u(t)三-< (3) ^ 0 t 关 0 其中* t為時間。 如圖2所示，時脈函數0(t)即可轉換為單位函數u(t)。 7 能以相對對=單位函數u(t)，讓時脈訊號脈衝 擾的能量，降至最伋u( i ,度產生，使時脈訊號產生電磁干 至最低，達到減少電磁干擾的目的。 單位函數的運算各g脈^需之形態，可由广咬多個的 示，顯示由；單: 函數作為時脈訊號。如圖3所 一個函數之差所形成時脈訊號，其中單位函數 ♦1)及赌祕u(t_2)齡 由數 (4) u(t-l) Ξ <Q ε lim —厂{w (7)一w(i — 〇}汾g Jo lim — {L{u(f)} - L{u(t- ^)}} ε lim £->0 ———Qs Sc 1 v le~s 0 —lim-λ — S (1)Q ε 0 lim se S 1 (2) where S is the S domain function; ε is a small time; u(t) is a unit function. Transformation of the equation, converting the clock function <5 (t) into a unit function u(t), and defining the unit function u(t) as: , 1 t = 0 u(t) three-< (3) ^ 0 tOff 0 where * t is time. As shown in Figure 2, the clock function 0(t) can be converted to the unit function u(t). 7 can be relative = unit function u(t), let The energy of the pulse signal of the clock signal is reduced to the lowest (u (i, the degree is generated, so that the electromagnetic signal is generated to the lowest of the pulse signal to achieve the purpose of reducing electromagnetic interference. The unit function is calculated in the form of each g pulse. The bite of multiple shows, the display by; single: function as the clock signal. The difference between the function shown in Figure 3 is the clock signal, where the unit function ♦1) and the gambling secret u(t_2) age is counted (4) u(tl) Ξ <
(5) u(t-2) s ^(5) u(t-2) s ^
一中，t為時間。由式（4)單位函數u(t-l)減式（5)單 位函數u(卜2)，即可經由簡單的運算產生式（3)的單位 u(t)，以作為時脈訊號。 數 如圖4所示’為本發明降低時脈訊號電磁干擾方法之 作業流輕’該流程具體顯示本發明降低時脈訊號電磁 之步驟’詳細步驟說明如下： 步驟S1 :由一時脈產生器產生時脈訊號，作為數位系 統傳輸資料訊號的計時參考。 ’、 步驟S2 :擷取時脈產生器所產生之時脈訊號，形成— 時脈函數。 步驟S3 :將時脈函數6(t)進行拉氏轉換運算。 步驟S4:時脈函數5(t)進行拉氏轉換後，形成單位函數^ 8 上W93 步驟S5 :由至少一單位函數，形成有效的單位函數，伟生 時脈訊號。 … 步驟S6 :將有效的時脈訊^輸出’作為數位系統資料訊辦 傳輪之計時參考。 化In one, t is time. By subtracting the unit function u(t-l) of the equation (4) by the unit function u(b 2), the unit u(t) of the equation (3) can be generated as a clock signal by a simple operation. The number shown in FIG. 4 is 'the operation flow of the method for reducing the electromagnetic interference of the clock signal of the present invention. The flow specifically shows the step of reducing the electromagnetic signal of the clock signal of the present invention. The detailed steps are as follows: Step S1: generated by a clock generator The clock signal is used as a timing reference for the digital system to transmit data signals. Step S2: Capture the clock signal generated by the clock generator to form a clock function. Step S3: Perform a Lagrangian conversion operation on the clock function 6(t). Step S4: After the Lagrangian transformation of the clock function 5(t), a unit function ^8 is formed on W93. Step S5: Forming a valid unit function by at least one unit function, the Weisheng clock signal. ... Step S6: Use the valid clock signal output as the timing reference for the digital system data transmission. Chemical
由前述的步驟，本發明降低時脈訊號電磁干擾方法， 即可藉由將時脈訊號之函數轉換為單位函數，同時利用至 少一組之單位函數之簡單運算產生一個合適的單位函數頻 率’作為時脈訊號頻率，使時脈所產生的能量降低，以減 少電磁干擾。此外，本發明之降低時脈訊號電磁干擾方法， 係以函數的轉換及邏輯運算方式產生低能量的時脈訊號， 可以軔體方式完成’無需額外增加線路及零件，除可降低 電磁干擾’亦可降低產品的製造成本。 以上=述者，僅用以方便說明本發明之較佳實施例， 本發明之範圍不限於該等較佳實施例，凡依本發明所做的 任何變更，於不脫離本發明之精神下，皆屬本發明申專 利之範圍。 1335793 【圖式簡單說明】 圖1為一時脈產生器所產生脈衝的時脈訊號。 圖2為本發明將時脈函數轉換為單位函數訊號。 圖3為本發明由二組單位函數之差所形成時脈訊號。 圖4為本發明降低時脈訊號電磁干擾方法之流程圖。 【主要元件符號說明】 S1產生時脈訊號步驟 S2擷取時脈訊號步驟 S3拉氏轉換運算步驟 S4轉換單位函數步驟 S5形成有效時脈訊號步驟 S6輸出時脈訊號步驟By the foregoing steps, the present invention reduces the clock signal electromagnetic interference method by generating a suitable unit function frequency by converting a function of the clock signal into a unit function while using a simple operation of at least one unit function. The frequency of the clock signal reduces the energy generated by the clock to reduce electromagnetic interference. In addition, the method for reducing electromagnetic interference of the clock signal of the present invention generates a low-energy clock signal by means of function conversion and logic operation, and can be completed in a body-like manner [without additional lines and components, in addition to reducing electromagnetic interference] It can reduce the manufacturing cost of the product. The above is a description of the preferred embodiments of the present invention, and the scope of the present invention is not limited to the preferred embodiments, and any changes made in accordance with the present invention may be made without departing from the spirit of the present invention. All of them are within the scope of the patent application of the present invention. 1335793 [Simple description of the diagram] Figure 1 shows the pulse signal of the pulse generated by a clock generator. 2 is a diagram of the present invention for converting a clock function into a unit function signal. 3 is a clock signal formed by the difference between two sets of unit functions in the present invention. 4 is a flow chart of a method for reducing electromagnetic interference of a clock signal according to the present invention. [Main component symbol description] S1 generates clock signal step S2 captures clock signal step S3 Laplace conversion operation step S4 converts unit function step S5 forms effective clock signal step S6 outputs clock signal step