1334072 determine the charge time of the voltage source to shift the voltage of the control node of the first transistor pair. · 七、 指定代表圖： (一) 本案指定代表圖為：第（5 )圖。 . (二) 本代表圖之元件符號簡單說明： 500 電壓調整電路 501、503 電壓提升單元 502、504 控制電路 510 交錯耦合式拴鎖電路1334072 determines the charge time of the voltage source to shift the voltage of the control node of the first transistor pair. VII. Designated representative map: (1) The representative representative map of the case is: (5). (2) A brief description of the component symbols of this representative diagram: 500 voltage adjustment circuit 501, 503 voltage boosting unit 502, 504 control circuit 510 interleaved coupling shackle circuit
51卜 512 PMOS 513 > 514 NMOS 540 反向器鏈 八、 本案若有化學式時，請揭示最能顯示發明特徵的化學 式： (無） 九、發明說明： 【發明所屬之技術領域】 本發明側於-種電壓難電路以及其控制方法，特別是 指一種具有預充功能，使得交錯齡式栓鎖電路（咖 1滅）能有更㈣反應時間將輸出電壓調整至所需電位的 電壓調整電路以及其控制方法。 · 【先前技術】 1334072 電路系統中，針對不同的需求會有不同的電壓源，例如後 ，電路需·^載而需要大功率的電源科，對於積體電路 曰曰片（1C)而s，則必須針對不同電壓準位的訊號做電壓轉換， 在習知技術巾it f是岐錯齡錄鎖電路（_s_coupl、ed 1号tch)來達到調整電壓準位的效果。 °月 > 考第1圖，第1圖為習知技術交錯搞合式拾鎖電路1〇〇 之電5^® ’其包含有兩個連接方式互相對稱的電晶體對ι〇ι與 」 102 ’每一電晶體對皆包含有一P型金氧半電晶體（PMOS)以 及一_金氧半電晶體（應〇^)，其中PMOS係與NM〇s串聯， 亦即PMOS與NMOS的汲極耦合以形成一輸出端，每一電晶體 對中PMOS的閘極（gate)為該電晶體對中的控制節點，每一電 晶體對中的控制節點皆耦合至另一電曰曰曰體對之輸出端。以第1 圖所示之交錯耦合式拴鎖電路100為例’電晶體對1〇1包含有 PMOS110 ’其源極耦合至一高電壓源vqdh，汲極則與 NMOS130的汲極耦合形成節點103，NM〇S13〇的源極則輕合至 地’·電晶體對102包含有PMOS120，其源極耦合至一高電壓源 ) VDDH ’汲極則與NMOS140的汲極耦合形成節點1〇4， NMOS140的源極則耦合至地。其中pMOS110的閘極為電晶體 對101的控制節點’耦合至節點104形成交錯耦合式拴鎖電路10〇 的電壓輸出端，而PMOS120的閘極為電晶體對1〇2的控制節 點，耦合至節點103 ’交錯耦合式拴鎖電路1〇〇另包含有一反相 器150 ’輸入電壓Vin耦合至NMOS130的閘極，另一方面經由反 相器150反向後耦合至NMOS140的閘極。 反相器150的操作電壓與輸入電壓Vin準位皆為VDD，當輸 5 入電壓Vin為VDD時NMOS130會導通（tum on)而NMOS140 不導通（turnoff) ’所以節點103電壓為〇使得!^^^導通， 將節點104的輪出電MVout提升到較高的電壓值，因此 PMOS110不導通’郎點103電屋仍維持在〇 ^當輸入電壓γ|η為〇 時NMOS130不導通而NMOS140導通’節點1〇4的輸出電壓v^ut 會被降到0V ’因此PMOS110導通，節點103電壓值被提升到 VDDH使得PMOS120不導通，輸出電壓乂_維持〇¥。 然而，由於PMOS110、PMOS120的閘極電壓取決於 NMOS130、NMOS140導通與否’亦即考慮暫態時，丽〇313〇、 NMOS140必須在PMOS110、PMOS120之前動作，因此在設計 時NMOS130、NMOS140的寬長比（aSpectrati0)必須較大以使 得其與PMOS110、PMOS120相比之下較有主控性（str〇nger)， 如此一來，交錯耦合式拴鎖電路1〇〇才能正常工作。不過，這同 時也造成輸出電壓Vout在由0V提升至VDDH的上升時間（rising time)與從VDDH下降至0V的下降時間（faUing time)並不相 等’也就是說輸出電Μ對比於輸入電壓會有一定量的失真，若 輸入電壓為一脈衝寬度調變（PWM)訊號，在考慮製程誤差的 情況下此失真會更加嚴重。另外，雖然輸出電壓v〇m會隨著輸 入電壓Vin的電壓準位改變而改變，然而在轉換時因為？1^〇§的 主控性比較弱（weaker)，節點靠PMOS提升電壓的速度會比 NMOS導通的速度慢’因此會發生同一電晶體對的_〇8尚未 完全不導通時NMOS即已導通的情形’造成在輸入電壓vin的電 壓準位改變時會有大電流流經電晶體對而形成功率損耗。 請參考第2圖，第2圖為另一習知技術交錯耦合式拴鎖電路 1334072 二之電路圖，其所含元件與第1圖之交錯耦合式拴鎖電路綱 =，/、功用也相似’只有部份元件其連接方式不同，熟知技 關係參考上述交雜合紐鎖電路_說明即 I輕易付知其制與第1Θ之交_合式拾鎖電路刪相同，同 時也具有相同的缺點’在此不再贅述。 【發明内容】 、發明之主要目的’即在於提供-種具有預充功能 的=調正電路及其控制方法，使得其輸出電壓驗速的達到 所萬之電位’且其上升時間（nsingtime)及下降時間（臟^ time)不致失真太嚴重，以解決上述問題。 』根據本判-實酬’其係揭露—種具有預充功能的電壓 調整電路，其包含有-交錯搞合式拾鎖電路（cross·# latch) ’其具有連接方式互相對稱之一第一、第二電晶體對，每 -電晶體對皆接收該輸人電壓^每—電晶體對之一輸出端皆互 她合至另-電晶體對之-控制節點，其中該第二電晶體對之 輸出端電壓即為該輸出電壓，·—電壓提升單元，麵合至一電源 與該第-電晶體對之該控制節點，絲提升該洲節點之電 壓’·以及-控織路，搞合至該龍提料元與錄入電壓， 可制該輸入賴之變化以提供一脈衝（pulse)，該脈衝可控 繼電·升單元以決定該電源難第—電㈣狀該控制節 點之充電時間。 根據本發明另-實施例’其係、揭露—種調整電壓的控制方 法’用來將-輸入電壓轉換至具有較高電壓值之一輸出電壓， 7 1334072 其包含有提供連财式互姆稱之—第—、第二電晶體對，每 =電晶體對皆接收該輸人電社每—電晶體對之—輸出端皆互 ^輕合至另-電晶體對之一控制節點，其中該第二電晶體對之 輸出端電壓即驗翻龍；侧該輸人輯之變化以提供一 第-脈衝；以及根據該第—脈衝來控制—電源對該第一電晶體 對之該控制節點之充電時間。 【實施方式】 、由上所述’ S知技術的缺點在於當—電晶體對中的丽⑽ 不導通時，其輸出電壓賴由該電晶體射㈣聰來往 VDDH提升’ _PMQS在騎地弱（weakef)(亦即寬長比 (aspectrati0)較小，電流流通能力較弱）；而在顧沉導通時， 該PM0S的控制節點（即PM0S的閘極）電壓必須由另一電晶體 對中同樣較弱的PM0S將該控制節點的電壓提升後才能將該 PM0S關閉，此二現象導致輸出電壓v〇m不論從_师〇賊 疋由VDDH到0V都f要-段轉換時間，而這段轉換時間並不對 稱而造成電壓訊號失真，而且會造成功率招拉 ） 於是本發蒙-麵織==舰，树 輸入電壓Vin改變時預先將控制節點《電，使得輸出電壓⑽ 的改變更快以及上升時間與下降時間更加對稱以減少失真及功 率損耗。 首先睛參考第3®’第3圖為本發g种電壓提料元3〇1與控 制電路302之電路圖’在本實施例中，電壓提升單元3〇1為一源 極麵合至高電屋源VDDH的1>型金氧半電晶體（pM〇s) 31〇， 8 1334072 但是也可以用其他不同的電路來實施’ PMOS310的汲極可搞合 至前述習知技術中所提到的交錯耦合式拾鎖電路1〇〇、2〇〇中的 控制節點，當PMOS310導通時，便可以將控制節點的電壓往 VDDH提升，加速控制節點的電壓到達預定的電壓值，而當 PMOS310不導通時，則可視為與交錯耦合式拴鎖電路1〇〇、2〇〇 間斷路。PMOS310導通與否係由控制電路3〇2來控制，控制電 路302包含有一PMOS320、兩NMOS330與340、一延遲單元350 以及一反向器360。PMOS320耦合至高電壓源VDDH，由於其 閘極接地’故PMOS320可視為一電阻；一互相串聯並分別耗合 至PMOS320與地之間的NMOS330與NMOS340，其作用類似於 一反及閘（NAND gate )，當此二NMOS的閘極（亦即NAND gate 的二輸入端）電壓為電壓準位”1”時（亦即電壓VDD )nm〇S33〇 與NMOS340會導通，於是NMOS330與PMOS320的耦合接點p 電壓為0，該耦合接點P電壓即為PMOS310的閘極電壓，因此使 得PMOS310導通。輸入電壓Vin經由延遲單元350延遲一預定時 間後輸入NMOS330的閘極，同時輸入電壓Vin亦經由反向器360 3 反向後輸入NMOS340的閘極’如第4圖所示，當輸入電壓yjn 由電壓準位”1”改變至電壓準位”0”時，在該預定時間内 NMOS330與NMOS340的閘極電壓皆為VDD，導致PMOS310的 閘極電壓為一脈衝，其脈衝寬度可由延遲單元350來控制，在該 脈衝寬度時間内PMOS310導通，將交錯輕合式栓鎖電路1〇〇、 200中的控制節點的電壓往VDDH提升’加速控制節點的電壓到 達預定的電壓值，由此可知，當輸入電壓Vin沒有發生改變時柄 合接點P電壓為VDDH，PMOS310不導通。 9 1334072 *月參考第5圖’第5圖為本發明電壓調整電路5〇〇第一實施例 的電路圖’電壓調整電路5〇〇包含有一交錯輕合式拾鎖電路 510。、兩電壓提升單元5〇1與5〇3、兩控制電路5〇2與5〇4以及一反 f器鏈540。其中交錯耦合式拴鎖電路510的結構與運作原理與 前述之交錯耦合式拴鎖電路100相同，而電壓提升單元5〇1與5〇3 的結構與運作原理與前述之電壓提升單元301相同，控制電路 502與504的結構與運作原理則與前述之控制電路3〇2相同，反向 器鏈540則作為反向功能與延遲功能，現詳述其工作原理如下。 當輸入電壓Vm為電壓準位”Γ，（即vdd)時，節點b、d電壓皆 為VDD ’郎點a、c電壓則為〇，因此節點e、f電壓為vj)dh，電 壓k升單元501與503皆不導通，節點b電壓為VDD使得 NMOS513導通，控制節點g電壓為〇，使得導通，另 外因為節點c電壓為0使得NM〇S514不導通，因此輸出電壓v〇ut 為VDDH，PMOS511不導通。當輸入電壓Vin由電壓準位”丨，，改 變至電壓準位0”（即電壓〇)時，節點a電壓由〇變至Vdd ,但 節點d此時尚未改變（因為節點a至節點d間相隔三個反向器，因 此造成一延遲時間）’電壓值仍是VDD，因此節點e電壓迅速被 拉至0導至電壓提升單元501導通，因此節點g的電壓被高電源 VDDH預充，其預充時間可藉由反向器鏈54〇的反向器數目來調 整，節點b電壓變為0後NMOS513不導通，控制節點g的電壓值 藉由預充迅速提升至VDDH，使得PMOS512不導通，當節點0 電壓變為1時NMOS514導通，輸出電壓Vol^〇，pm〇S51^ 通’最後節點d電壓變至0，節點e電壓恢復至vqdjj，預充過程 結束，整個電壓調整電路500恢復穩態操作。另一方面，當輸入 1334072 電壓Vin由電壓準位”0”改變至電壓準位”ι”（即電壓^1)〇)時， 節點c此時尚未改變（因為輸入電壓端至節點相隔三個反向 器，因此造成一延遲時間），電壓值仍是VDD，因此節點f電壓 迅速被拉至〇導至電壓提升單元5〇3導通，因此輸出電壓v〇ut被 向電源VDDH預充’其預充時間可藉由反向器鏈54〇的反向器數 目來調整，輸出電壓Vout可藉由預充迅速提升至vddh,當節 點c電壓變為0後NMOS514不導通，輸出電壓v〇ut固定為 」 ’節點f電壓恢復至VDDH ’預充過程結束，整個電壓調 整電路500恢復穩態操作。 請參考第6圖，第6圖為本發明電壓調整電路6〇〇第二實施例 的電路圖，其與弟5圖之電壓調整電路5〇〇的不同處在於將電壓 調整電路500中的交錯耦合式拴鎖電路51〇替換成類似前述之交 錯耦合式拴鎖電路200的結構，當輸入電壓Vin為電壓準位”Γ， (即VDD)時，節點b電壓為vdD，舰〇;5613不導通，節點c 電壓為0 ’ NMOS614導通，導致PM〇S612導通，輸出電壓v〇m 為。當輸入電壓Vin由電壓準位”1”改變至電壓準位，，〇” J (即電壓〇)時’控制電路6似使得電壓提升單元601將控制節點 g的電壓值預充至VDDH，PMOS612不導通，此時因為節點_ 電壓變為0;蘭(顺3導通，所以輸出電壓被拉至〇。當輸入電 壓Vin由電壓準位”〇”改變至電壓準位”丨，，（即時， ,〇S613不導通而顺〇观4導通，控制電路6〇4使得電麼提升 單元603將輸出電壓v〇ut預充至。 凊參考第7®，第7圖為本發明電細整電路第三實施例 的電路圖’其中的交錯搞合式拾鎖電路為前述之交錯輕合式拾 11 =路觸與2_齡使用，其雜絲作顧與交錯麵合式 —，】路10G、2GG完全相同’因此電壓調整與前述之第 ^1^二實施觸魏與操作顧亦她，習知技藝者可輕易 推論件之，在此不予贅述。 請參考第8圖’第8圖為本發明龍提升單與控制電路 之^關’ f赌升單调触㈣_翁狀電壓提 升早心電賴2在使収件與祕上料相似，唯一 不同點在於觀〇獅__合至触賴偏，而不是像第 圖之控㈣賴2_合至—㈣後之輸人縣，但是由於輸 =電壓Yin與輸出糕vou响本來就存在有時間延遲，因此可以 達到與控制電路302類似的效果。51 512 PMOS 513 > 514 NMOS 540 reverser chain VIII. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: (None) 9. Description of the invention: [Technical field of the invention] Side of the invention The invention relates to a voltage hard circuit and a control method thereof, in particular to a voltage adjustment circuit having a precharge function, so that the staggered age type latch circuit can have a more (four) reaction time to adjust the output voltage to a desired potential. And its control method. · [Prior Art] 1334072 In the circuit system, there are different voltage sources for different needs. For example, after the circuit needs to be loaded, a power supply unit with high power is required. For the integrated circuit chip (1C), It is necessary to perform voltage conversion for signals of different voltage levels. In the conventional technology towel, it f is the wrong-age recording circuit (_s_coupl, ed 1st tch) to achieve the effect of adjusting the voltage level. °月> 1st picture, the first picture shows the conventional technology of the interleaved pickup circuit 1〇〇's electric 5^® 'which contains two pairs of transistors symmetrical to each other ι〇ι and 102 'Each transistor pair contains a P-type MOS transistor and a MOS transistor, which is connected in series with NM〇s, which is the PMOS and NMOS bungee. Coupling to form an output, the gate of each transistor pair PMOS is a control node in the transistor pair, and the control node in each transistor pair is coupled to another pair of transistors The output. Taking the interleaved shackle circuit 100 shown in FIG. 1 as an example 'the transistor pair 1 〇 1 includes a PMOS 110 ′ whose source is coupled to a high voltage source vqdh, and the drain is coupled to the drain of the NMOS 130 to form a node 103. The source of NM〇S13〇 is lightly coupled to ground'. The transistor pair 102 includes a PMOS 120 whose source is coupled to a high voltage source. VDDH 'The drain is coupled to the drain of the NMOS 140 to form a node 1〇4. The source of NMOS 140 is coupled to ground. The control node of the gate of the pMOS 110 is coupled to the node 104 to form a voltage output of the interleaved shackle circuit 10A, and the gate of the PMOS 120 is coupled to the control node of the transistor 2, coupled to the node 103. The 'interleaved coupled shackle circuit 1' further includes an inverter 150' whose input voltage Vin is coupled to the gate of the NMOS 130 and, on the other hand, reversed via the inverter 150 to the gate of the NMOS 140. The operating voltage of the inverter 150 and the input voltage Vin are both VDD. When the input voltage Vin is VDD, the NMOS 130 is turned on (tum on) and the NMOS 140 is turned off (so the voltage of the node 103 is 〇! ^ ^^ is turned on, the MVout of the node 104 is boosted to a higher voltage value, so the PMOS 110 is not turned on, and the NMOS point is maintained at 〇. When the input voltage γ|η is 〇, the NMOS 130 is not turned on and the NMOS 140 is turned on. 'The output voltage v^ut of node 1〇4 will be reduced to 0V'. Therefore, PMOS110 is turned on, the voltage value of node 103 is raised to VDDH so that PMOS120 is not turned on, and the output voltage 乂_ is maintained at 〇¥. However, since the gate voltages of the PMOS 110 and the PMOS 120 depend on whether the NMOS 130 and the NMOS 140 are turned on or off, that is, when the transient is considered, the NMOS 〇 and the NMOS 140 must operate before the PMOS 110 and the PMOS 120. Therefore, the width and length of the NMOS 130 and the NMOS 140 are designed. The ratio (aSpectrati0) must be larger so that it is more mastered than the PMOS 110 and PMOS 120, so that the interleaved shackle circuit 1 can operate normally. However, this also causes the output voltage Vout to rise from 0V to VDDH and the faing time from VDDH to 0V is not equal 'that is, the output voltage is compared to the input voltage. There is a certain amount of distortion. If the input voltage is a pulse width modulation (PWM) signal, the distortion will be more serious considering the process error. In addition, although the output voltage v〇m changes as the voltage level of the input voltage Vin changes, but at the time of conversion? The master control of 1^〇§ is weak (weaker), the speed at which the node boosts the voltage by the PMOS will be slower than the speed at which the NMOS is turned on. Therefore, the NMOS is turned on when the _〇8 of the same transistor pair is not completely turned on. The situation 'causes a large current flowing through the transistor pair to cause a power loss when the voltage level of the input voltage vin changes. Please refer to FIG. 2, which is a circuit diagram of another conventional technique of the interleaved coupling type 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 133 = , , , , , , , , , , , , Only some of the components are connected in different ways, and the well-known technical relationship refers to the above-mentioned hybrid hybrid lock circuit _ description that I easily know that the system is the same as the first _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ No longer. SUMMARY OF THE INVENTION The main purpose of the invention is to provide a pre-charging function and a control method thereof, such that the output voltage is up to the tens of thousands of potentials and its rise time (nsingtime) and The fall time (dirty ^ time) is not too severe to solve the above problem. According to the present judgment - the actual remuneration, the system discloses a voltage adjustment circuit with a pre-charging function, which includes a -interlaced pickup circuit (cross·# latch), which has one of the connection modes being symmetric with each other, a second transistor pair, each transistor pair receiving the input voltage ^ one of the output pairs of each transistor pair is coupled to the other - transistor pair - control node, wherein the second transistor is The output voltage is the output voltage, and the voltage boosting unit is combined with a power supply and the control node of the first-electrode pair, and the wire boosts the voltage of the continent node, and controls the weaving path. The dragon extracting element and the input voltage can be varied to provide a pulse, and the pulse can control the relaying unit to determine the charging time of the control node in the power-to-electric (four) state. According to another embodiment of the present invention, the method for controlling voltage adjustment is used to convert an input voltage to an output voltage having a higher voltage value, 7 1334072, which includes a cross-border The first and the second pair of transistors, each of the pair of transistors receives the input node of each of the input and the output of the transistor, and the output ends are mutually coupled to one of the control nodes of the other pair of transistors, wherein The output voltage of the second transistor pair is a test turn; the input is changed to provide a first pulse; and the first pulse is controlled according to the first pulse to the control node of the first transistor pair Charging time. [Embodiment] The disadvantage of the above-mentioned 'S-known technology is that when the MN (10) in the transistor pair is not turned on, its output voltage is increased by the transistor (4) Cong to VDDH' _PMQS is weak on the ground ( Weakef) (that is, the aspect ratio is smaller and the current flow capacity is weaker); and when the junction is turned on, the voltage of the control node of the PM0S (ie, the gate of the PM0S) must be the same by another transistor. The weaker PM0S raises the voltage of the control node before the PM0S is turned off. These two phenomena cause the output voltage v〇m to be converted from VDDH to 0V. The time is asymmetrical and the voltage signal is distorted, and the power is pulled.) Therefore, the input voltage Vin changes in advance when the input voltage Vin changes, so that the output voltage (10) changes faster and rises. Time and fall time are more symmetrical to reduce distortion and power loss. First, the reference to the 3rd '3rd figure is a circuit diagram of the voltage extraction element 3〇1 and the control circuit 302 of the present invention. In this embodiment, the voltage boosting unit 3〇1 is a source surface to the high electric house. Source VDDH 1> type MOS transistor (pM〇s) 31〇, 8 1334072 But it can also be implemented by other different circuits. The PMOS 310 can be folded to the interleaving mentioned in the prior art. The control node in the coupled pickup circuit 1〇〇, 2〇〇, when the PMOS 310 is turned on, can raise the voltage of the control node to VDDH, accelerate the voltage of the control node to reach a predetermined voltage value, and when the PMOS 310 is not turned on It can be regarded as an open circuit between the interleaved and shackle circuits 1〇〇 and 2〇〇. Whether the PMOS 310 is turned on or not is controlled by the control circuit 312. The control circuit 302 includes a PMOS 320, two NMOSs 330 and 340, a delay unit 350, and an inverter 360. The PMOS 320 is coupled to the high voltage source VDDH, and since its gate is grounded, the PMOS 320 can be regarded as a resistor; NMOS 330 and NMOS 340 are connected in series to each other and respectively to the PMOS 320 and the ground, and the function is similar to a NAND gate. When the voltage of the gate of the two NMOSs (that is, the two input terminals of the NAND gate) is the voltage level "1" (that is, the voltage VDD) nm 〇 S33 〇 and the NMOS 340 are turned on, then the coupling junction of the NMOS 330 and the PMOS 320 The voltage of p is 0, and the voltage of the coupling contact P is the gate voltage of the PMOS 310, thus turning on the PMOS 310. The input voltage Vin is delayed by the delay unit 350 for a predetermined time and then input to the gate of the NMOS 330, while the input voltage Vin is also inverted via the inverter 360 3 and then input to the gate of the NMOS 340 as shown in FIG. 4 when the input voltage yjn is from the voltage When the level "1" is changed to the voltage level "0", the gate voltages of the NMOS 330 and the NMOS 340 are both VDD, and the gate voltage of the PMOS 310 is a pulse, and the pulse width thereof can be controlled by the delay unit 350. During the pulse width time, the PMOS 310 is turned on, and the voltage of the control node in the interleaved light-locking latch circuits 1〇〇, 200 is raised to VDDH, and the voltage of the acceleration control node reaches a predetermined voltage value, thereby knowing that when the input voltage is When the Vin does not change, the handle-contact voltage P is VDDH, and the PMOS 310 is not turned on. 9 1334072 *Month reference to Fig. 5' Fig. 5 is a circuit diagram of the voltage adjustment circuit 5 of the first embodiment of the present invention. The voltage adjustment circuit 5A includes an interleaved light-weight pickup circuit 510. Two voltage boosting units 5〇1 and 5〇3, two control circuits 5〇2 and 5〇4, and a reverser chain 540. The structure and operation principle of the interleaved shackle circuit 510 are the same as those of the interleaved shackle circuit 100 described above, and the structure and operation principle of the voltage boosting units 5〇1 and 5〇3 are the same as those of the voltage boosting unit 301 described above. The structure and operation principle of the control circuits 502 and 504 are the same as those of the aforementioned control circuit 3〇2, and the inverter chain 540 functions as a reverse function and a delay function. The operation principle is as follows. When the input voltage Vm is the voltage level Γ, (ie, vdd), the voltages of the nodes b and d are both VDD 'lang point a, and the c voltage is 〇, so the voltages of the nodes e and f are vj) dh, and the voltage is k liter. The cells 501 and 503 are not turned on, the voltage of the node b is VDD such that the NMOS 513 is turned on, the voltage of the control node g is 〇, so that it is turned on, and because the voltage of the node c is 0, the NM 〇 S 514 is not turned on, so the output voltage v 〇ut is VDDH. PMOS 511 does not conduct. When the input voltage Vin is changed from voltage level to 电压, to voltage level 0 (ie, voltage 〇), the voltage of node a changes from 〇 to Vdd, but node d has not changed at this time (because node a There are three inverters between the nodes d, thus causing a delay time. The voltage value is still VDD, so the node e voltage is quickly pulled to 0 and the voltage boosting unit 501 is turned on, so the voltage of the node g is high. Precharge, the precharge time can be adjusted by the number of inverters in the inverter chain 54〇, the NMOS 513 is not turned on after the voltage of the node b becomes 0, and the voltage value of the control node g is rapidly increased to VDDH by precharge. Make PMOS512 non-conducting, when node 0 voltage becomes 1, NMOS514 Turn on, output voltage Vol^〇, pm〇S51^ pass 'last node d voltage changes to 0, node e voltage returns to vqdjj, the precharge process ends, the entire voltage adjustment circuit 500 resumes steady state operation. On the other hand, when input 1334072 When the voltage Vin is changed from the voltage level "0" to the voltage level "ι" (ie voltage ^1) 〇), the node c has not changed at this time (because the input voltage terminal to the node is separated by three inverters, thus causing A delay time), the voltage value is still VDD, so the node f voltage is quickly pulled to the voltage boosting unit 5〇3 is turned on, so the output voltage v〇ut is precharged to the power supply VDDH' its precharge time can be The number of inverters of the inverter chain 54〇 is adjusted, and the output voltage Vout can be quickly boosted to vddh by precharging. When the voltage of the node c becomes 0, the NMOS 514 is not turned on, and the output voltage v〇ut is fixed to “'node f The voltage is restored to VDDH. At the end of the precharge process, the entire voltage regulation circuit 500 resumes steady state operation. Please refer to FIG. 6. FIG. 6 is a circuit diagram of a second embodiment of the voltage adjustment circuit 6 of the present invention, which is different from the voltage adjustment circuit 5A of FIG. 5 in that the interleaving coupling in the voltage adjustment circuit 500 is performed. The shackle circuit 51 is replaced by a structure similar to the aforementioned interleaved shackle circuit 200. When the input voltage Vin is at the voltage level Γ, (ie, VDD), the voltage of the node b is vdD, and the ship is not turned on. , the voltage of node c is 0 ' NMOS 614 is turned on, causing PM 〇 S612 to be turned on, and the output voltage v 〇 m is. When the input voltage Vin is changed from the voltage level "1" to the voltage level, 〇" J (ie, voltage 〇) The control circuit 6 is similar in that the voltage boosting unit 601 precharges the voltage value of the control node g to VDDH, and the PMOS 612 does not conduct. At this time, since the node_voltage becomes 0; blue (cis 3 is turned on, the output voltage is pulled to 〇. When the input voltage Vin is changed from the voltage level "〇" to the voltage level "丨, (instant, , 〇S613 is not turned on and the conduction is turned on, the control circuit 6〇4 causes the electric lifting unit 603 to output the voltage v 〇ut pre-charged. 凊Reference to 7®, Figure 7 is this issue The circuit diagram of the third embodiment of the electric thinning circuit is characterized in that the interleaved pickup type locking circuit is the aforementioned interlaced pick-up pickup 11 = road contact and 2_ age use, and the miscellaneous wire is used as a cross-over surface--] 10G 2GG is exactly the same 'so the voltage adjustment and the above-mentioned ^1^2 implementation touch Wei and operate Gu Yi, the skilled artisan can easily infer the pieces, please do not repeat them here. Please refer to Figure 8 '8th figure For the invention of the dragon upgrade single and the control circuit ^ off 'f gambling up single touch (four) _ Weng-like voltage boost early ECG 2 in the collection and secret material similar, the only difference is the Guan Yu __ It is not the same as the control of the circuit. It is not the same as the control of the figure (4) _ 2_ to - (4), but because of the transmission = voltage Yin and the output cake vou, there is a time delay, so it can reach the control circuit. 302 similar effect.
J 請參考第9圖，第9圖為本發明電壓調整電路_第四實施例 的電路圖’電壓§周整電路9〇〇包含有一交錯搞合式拾鎖電路 910、兩電壓提升單元901與903、兩控制電路9〇2與9_及一反 2器鏈9^40。其中交錯耦合式拴鎖電路91〇的結構與運作原理與 則述之交錯耦合式拴鎖電路1〇〇相同，而電壓提升單元9〇1血9〇3 的結構與運作原理與前述之提升單元相同，控制電路 902與904的結構與運作原理則與前述之控制電路8似目同，反向 器鏈940則作為反向功能’現詳述其卫作原理如下。當輸入電壓 Vin為電壓準位1”（即ydd)時，節點b電壓解^，節點&、 c電壓則為0，因此節點e、f電屋為，電壓提升單元9〇1與 903皆不導if ’祕b電壓為使得顧⑽丨3導通，控制節 點g電壓為0 ’使得PMOS912導通，另外因為節斯電壓為〇使得 NMOS914不導通，因此輸出電壓乂邮為奶⑽，不導 12 1334072 通。畲輸入電壓Vin由電壓準位”1”改變至電壓準位，，〇，，（即電壓 〇 )時’節點a電壓由0變至VDD ’但輸出電壓VouUt時尚未改變， 電壓值仍是VDDH，因此節點e電壓迅速被拉至〇導至電壓提升 單元901導通，因此節點g的電壓被高電源^^^預充，節點匕 的電壓變為0後NMOS913不導通，控制控制節點g的電壓值可藉 由預充迅速提升至VDDH ’使得PMOS912不導通，當節點〇電 壓變為1時NMOS914導通，此時輸出電壓v〇ut才變為〇， } PM0S911導通，節點e的電壓也恢復至VDDH，預充過程結束， 整個電壓調整電路9〇〇恢復穩態操作。當輸入電壓由電壓準 位”0”改變至電壓準位，T，（即電壓VDD)時，控制節點g的電壓 值此時尚未改變，電壓值仍是VDDH，因此節點『電壓迅速被拉 至〇導至電壓提升單元903導通，因此輸出電壓v〇ut被高電源 VDDH預充，當節點0電壓變為〇時]^]^〇5；914不導通，輸出電壓 Vout固定為VDDH，節點f電壓恢復至，預充過程結束， 整個電壓調整電路9〇〇恢復穩態操作。 請參考第10圖，第1〇圖為本發明電壓調整電路1〇〇〇第五實 施例的電路圖，其與第9圖之電壓調整電路9〇〇的不同處在於將 電壓調整電路900中的交錯耦合式拴鎖電路91〇替換成類似前述 之交錯耦合式拴鎖電路2〇〇的結構，當輸入電壓Vm為電壓準 位”1’’（即VDD)時，節點b電壓為VDD，NMOS1013不導通， 節點c電壓為〇，NM〇S1〇14導通，導致pM〇sl〇12導通，輸出 電壓Vout為VDDH。當輸入電壓\rm由電壓準位”1”改變至電壓 準位”〇”（即電壓0)時，控制電路1002使得電壓提升單元10〇1 將控制節點g的電壓值預充至VDDH，PMOS1012不導通，此時 13 1334072 因為節點b的電壓變為〇，NMOS1013導通’所以輸出電壓被拉 至〇。當輸入電壓Vin由電壓準位”0”改變至電壓準位”丨”（即 VDD)時’ NM0S1G13不導通而麵⑽刚導通控制電路腦 使得電壓提升單元1〇03將輸出電壓v〇m預充至。 請參考第11圖，第11圖為本發明電壓調整電路11〇〇第六實 施例的電路圖，其中的交錯耦合式拴鎖電路為前述之交錯耦合 式拾鎖電賴〇與的齡使肖’其功能雜作顧與交錯輕 合式拴鎖電路1〇〇、2〇〇完全相同’因此電塵調整電路聰與前 述之第四、第五實施綱魏絲作原理亦她，胃 可輕易推論得之，在此不予贅述。 w 請注意，實施例-到實施例六中雖然都使用兩組電麗提升 早讀兩組控制電路，但找際應用上可視需求而 電壓提升單元與控繼路，也就是說，可視需要選擇性地只預 充控制節點或者輸出端的電壓其中之一。 ^ 雖穌發日化揭露難實_揭露如上，然其並非用以限 ^，明，贿熟習此技藝者，在不麟本發明之精神和範圍J, please refer to FIG. 9. FIG. 9 is a circuit diagram of the fourth embodiment of the voltage adjustment circuit of the present invention. The voltage § circumference circuit 9A includes a staggered latching circuit 910, two voltage boosting units 901 and 903, Two control circuits 9〇2 and 9_ and a reverse 2 chain 9^40. The structure and operation principle of the interleaved coupled shackle circuit 91〇 are the same as those of the interleaved shackle circuit 1〇〇 described above, and the structure and operation principle of the voltage boosting unit 9〇1 blood 9〇3 and the aforementioned lifting unit Similarly, the structure and operation principle of the control circuits 902 and 904 are similar to those of the aforementioned control circuit 8, and the inverter chain 940 is used as a reverse function. When the input voltage Vin is the voltage level 1" (ie ydd), the node b voltage is solved, and the node & c voltage is 0, so the nodes e, f are the voltage boosting units 9 〇 1 and 903 The output voltage is such that the voltage of the control node g is 0', so that the voltage of the control node g is 0', so that the PMOS 912 is turned on. In addition, since the NMOS 914 is not turned on, the output voltage is sent as milk (10), and no 12 1334072 通. The input voltage Vin is changed from the voltage level "1" to the voltage level, 〇,, (ie, voltage 〇) when the 'node a voltage changes from 0 to VDD' but the output voltage VouUt has not changed, the voltage value Still VDDH, so the node e voltage is quickly pulled to the voltage boosting unit 901 to be turned on, so the voltage of the node g is precharged by the high power supply ^^^, the voltage of the node 变为 becomes 0, and the NMOS 913 is not turned on, and the control node is controlled. The voltage value of g can be quickly boosted to VDDH ' by pre-charging so that the PMOS 912 is not turned on. When the node 〇 voltage becomes 1, the NMOS 914 is turned on, and the output voltage v〇ut becomes 〇, } PM0S911 is turned on, the voltage of the node e Also restored to VDDH, the precharge process is over, The voltage adjustment circuit 9 〇〇 restores the steady state operation. When the input voltage is changed from the voltage level "0" to the voltage level, T, (ie, voltage VDD), the voltage value of the control node g has not changed at this time, the voltage value Still VDDH, so the node "voltage is quickly pulled to the voltage boosting unit 903 is turned on, so the output voltage v〇ut is precharged by the high power supply VDDH, when the node 0 voltage becomes 〇] ^]^〇5; 914 Non-conducting, the output voltage Vout is fixed to VDDH, the node f voltage is restored to, the pre-charging process is finished, and the entire voltage adjusting circuit 9〇〇 resumes steady-state operation. Please refer to FIG. 10, which is the voltage adjusting circuit 1 of the present invention. The circuit diagram of the fifth embodiment is different from the voltage adjustment circuit 9A of FIG. 9 in that the interleaved shackle circuit 91 电压 in the voltage adjustment circuit 900 is replaced by the interleaved coupling 前述 similar to the above. The structure of the lock circuit 2〇〇, when the input voltage Vm is the voltage level “1” (ie, VDD), the voltage of the node b is VDD, the NMOS 1013 is not turned on, the voltage of the node c is 〇, and the NM〇S1〇14 is turned on, resulting in pM〇sl〇12 is turned on, output voltage V Out is VDDH. When the input voltage \rm is changed from the voltage level "1" to the voltage level "〇" (ie, voltage 0), the control circuit 1002 causes the voltage boosting unit 10〇1 to precharge the voltage value of the control node g to VDDH, PMOS1012 Not conducting, at this time 13 1334072 because the voltage of node b becomes 〇, NMOS1013 turns on 'so the output voltage is pulled to 〇. When the input voltage Vin is changed from the voltage level "0" to the voltage level "丨" (ie VDD), 'NM0S1G13 is not turned on, and the surface (10) just turns on the control circuit brain so that the voltage boosting unit 1〇03 will output the voltage v〇m Filled up. Please refer to FIG. 11. FIG. 11 is a circuit diagram of a sixth embodiment of the voltage adjusting circuit 11 of the present invention, wherein the interleaved coupled shackle circuit is the aforementioned interleaved coupled pickup and the age of the shackle The function of the miscellaneous work is exactly the same as the interlaced light-locking shackle circuits 1〇〇 and 2〇〇. Therefore, the electric dust adjustment circuit is the same as the fourth and fifth implementations of the above-mentioned Weiss, and the stomach can be easily inferred. It will not be repeated here. w Please note that in the embodiment-to-sixth embodiment, although two sets of electric motors are used to enhance the early reading two sets of control circuits, the search for the application needs the voltage boosting unit and the control circuit, that is, the visual selection is required. Only one of the voltages of the control node or the output terminal is precharged. ^ Although it is difficult to expose the above-mentioned issues, it is not used to limit, Ming, and bribe to those skilled in the art, in the spirit and scope of the invention.
J ^ Γ作些許之更動與獅，因此本發明之保魏圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖為f知技術交雜合缺鎖電路之電路圖。 =2圖為另—f知技術交雜合式鋪電路之電路圖。 =3圖為本發明中電壓提升單元與控制電路之電路圖 第4圖為第3圖中輸人賴Vin、延遲輸人、反向輸入電壓以 14 1334072 及接點p電壓之波形圖。 第5圖為本發明電壓調整電路第一實施例之電路圖。 第6圖為本發明電壓調整電路第二實施例的電路圖。 第7圖為本發明電壓調整電路第三實施例的電路圖。 第8圖為本發明電壓提升中單元與控制電路之電路圖。 第9圖為本發明電壓調整電路第四實施例的電路圖。 第10圖為本發明電壓調整電路第五實施例的電路圖。 第11圖為本發明電壓調整電路第六實施例的電路圖。 【主要元件符號說明】 100'200 > 510 > 910 交錯耦合式拴鎖電路 1〇1 ' 102 電晶體對 103、104 節點J ^ makes a few changes and lions, so the scope of the patent application scope of the invention is subject to the definition of patent application. [Simple description of the drawing] Fig. 1 is a circuit diagram of a hybrid technology circuit. The =2 picture is a circuit diagram of another hybrid circuit. Fig. 4 is a circuit diagram of the voltage boosting unit and the control circuit in the present invention. Fig. 4 is a waveform diagram of the input voltage, the delay input, the reverse input voltage, the voltage of 14 1334072, and the voltage of the contact p in Fig. 3. Fig. 5 is a circuit diagram showing a first embodiment of the voltage adjusting circuit of the present invention. Fig. 6 is a circuit diagram showing a second embodiment of the voltage adjusting circuit of the present invention. Fig. 7 is a circuit diagram showing a third embodiment of the voltage adjusting circuit of the present invention. Figure 8 is a circuit diagram of a unit and a control circuit for voltage boosting of the present invention. Figure 9 is a circuit diagram of a fourth embodiment of the voltage regulating circuit of the present invention. Fig. 10 is a circuit diagram showing a fifth embodiment of the voltage adjusting circuit of the present invention. Figure 11 is a circuit diagram of a sixth embodiment of the voltage adjusting circuit of the present invention. [Major component symbol description] 100'200 > 510 > 910 Interleaved coupled shackle circuit 1〇1 '102 transistor pair 103, 104 nodes
110、120、310、320、511、512、611、612、911、912、1011、 1012 PMOS 130、140、330、340、513、514、613、614、830、913、914、 1013、1014 NMOS 150、360 反向器 301 > 501'503'601 ' 603'801 ' 901 ' 903'1001 ' 1003 電 壓提升單元 302、502、504、602、604、802、902、904、1002、1004 控 制電路 350 延遲單元 500、600、700、900、1000、1100 電壓調整電路 15110, 120, 310, 320, 511, 512, 611, 612, 911, 912, 1011, 1012 PMOS 130, 140, 330, 340, 513, 514, 613, 614, 830, 913, 914, 1013, 1014 NMOS 150, 360 inverter 301 > 501 '503 '601 ' 603 ' 801 ' 901 ' 903 '1001 ' 1003 voltage boosting unit 302, 502, 504, 602, 604, 802, 902, 904, 1002, 1004 control circuit 350 delay unit 500, 600, 700, 900, 1000, 1100 voltage adjustment circuit 15