1333073 P2006-0 3 7-TW-A 21681 twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種抖動量測電路，且特別是有關於一 種内建之時脈抖動量測電路。 、 【先前技術】 資料脈衝(Data Pulse)在傳輸線路上傳輪時，如果斧 號發生抖動的話，可能使時脈回復電路(cl〇ck Rec〇ve^ Circuit ’ CDR)或鎖相迴路(PLL)發生問題，甚至資料可能 遺失。抖動可以定義為：訊號之上升緣(或下降緣)相對^ 其理想時間位置的時間偏移量。圖丨顯示出抖動的定義 抖動會使得接收端的位元錯誤率(Bit]Errorilate，ber)提 高’降低整個系統的服務品質(Qua〗ity 〇fSeryice)。 ¥間誤差(TIE ’ Time Interval Error)參數為抖動的參 數之一，其意思是，在任一時間點，接收到的信號位元(或 脈衝)與參考時脈間的相位差。 • -般而S，抖動可歸類為定量性抖動(Deterministic1333073 P2006-0 3 7-TW-A 21681 twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a jitter measurement circuit, and more particularly to a built-in clock Jitter measurement circuit. [Prior Art] When the data pulse is transmitted on the transmission line, if the axe is shaken, the clock recovery circuit (cl〇ck Rec〇ve^ Circuit 'CDR) or phase-locked loop (PLL) may be used. A problem has occurred and even the information may be lost. Jitter can be defined as the time offset of the rising edge (or falling edge) of the signal relative to its ideal time position. Figure 丨 shows the definition of jitter. Jitter will increase the bit error rate (Bit] Errorilate, ber) at the receiving end to reduce the service quality of the entire system (Qua ity 〇 fSeryice). The TIE 'Time Interval Error parameter is one of the jitter parameters, which means the phase difference between the received signal bit (or pulse) and the reference clock at any point in time. • - and S, jitter can be classified as quantitative jitter (Deterministic
Jitter，DJ)與隨機性抖動(Rand〇m Jitter，RJ)。隨機性抖 動為隨機產生的時序雜訊水平抖動。其分布情況通常為 高斯分佈（Gaussian Distribmi〇n)，亦可稱為正規分佈 (Normal Distribution) ° 以目則來现，可利用外接的自動測試設備（ATE, automatic test equipment)來測量抖動。但是，因為要將信 號輸出至自細試設備，所雜號得通過輪出/入接腳。 如此-來’所測量到的抖動可能未必是原先的抖動。此 外，自動測試設備所費不貲，也會額外增加測試成本。 5 1333073 P2006-017-TW-A 21681twf.doc/p 故而，較好能有一種能精準測量抖動的BIST電路， 可降低測試成本、測試時間與減少剛量儀器的使用。 【發明内容】 社唯有f於此，本發明提供—種内建的抖動測量電路，其可 ^抖動’又可降低職成本' 測試時間與減少測量 儀裔的使用。 供—翻建的抖_量電路，其可校正同步雙 才偵測益内之延遲緩衝器，以精準測量抖動。 後，抖動測量電路’其可在每次取樣 後重置同步雙械測器，以減少磁滞效應。 本發明的範例之一提出—絲士 # 用於測量待_脈訊號之抖動。動量測電路， 二，相_電路’對該待測時脈訊號與-參考時脈 訊唬進行不同延遲，並偵測該 ^ ^ ^ 延遲後參考時脈訊關之相位=待測時脈訊號與該 對該同步雙相制電路所彳貞^& ’以及—決疋電路’ 算、資料栓鎖與計數，叫==目位_進行邏輯運 該抖動之—計數值與機率㈣。纟於該彳㈣時脈訊號之 本發明之另一範例提供〜 測量〜參考時脈訊號與—待 d差I測電路，用於 訊號間之—時間差，該待測=路所輪出之-待測時脈 時間差量測電路包括：H至少包括ϋ源’該 待測電路，該同步雙相_=相_電路，祕於該 元與第二延遲緩衝單it，包括—第—延遲缓衝單 時’得到該待測時脈·之 =振錢處於—正常運作 相位之一機率分佈圖，以 6 P2006-017-TW-A 21681twf.doc/p 該相位之該機率分佈圖來校正該 第I遲鐽衝早兀與弟二延遲緩衝單元對該 號所造成之-延遲時間差；以及一決 r考犄脈訊 同步雙相_電路1該同步雙相_電心轉接於該 相位關錢行賴運算、㈣栓料 偵測出的 於該時間差之-計數值。 U數1得到有關 本發明之又-範例提供—種時間差量 測量-參考時脈訊號與—待測.電路所輸出之，航 訊號間之-時間差，該待測電路至少 待測¥脈 時間J量測電路包括:一同步雙相偵測電路，於: 待測電路，該同步雙相偵測電路包括— ''5: 元與第二延遲緩衝單S，當該錄源處缓衝f 時，得到該待測時脈訊號之一相位之二機率八由振' 根據該待測時脈訊號之該相位之該機八杜刀圖以 第-延遲緩衝單元與第二延遲緩衝 號所造成之—延遲時間差；《及-決定電^二二 同步雙相偵測電路，對該同步雙相偵測電 相位關係進行邏輯運算、資料栓鎖 、’丨、 於該時間差之一計數值。 7数μ仵到有關 為讓本發明之上述和其他目的、特徵 顯易懂，下文特舉本發明之較佳實 ^^月 式，作詳細說明如下。 立配合所附圖 【實施方式】 為了使本發明之内容更為明瞭，以下 為本發_實關據以實施的範例。 觀，、她例作 ^33073 P2006-017-TW-A 2168ltwf.doc/p ^圖2顯示根據本發明第一實施例之内建的抖動測量 電路之方塊示意圖。此抖動測量電路主要包括：同步= 相偵測器23與決定電路25{>此抖動測量電路用於偵 測電路21之待測時脈訊號CLKtest的抖動，也就是時脈 訊號CLKtest相對於參考時脈訊號aKref的誤差。此^ 測電路21可為PLL、CDR、DLL(延遲鎖相迴路），或其他 可根據參考時脈訊號而產生另一輸出時脈訊號的相類似 電路。 、 同步雙相偵測器23用於偵測此待測時脈訊號 CLKtest與參考時脈訊號cLKref間的相位關係，並輸出 兩訊號S1/S2至決定電路25。決定電路25計數訊號S1/S2 以得到計數值R1/R2，並送至後端的計算單元/計算軟體 (未示出）’以得到抖動值與其RMS值。 圖3顯示出同步雙相偵測器23與決定電路25之電 路方塊圖。同步雙相偵測器23包括：延遲緩衝器301〜303 與相位偵測單元304〜305。決定電路25包括邏輯電路 311〜312，拴鎖器313〜314，邏輯電路315〜316，多工器 317與計數器318。 延遲緩衝器301與302延遲此參考時脈訊號 CLKref ’並產生延遲後參考時脈訊號pi與D2。延遲緩衝 器303延遲此待測時脈訊號CLKtest，並產生延遲後輸出 時脈訊號D3。延遲緩衝器301〜303所造成的延遲不同， 而且其延遲量是可調整的。比如，延遲緩衝器301所造 成的延遲量最小，延遲缓衝器303所造成的延遲量略大， 而延遲緩衝器302所造成的延遲量最大。 8 1333073 P2006-017-TW-A 2168ltwf.doc/p 相if债測單元304 305比如是D型正反器（dff)。相 位谓測單元綱〜3〇5具有··資料輸入端D，脈輸入端c， 重置端RST與資料輸出端q。相位偵測單元3〇4〜3〇5之資 料輸，端D分別接受延遲後參考脈訊號卯與⑽。相位 偵測單元3G4〜305之時脈輸人端c接受延遲後輸出時脈 訊號D3。相位偵測單元304〜3〇5之重置端RST接受重置 訊號RST。相位偵測單元綱德之資料輸出端Q分別輸 出訊號S1與S2。 訊號S1(其值可能為1或〇)代表延遲後參考時脈訊 號D1與延遲後輸出時脈訊號D3間之相位關係。訊號 S2(其值可能為丨或〇)代表延遲後參考時脈訊號D2與延 遲後輸出時脈訊號D3間之相位關係。 此外，為♦決磁滯效應，在第一實施例中，每當取 樣一筆（也就是產生一筆訊號S1/S2)時，重置訊號RST便 會將相位偵測單元304與305重置。 邏輯電路311與312接收相位偵測單元3〇4與305 之輸出訊號S1與S2。栓鎖器313與314根據延遲後輸出 時脈訊號D3而拴鎖邏輯電路311與312之輸出訊號。邏 輯電路315與316接收栓鎖器313與314之輸出訊號、 延遲後輸出時脈訊號D3與致能訊號Μ，其中致能訊號 ΕΝ由外部測試儀器所產生。栓鎖器313與314與邏輯電 路315與316的組合可以產生脈衝訊號。邏輯電路311 與312之輸出訊號為1，則邏輯電路315與316輸出脈衝 訊號；如邏輯電路311與312之輸出訊號為0，則邏輯電 路315與316不輸出脈衝訊號。 1333073 P2006-017-TW^A 21681 twf.doc/p 多工器317根據選擇訊號SEL而選擇邏輯電路 與316之輸出之一。計數器318則計數多工器gw之 出而產生計數值R1/R2。計數器318比如為連波計數哭】 (Ripple Counter)。利用栓鎖器313/314與計數器 之組合可大幅加速抖動的測量。 °° 第-實施例之BIST電路具有兩種操作模式：測試模 式與校正模式。在測試模式下，待測電路之振 雷 壓控制振盪器vco)會正常操作；而在校正模式下'，(此1 i源則處於自由振盪(free-mn)下。但在本發明之另一奋 施例中，也可以從外部輸入所需要的待測時脈訊& CLKtest來做校正模式。也就是說，當處於校正模式時， 所需要之隨機時脈訊號可能由外部輪入；或者，=需要 之隨機時脈訊號可由待測電路内部之處於自由振蓋二振 盪器所產生。 請參考圖4 ’其顯示在測試模式下，待測時脈訊號 CLKtest之相位0 d之機率分佈函數圖（PDF，pr〇baM丨i^ distribution function)。在測試模式下，假設抖動量 是正規分佈的。根據訊號S1/S2之值，待測時脈訊號 CLKtest之相位可分為三個區塊：小於必―（當sl=〇: S2-0)，介於¢-與¢+之間（當Sl=j，s2=〇);以及大於 ¢+(當 Sl=l，S2=l)。 ' 在圖4中’ P1〜P3分別代表此三個區塊的面積 (PHP2+P3=1) ’也就是’相位位於哪一個區塊的機 率。比如說’ Pl=Rl/(取樣數），P2=R2/(取樣數）。符號τ 代表’當Sl=l與S2=0時，相位之範圍。 1333073 P2006-017-TW-A 21681twf.doc/p 請參考圖5，其顯示在校正模式下，待測時脈訊號 CLKtest之相位0d之機率分佈函數圖。由於待測電路之 振盪源處於自由振盪下，所以待測時脈訊號CLKtest會 隨機產生。也就是說，待測時脈訊號CLKtest與參考時 * 脈訊號CLKref間並無關聯’而且待測時脈訊號CLKtest . 之相位0 d之機率分佈函數圖會呈現均勻分布。符號το 代表參考時脈訊號CLKref(也就是延遲後參考時脈訊號 D1)之周期。符號τ代表延遲緩衝器3〇1與302之延遲時 _ 間差。CLKrefdl與CLKrefd2分別代表圖3之延遲緩衝器 301與302所產生之延遲後參考時脈訊號D1與D2。根據 待測電路之振盪源處於自由振盪時所產生的均勻分布的 統計特性’可得到·· T=P2, *T0。根據τ〇與p2，，可取 得延遲緩衝器301與302之延遲時間差。 圖6顯示相位0d之累加機率分佈函數圖（CDF， cumulative distribution function)。橫轴則為待測時 脈訊號CLKtest之相位#，並以均方根⑽s)值⑷為 • 單位。根據P1 ’ P2，利用圖6可查得相位誤差χ—與x+ (以 σ為单位）。更根據P2，來計算了的值。再由丁與父_、 x+的關係，即可得到—個σ的所對應的相位大小。如果 用公式表示，則為： 〇 =Τ/(χ+-χ,) ，如货Ρ1 一〇. 11〇〇，ρ2=〇 5414時所對應出之 為—1.23而χ+則為+〇39 。所以， σ =0. 04/(0. 39-(-1. 23))=0. 025 圖7顯不权擬結果。參考時脈訊號為 11 1333073 P2006-017-T W-A 21681 twf.doc/p 2· 5GHz，待測時脈訊號CLKtest之抖動之σ為如（即 為 〇.025UI)。 請參考底下的2個抖動值誤差比較表，以更加了解 有無饋入重置訊號RST至相位偵測器之差別。 下表1顯示不饋入重置訊號RST至相位偵測器所得 到之抖動值誤差比較表。 -~~—___ 表 1 PI P2 T 誤差 理想校正狀 0. 0809 0.5686 0.0409 8. 1% 0. 0809 0.5686 0.0375 ------ 15. 9% 3 0. 0809 0.0809 0.5686 0. 5686 0.0380 0. 0369 14.8% 〜— Tl2% --- ' 〜以，，人一N ，π仪正保下， 將圖2之待測時脈訊號cutest以可控制時脈訊號（由訊 旒產生器所產生）所取代。此可控制時脈訊號之相位0d 之機率分佈函數圖會呈現均勻分布’且此可控制時脈訊 號與參考時脈間的相位差為均勻分佈。如此可以進行精 確的校正。校正狀態卜校正狀態3則代表在校正模式中月, 使用不同之自由振盪頻率所測出的結果。 下表2顯示饋入重置訊號RST至相位偵測器所得 之抖動誤差比較表。 ------ P1 P2 誤差 理想校正肤 JU100 0. 5414 0. 0400 1% ------1 12 1333073 P2006-017-TW-A 2l681twf.doc/p 態 ------- 校正狀態1 校正狀態2 0. 1100 0. 5414 0.0389 3. 8% 0. 1100 0. 5414 0.0392 3· 0% 校正狀態3 〇. 1100 0. 5414 0. 0379 6. 1% /、π t κ，-傾八垔直别 偵測斋時’所得到的抖動誤差的確比較小 圖8顯示本發明第二實施例之BIST電路之電路示意Jitter, DJ) and random jitter (Rand〇m Jitter, RJ). Random jitter is a randomly generated temporal noise level jitter. The distribution is usually Gaussian Distribmi〇n, which can also be called Normal Distribution. It can be measured by means of an external automatic test equipment (ATE). However, because the signal is to be output to the self-test device, the number is passed through the wheel/input pin. The jitter measured by this - may not necessarily be the original jitter. In addition, automated test equipment is costly and adds additional testing costs. 5 1333073 P2006-017-TW-A 21681twf.doc/p Therefore, it is better to have a BIST circuit that can accurately measure jitter, which can reduce the test cost, test time and reduce the use of rigid instruments. SUMMARY OF THE INVENTION The present invention provides a built-in jitter measurement circuit that can be used to reduce the cost of the job and reduce the use of the meter. The revamped _ _ circuit, which corrects the delay buffer in the sync doubling detection to accurately measure jitter. Thereafter, the jitter measurement circuit 'resets the synchronous dual-machine detector after each sampling to reduce the hysteresis effect. One of the examples of the present invention proposes that - Silker # is used to measure the jitter of the pulse to be pulsed. The momentum measurement circuit, the second phase _ circuit 'different delays of the clock signal to be tested and the reference clock signal, and detects the phase of the reference clock signal after the delay of the ^ ^ ^ delay = clock to be tested The signal and the synchronization biphasic circuit 彳贞^& 'and the 疋 circuit' calculation, data latching and counting, called == destination _ logically carry the jitter - the count value and the probability (four). Another example of the present invention in which the clock signal is provided is a measurement-reference clock signal and a signal to be measured, which is used for the time difference between the signals, which is to be tested = the road is rotated - The clock time difference measurement circuit to be tested includes: H includes at least a source of the circuit to be tested, the synchronous two-phase _=phase_circuit, secretive to the element and the second delay buffer single it, including - the first delay buffer Single time 'get the time of the clock to be tested · the vibration is in the probability of one of the normal operating phases, and correct the number by the probability distribution of the phase of 6 P2006-017-TW-A 21681twf.doc/p I delayed the delay and the delay time of the second delay buffer unit caused by the delay time difference; and a decision r test pulse synchronous two-phase _ circuit 1 the synchronous two-phase _ core transfer in the phase of the money The row-dependent value and the count value of the time difference detected by the plug material. U number 1 is obtained in accordance with the present invention - the time difference measurement - reference clock signal and - the circuit to be tested, the time difference between the aeronautical signals, the circuit to be tested is at least the time of the pulse to be tested J The measuring circuit comprises: a synchronous two-phase detecting circuit, wherein: the circuit to be tested, the synchronous two-phase detecting circuit comprises - ''5: element and the second delay buffering single S, when the recording source buffers f Obtaining a phase probability of one of the phases of the clock signal to be measured, and generating, by the vibration, a phase of the machine according to the phase of the pulse signal to be measured, the first delay buffer unit and the second delay buffer number - Delay time difference; "and-determine the electric two-two synchronous two-phase detection circuit, the logical operation of the synchronous two-phase detection electrical phase relationship, data latching, '丨, one of the time difference values. In order to make the above and other objects and features of the present invention readily apparent, the preferred embodiment of the present invention will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS [Embodiment] In order to clarify the content of the present invention, the following is an example of implementation of the present invention. View, her example ^33073 P2006-017-TW-A 2168ltwf.doc/p Figure 2 shows a block diagram of a built-in jitter measurement circuit in accordance with a first embodiment of the present invention. The jitter measurement circuit mainly includes: synchronization=phase detector 23 and decision circuit 25{> the jitter measurement circuit is used for detecting the jitter of the clock signal CLKtest of the circuit 21 to be tested, that is, the clock signal CLKtest is relative to the reference. The error of the clock signal aKref. The circuit 21 can be a PLL, CDR, DLL (Delayed Phase Locked Loop), or other similar circuit that can generate another output clock signal based on the reference clock signal. The synchronous dual-phase detector 23 is configured to detect a phase relationship between the clock signal CLKtest to be tested and the reference clock signal cLKref, and output two signals S1/S2 to the decision circuit 25. The decision circuit 25 counts the signal S1/S2 to obtain the count value R1/R2, and sends it to the back end calculation unit/computing software (not shown) to obtain the jitter value and its RMS value. Figure 3 shows a block diagram of the circuit of the synchronous two-phase detector 23 and the decision circuit 25. The synchronous two-phase detector 23 includes delay buffers 301 to 303 and phase detecting units 304 to 305. The decision circuit 25 includes logic circuits 311 to 312, latchers 313 to 314, logic circuits 315 to 316, a multiplexer 317 and a counter 318. Delay buffers 301 and 302 delay this reference clock signal CLKref' and generate delayed reference clock signals pi and D2. The delay buffer 303 delays the clock signal CLKtest to be tested, and generates a delay to output a clock signal D3. The delays caused by the delay buffers 301 to 303 are different, and the amount of delay is adjustable. For example, the delay buffer 301 causes the least amount of delay, the delay buffer 303 causes a slightly larger amount of delay, and the delay buffer 302 causes the largest amount of delay. 8 1333073 P2006-017-TW-A 2168ltwf.doc/p phase debt measurement unit 304 305 is, for example, a D-type flip-flop (dff). The phase predicate unit class ~3〇5 has a data input terminal D, a pulse input terminal c, a reset terminal RST and a data output terminal q. The phase detection units 3〇4~3〇5 are input, and the terminal D receives the delayed reference signals 卯 and (10), respectively. The clock input terminal c of the phase detecting units 3G4 to 305 receives the delay and outputs the clock signal D3. The reset terminal RST of the phase detecting units 304 to 3〇5 receives the reset signal RST. The data output terminal Q of the phase detecting unit Gangde outputs signals S1 and S2, respectively. The signal S1 (the value may be 1 or 〇) represents the phase relationship between the reference clock signal D1 after the delay and the output clock signal D3 after the delay. The signal S2 (which may be 丨 or 〇) represents the phase relationship between the delayed reference signal D2 and the delayed output clock signal D3. Further, in the first embodiment, the reset signal RST resets the phase detecting units 304 and 305 each time a sample is taken (i.e., a signal S1/S2 is generated). The logic circuits 311 and 312 receive the output signals S1 and S2 of the phase detecting units 3〇4 and 305. The latches 313 and 314 latch the output signals of the logic circuits 311 and 312 according to the output of the clock signal D3 after the delay. The logic circuits 315 and 316 receive the output signals of the latches 313 and 314, and output the clock signal D3 and the enable signal 延迟 after the delay, wherein the enable signal 产生 is generated by an external test instrument. The combination of latches 313 and 314 and logic circuits 315 and 316 can generate pulse signals. The output signals of the logic circuits 311 and 312 are 1, and the logic circuits 315 and 316 output the pulse signals; if the output signals of the logic circuits 311 and 312 are 0, the logic circuits 315 and 316 do not output the pulse signals. 1333073 P2006-017-TW^A 21681 twf.doc/p The multiplexer 317 selects one of the outputs of the logic circuit and 316 according to the selection signal SEL. The counter 318 counts the multiplexer gw to generate the count value R1/R2. The counter 318 is, for example, a Ripple Counter. The combination of the latch 313/314 and the counter greatly accelerates the measurement of jitter. ° The BIST circuit of the first embodiment has two modes of operation: test mode and correction mode. In the test mode, the vibration-voltage controlled oscillator vco of the circuit under test will operate normally; and in the calibration mode, (this 1 i source is under free-mn (free-mn). But in the present invention In an example, the required pulse time & CLKtest can be input from the outside to make a correction mode. That is, when in the calibration mode, the required random clock signal may be rotated by the outside; Or, = the random clock signal required can be generated by the free vibrating two oscillator inside the circuit under test. Please refer to Figure 4', which shows the probability distribution of the phase 0 d of the pulse signal CLKtest to be tested in the test mode. Function graph (PDF, pr〇baM丨i^ distribution function). In the test mode, it is assumed that the jitter amount is normally distributed. According to the value of the signal S1/S2, the phase of the clock signal CLKtest to be tested can be divided into three regions. Block: less than must - (when sl = 〇: S2-0), between ¢- and ¢+ (when Sl=j, s2=〇); and greater than ¢+ (when Sl=l, S2=l) ' In Figure 4' P1~P3 represent the area of the three blocks (PHP2+P3=1) 'that is, the phase is located The probability of a block. For example, 'Pl=Rl/(sample number), P2=R2/(sample number). The symbol τ represents the range of phase when Sl=l and S2=0. 1333073 P2006-017- TW-A 21681twf.doc/p Please refer to Figure 5, which shows the probability distribution function of the phase 0d of the pulse signal CLKtest to be tested in the calibration mode. Since the oscillation source of the circuit under test is under free oscillation, it is tested. The clock signal CLKtest is randomly generated. That is to say, there is no correlation between the pulse signal CLKtest to be tested and the reference signal signal CLKref, and the probability distribution function map of the phase 0 d of the pulse signal CLKtest to be tested is uniform. The symbol το represents the period of the reference clock signal CLKref (that is, the post-delay reference clock signal D1). The symbol τ represents the delay _ difference between the delay buffers 3〇1 and 302. CLKrefdl and CLKrefd2 represent the The delays generated by the delay buffers 301 and 302 are referenced to the clock signals D1 and D2. According to the statistical characteristics of the uniform distribution generated when the oscillation source of the circuit under test is in free oscillation, T=P2, *T0 can be obtained. According to τ〇 and p2, can be obtained The delay time difference between the late buffers 301 and 302. Figure 6 shows the cumulative distribution function (CDF) of phase 0d. The horizontal axis is the phase # of the clock signal CLKtest to be measured, and the root mean square (10) s) The value (4) is • unit. According to P1 'P2, the phase error χ- and x+ (in σ) can be found using Fig. 6. The value calculated according to P2. Then, by the relationship between Ding and the parent _, x+, the phase size corresponding to σ can be obtained. If expressed by the formula, it is: 〇=Τ/(χ+-χ,), such as Ρ1 〇. 11〇〇, ρ2=〇5414 corresponds to -1.23 and χ+ is +〇39 . Therefore, σ =0. 04/(0. 39-(-1. 23))=0. 025 Figure 7 shows the results. The reference clock signal is 11 1333073 P2006-017-T W-A 21681 twf.doc/p 2· 5GHz, and the jitter of the pulse signal CLKtest to be tested is σ (ie 〇.025UI). Please refer to the two jitter value error comparison tables below to learn more about the difference between the feed reset signal RST and the phase detector. Table 1 below shows the jitter value error comparison table obtained without feeding the reset signal RST to the phase detector. -~~—___ Table 1 PI P2 T error ideal correction 0. 0809 0.5686 0.0409 8. 1% 0. 0809 0.5686 0.0375 ------ 15. 9% 3 0. 0809 0.0809 0.5686 0. 5686 0.0380 0. 0369 14.8% 〜 Tl2% --- ' ～,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Replace. The probability distribution function diagram of the phase 0d of the control clock signal is uniformly distributed' and the phase difference between the controllable clock signal and the reference clock is evenly distributed. This allows for precise corrections. The correction state 242 correction state represents the result measured using different free oscillating frequencies in the calibration mode month. Table 2 below shows the jitter error comparison table obtained by feeding the reset signal RST to the phase detector. ------ P1 P2 error ideal correction skin JU100 0. 5414 0. 0400 1% ------1 12 1333073 P2006-017-TW-A 2l681twf.doc/p state ------- Calibration state 1 Calibration state 2 0. 1100 0. 5414 0.0389 3. 8% 0. 1100 0. 5414 0.0392 3· 0% Calibration state 3 〇. 1100 0. 5414 0. 0379 6. 1% /, π t κ, - The jitter error obtained when the pendulum is detected immediately is relatively small. FIG. 8 shows the circuit diagram of the BIST circuit of the second embodiment of the present invention.
®基本上，第二實施例之BIST電路之架構雷同於第一 貝施例之BIST電路，只是將圖2之多工器317與計數器 318替換成计數斋siga與gigb。至於第二實施例之運作 方式基本上了由弟一貫施例之描述内容得知，故於此不 再重述。 綜上所述，本發明之上述實施例具有以下的優點： 電路面積小，高操作速度與高準確性。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之 精神和範圍内’當可作些許之更動與潤飾，因此本發明 之·保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1顯示出抖動的定義。 圖2顯示根據本發明第一實施例之内建抖動測量電 路之方塊不意圖。 圖3顯示圖2之同步雙相偵測器與決定電路之電路 方塊圖。 圖4顯示在測試模式下，待測時脈訊號之相位之機 13 1333073 P2006-017-TW-A 21681twf.doc/p 率分佈函數圖。 圖5顯示在校正模式下，待測時脈訊號之相位之機 率分佈函數圖。 圖6顯示待測時脈訊號之相位之累加機率分佈函數 圖。 圖7顯示第一實施例之模擬結果。 圖8顯示本發明第二實施例之内建抖動測量電路之 電路示意圖。 【主要元件符號說明】 21 :待測電路 23 :同步雙相偵測器 25、25‘ ：決定電路 301〜303 :延遲緩衝器 304〜305 :相位偵測單元 311〜312、315〜316 :邏輯電路 313〜314 :栓鎖器 317 :多工器 318、318a、318b :計數器 14® Basically, the architecture of the BIST circuit of the second embodiment is identical to that of the first embodiment of the BIST circuit except that the multiplexer 317 and the counter 318 of FIG. 2 are replaced with the counts siga and gigb. As for the operation mode of the second embodiment, it is basically known from the description of the conventional embodiment of the brother, and therefore will not be repeated here. In summary, the above embodiments of the present invention have the following advantages: small circuit area, high operating speed and high accuracy. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. [Simple description of the diagram] Figure 1 shows the definition of jitter. Fig. 2 shows a block diagram of a built-in jitter measuring circuit according to a first embodiment of the present invention. Figure 3 is a block diagram showing the circuit of the synchronous two-phase detector and decision circuit of Figure 2. Figure 4 shows the phase distribution of the pulse signal to be measured in the test mode. 13 1333073 P2006-017-TW-A 21681twf.doc/p rate distribution function diagram. Figure 5 shows the probability distribution function of the phase of the pulse signal to be measured in the calibration mode. Figure 6 shows the cumulative probability distribution function of the phase of the pulse signal to be measured. Fig. 7 shows the simulation results of the first embodiment. Fig. 8 is a circuit diagram showing the built-in jitter measuring circuit of the second embodiment of the present invention. [Main component symbol description] 21: circuit under test 23: synchronous two-phase detector 25, 25': decision circuits 301 to 303: delay buffers 304 to 305: phase detecting units 311 to 312, 315 to 316: logic Circuits 313 to 314: latch 317: multiplexer 318, 318a, 318b: counter 14