TWI330879B - Spiral inductor with multilayer structure - Google Patents
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- TWI330879B TWI330879B TW96103179A TW96103179A TWI330879B TW I330879 B TWI330879 B TW I330879B TW 96103179 A TW96103179 A TW 96103179A TW 96103179 A TW96103179 A TW 96103179A TW I330879 B TWI330879 B TW I330879B
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- 239000000758 substrate Substances 0.000 claims description 16
- 230000001939 inductive effect Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 230000001965 increasing effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 241000237858 Gastropoda Species 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 210000000078 claw Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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L330879 九、發明說明: 【發明所屬之技術領域】 本發明有關於一種半導體積體電路,特別是有關於一 種具有多層結構的晶片内建電感元件(on-chip inductor )。 【先前技射ί】 數位及類比電路已成功地運用於半導體積體電路。傳 統上,晶片内建電感形成於基底上且運用於射頻頻帶積體 電路設計。第1圖繪示出一習知具有平面螺旋結構之晶片 内建電感元件剖面不意圖。晶片内建電感元件形成於一基 底100上方的介電層104中,其包括一螺旋導線103及一 内連線結構。螺旋導線103嵌入於介電層104中。内連線 結構包括嵌入於一介電層102中的導電插塞105及109及 一導電層107與嵌入於絕緣層104中的導電層111。介電 層102設置於介電層104與基底100之間,而螺旋導線103 藉由導電插塞105及109及導電層107及111而形成一電 流路徑,以與晶片外部或内部電路電性連接。 在通訊系統的快速發展下,系統晶片通常具有射頻電 路及數位或基頻電路。由於射頻電路在糸統晶片中所佔的 面積小於數位或基頻電路,因此整個晶片設計是採用數位 或基頻電路的製程。而相較於一般射頻電路的電感元件, 系統晶片中電感元件的線圈厚度較薄而使得品質因素 (quality factor /Q value )降低。由於積體電路的效能取決 於晶片内建電感元件之品質因素,因此有必要尋求一種新BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor integrated circuit, and more particularly to a wafer-on-chip inductor having a multilayer structure. [Previous Techniques] Digital and analog circuits have been successfully used in semiconductor integrated circuits. Traditionally, on-chip inductors are formed on the substrate and used in RF band integrated circuit design. Fig. 1 is a schematic view showing a conventional in-line inductor element profile having a planar spiral structure. The in-chip inductor component is formed in a dielectric layer 104 above a substrate 100 and includes a spiral conductor 103 and an interconnect structure. The spiral wire 103 is embedded in the dielectric layer 104. The interconnect structure includes conductive plugs 105 and 109 and a conductive layer 107 embedded in a dielectric layer 102 and a conductive layer 111 embedded in the insulating layer 104. The dielectric layer 102 is disposed between the dielectric layer 104 and the substrate 100, and the spiral wire 103 forms a current path through the conductive plugs 105 and 109 and the conductive layers 107 and 111 to electrically connect with external or internal circuits of the wafer. . In the rapid development of communication systems, system chips typically have radio frequency circuits and digital or baseband circuits. Since the RF circuit occupies less than a digital or baseband circuit in a MOSFET, the entire chip design is a digital or baseband circuit. Compared with the inductive component of the general RF circuit, the coil thickness of the inductive component in the system wafer is thin, so that the quality factor (Q value) is lowered. Since the performance of the integrated circuit depends on the quality factor of the built-in inductive component of the chip, it is necessary to seek a new one.
Clients Docket No.: VIT06-0124/2007-01 -24 TT’s Docket No:0608-A40974-TW/fmal/王琮郁 / 5 1.330879 的電感元件結構以增加電感元件的品質因素 【發明内容】 有鑑於此,本發明提供一種 元件,以改善電感品質因素,同時構之螺旋電感 根據上述之目的,本發明提供^種頻率範圍。 旋電感元件’包括:一絕緣層、::導:夕層結構之螺 且具有複數"疊層結構設置:=== 内且連接至螺教‘線與一接地端之間,包括複^ 層及複數導餘塞。這㈣電插塞設置於 1 以電性連接這些導電層。 θ之間用 螺;據土述之目的’本發明提供一種具有多層結構之 、、θ οχ ;基底上。螺旋導線設置於絕緣層内且 :。η個堆疊層結構對應設置於該具有 導線下方的該絕緣層内,其中η不大於 = 此電性連接,錢-堆疊層結構包括:複 ^ = 導電插塞。這些導電插塞電性連接螺旋導線與^等=電 層。對應螺旋導線最外匝與最内匝的導電層層數不同, 具有最多導電層層數的堆疊層結構連接至一接地端。 【實施方式】 以下配合第2及3Α圖說明本發明實施例之具 結構之螺旋電感it件,其中第2圖係緣示出具有多層結二 之螺旋電感元件平面示意圖,而第3Α圖係緣示出^ 2Clients Docket No.: VIT06-0124/2007-01 -24 TT's Docket No:0608-A40974-TW/fmal/王琮郁/ 5 1.330879 Inductor component structure to increase the quality factor of the inductor component [Invention] In view of this, this The present invention provides an element for improving the quality of the inductor while constructing a spiral inductor. According to the above object, the present invention provides a frequency range. The rotary inductance element 'includes: an insulating layer, a:: a snail of a layer structure and has a complex number " laminated structure setting: === and is connected between the thread of the snail and a ground, including a complex ^ Layer and complex guide plugs. The (four) electrical plug is disposed at 1 to electrically connect the conductive layers. The snail is used between θ; according to the purpose of the description, the present invention provides a multilayer structure, θ ο χ; on the substrate. The spiral wire is disposed in the insulating layer and: The n stacked layer structures are correspondingly disposed in the insulating layer below the wire, wherein n is not greater than = the electrical connection, and the money-stack layer structure comprises: a complex ^ = conductive plug. These conductive plugs are electrically connected to the spiral wires and the electrical layer. The number of layers of the outermost turns and the innermost turns of the corresponding spiral wires is different, and the stacked layer structure having the largest number of conductive layers is connected to a ground. [Embodiment] Hereinafter, a spiral inductor (IT) having a structure according to an embodiment of the present invention will be described with reference to FIGS. 2 and 3, wherein the second figure shows a plan view of a spiral inductor element having a plurality of layers of junctions, and the third figure is a flange. Show ^ 2
Client’s Docket Νο.:νΐΤ06·0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王综郁 / 6 1.330879 圖中3-3’線之剖面示意圖。 在第3A圖中,螺旋電感元件包括:嵌入於一絕緣層 中的一螺旋導線221及一堆疊層結構,其中絕緣層設置於 一基底200上。基底200包括一石夕基底或其他習知的半導 體基底。 基底200中可包含各種不同的元件,例如電晶體、電 阻、及其他習用的半導體元件。再者,基底200亦可包含 其他導電層(例如,銅、鋁、或其合金)以及絕緣層(例 如,氧化矽層、氮化矽層、或低介電材料層)。此處為了 簡化圖式’僅以一平整基底表示之。在本實施例中,絕緣 可包括依序設置於基底200上的介電層202、204、206、 208及210。介電層202、204、206、208及210可包括氧 化矽層、氮化矽層、或低介電材料層。 螺旋導線221嵌入於介電層210内,且具有複數匝, 例如三匝。螺旋導線221之外型可為圓型、矩型、六邊型、 八邊型、或多邊型。此處,係以八邊型作為範例說明。 堆疊層結構嵌入於螺旋導線221下方的介電層204、 • 206及208内且連接至螺旋導線221與一接地端G,其包 括複數導電層203、205及207以及複數導電插塞211及 213。舉例而言,導電層203、205及207可對應設置於介 電層204、206及208内。導電層203、205及207彼此重 疊且分開。導電插塞211設置於導電層203及205之間, 而導電插塞213設置於導電層205及207之間,以電性連 接導電層203、205及207,其中相鄰的導電層之間設置至 少二個導電插塞。在本實施例中,導電層203、205及207 與導電插塞211及213之材質可包括銅、鋁、或其合金。Client’s Docket Νο.:νΐΤ06·0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王综郁 / 6 1.330879 Schematic diagram of the 3-3' line in the figure. In Fig. 3A, the spiral inductor element comprises: a spiral wire 221 embedded in an insulating layer and a stacked layer structure, wherein the insulating layer is disposed on a substrate 200. Substrate 200 includes a stone substrate or other conventional semiconductor substrate. A variety of different components can be included in substrate 200, such as transistors, resistors, and other conventional semiconductor components. Further, the substrate 200 may also include other conductive layers (e.g., copper, aluminum, or alloys thereof) and an insulating layer (e.g., a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer). Here, for the sake of simplicity, the figure 'is represented only by a flat substrate. In this embodiment, the insulation may include dielectric layers 202, 204, 206, 208, and 210 disposed on the substrate 200 in sequence. Dielectric layers 202, 204, 206, 208, and 210 can include a hafnium oxide layer, a tantalum nitride layer, or a low dielectric material layer. The spiral wire 221 is embedded in the dielectric layer 210 and has a plurality of turns, such as three turns. The spiral wire 221 may be of a round shape, a rectangular shape, a hexagonal shape, an octagonal shape, or a polygonal type. Here, the octagonal type is taken as an example. The stacked layer structure is embedded in the dielectric layers 204, 206 and 208 below the spiral wires 221 and connected to the spiral wires 221 and a ground terminal G, and includes a plurality of conductive layers 203, 205 and 207 and a plurality of conductive plugs 211 and 213 . For example, conductive layers 203, 205, and 207 may be disposed within dielectric layers 204, 206, and 208, respectively. The conductive layers 203, 205, and 207 overlap and are separated from each other. The conductive plug 211 is disposed between the conductive layers 203 and 205, and the conductive plug 213 is disposed between the conductive layers 205 and 207 to electrically connect the conductive layers 203, 205 and 207, wherein adjacent conductive layers are disposed At least two conductive plugs. In this embodiment, the conductive layers 203, 205, and 207 and the conductive plugs 211 and 213 may be made of copper, aluminum, or an alloy thereof.
Client's Docket No.:VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王琮郁 / 7 1.330879 再者’螺旋導線221之厚度大於導電層203、205及207 之至少一層,而螺旋導線221的線寬大體相同於導電層 203 、 205 及 207 。 其次,兩導電插塞215設置於螺旋導線221與堆疊層 結構之間的介電層208内。其中一導電插塞215電性連接 位於螺旋‘線221最内匝的一端與導電層2〇7、2〇5及2〇3 的一端,而另一導電插塞215電性連接導電層2〇7、2〇5 及203的另一,與位於導電層2〇7上方介電層2〇8内的一 導電層209 ’藉以電性連接螺旋導線221與堆疊層社構。 冒再者,堆疊層結構藉由導電層2〇9而連接至接地端。同樣 地’導電層209與導電插塞215之材質可包括銅、鋁、或 其合金。 S外’需注意的是,上述堆疊層結構係以三層導電層 203、205及207嵌入於介電層2〇4、2〇6及2〇8作為範例 說明,然而多層内連線結構可包括一層或三層以上的導電 層。亦即第3A圖中可只留下導電層2〇3、2〇5及2〇7其中 之一或之一,以電性連接導電層209和螺旋導線221。 • 請參照第3B圖,其繪示出沿第2圖中3_3,線之另一實 施例剖面示意圖,其中相同於第3A圖之部件係使用相同 之標號並省略其說明。 本實施例之堆疊層結構係對應設置於螺旋導線221最 内匝下方的介電層208及206,如第5A及5B圖所示,其 分別繪示出第3B圖的堆疊層結構在介電層208及206的 平面示意圖。亦即’堆疊層結構與螺旋導線221最内匝重 疊。此處,堆疊層結構包括複數導電層205b及207b以及 複數導電插塞213a及21 la。舉例而言,導電層205b及207bClient's Docket No.:VIT06-0124/2007-01-24 TT's Docket No:0608-A40974-TW/final/王琮郁/ 7 1.330879 Furthermore, the thickness of the spiral wire 221 is larger than at least one layer of the conductive layers 203, 205 and 207. The line width of the spiral wire 221 is substantially the same as that of the conductive layers 203, 205, and 207. Next, two conductive plugs 215 are disposed within the dielectric layer 208 between the spiral wires 221 and the stacked layer structure. One of the conductive plugs 215 is electrically connected to one end of the innermost end of the spiral 'line 221 and one end of the conductive layers 2〇7, 2〇5 and 2〇3, and the other conductive plug 215 is electrically connected to the conductive layer 2〇 The other of 7, 2, 5 and 203 is electrically connected to the conductive layer 209' in the dielectric layer 2〇8 above the conductive layer 2〇7 to electrically connect the spiral wire 221 and the stacked layer structure. Further, the stacked layer structure is connected to the ground through the conductive layer 2〇9. Similarly, the material of the conductive layer 209 and the conductive plug 215 may include copper, aluminum, or an alloy thereof. S outside, it should be noted that the above stacked layer structure is illustrated by three conductive layers 203, 205 and 207 embedded in the dielectric layers 2〇4, 2〇6 and 2〇8, but the multilayer interconnect structure can be A layer of one or more conductive layers is included. That is, in Fig. 3A, only one or one of the conductive layers 2?3, 2?5 and 2?7 may be left to electrically connect the conductive layer 209 and the spiral wire 221. • Referring to Fig. 3B, a cross-sectional view of another embodiment of the line taken along line 3-3 of Fig. 2 is used, and the same reference numerals are used for the same parts as those of Fig. 3A, and the description thereof is omitted. The stacked layer structure of the present embodiment corresponds to the dielectric layers 208 and 206 disposed under the innermost turns of the spiral wires 221, as shown in FIGS. 5A and 5B, which respectively illustrate the stacked layer structure of FIG. 3B in dielectric A schematic plan view of layers 208 and 206. That is, the 'stacked layer structure overlaps the innermost turn of the spiral wire 221. Here, the stacked layer structure includes a plurality of conductive layers 205b and 207b and a plurality of conductive plugs 213a and 21la. For example, conductive layers 205b and 207b
Client's Docket No.:VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王琮郁/ 8 1330879 可對應設置於介電層206及208内。導電層205b及207b 彼此重疊且分開。導電插塞213a設置於導電層205b及207b 之間,以電性連接導電層205b及207b,其中相鄰的導電 層之間設置至少二個導電插塞。另外,堆疊層結構藉由設 置於介電層208内的導電插塞215a連接至螺旋導線221, 並藉由導電插塞21 la與一内連線結構及導電層209連接而 接地。在本實施例中,内連線結構包括複數導電層203、 205a及207a及複數導電插塞211、213及215。導電層205a 及207a可對應設置於介電層206及208内。導電插塞211 ® 及213電性連接於導電層203、205a及207a之間,而導電 插塞215電性連接於導電層207a與209之間。 再參照第3B圖。應注意的是導電層205a和205b可直 接在介電層206内電性連接,而不須透過導電插塞211及 ' 211a和導電層203來電性相接,例如第3C圖中位於介電 層204中的導電層203a及203b所示。 請參照第3C圖,其繪示出沿第2圖中3-3’線之另一實 施例剖面示意圖,其中相同於第3A及3B圖之部件係使用 • 相同之標號並省略其說明。在本實施例中,螺旋電感元件 包括具有m匝的螺旋導線221及η個堆疊層結構,其中η 不大於m。再者,堆疊層結構彼此電性連接。一個堆疊層 結構對應設置螺旋導線221之一匝。當η小於m時(例如, η為2,而m為3),螺旋導線221之至少一匝的下方沒有 設置堆疊層結構。舉例而言,螺旋導線221之最外匝的下 方沒有設置堆疊層結構。再者,對應螺旋導線221每一匝 的堆疊層結構中導電層層數可由外匝向内匝增加,使得對 應螺旋導線221最内匝的導電層層數最多,如第6A、6B、Client's Docket No.: VIT06-0124/2007-01-24 TT’s Docket No: 0608-A40974-TW/final/Wang Yuyu/8 1330879 can be disposed in the dielectric layers 206 and 208. The conductive layers 205b and 207b overlap and are separated from each other. The conductive plug 213a is disposed between the conductive layers 205b and 207b to electrically connect the conductive layers 205b and 207b, wherein at least two conductive plugs are disposed between the adjacent conductive layers. In addition, the stacked layer structure is connected to the spiral wire 221 by a conductive plug 215a disposed in the dielectric layer 208, and is grounded by connecting the conductive plug 21 la to an interconnect structure and the conductive layer 209. In the present embodiment, the interconnect structure includes a plurality of conductive layers 203, 205a and 207a and a plurality of conductive plugs 211, 213 and 215. Conductive layers 205a and 207a may be disposed in dielectric layers 206 and 208, respectively. The conductive plugs 211 and 213 are electrically connected between the conductive layers 203, 205a and 207a, and the conductive plugs 215 are electrically connected between the conductive layers 207a and 209. Referring again to Figure 3B. It should be noted that the conductive layers 205a and 205b can be electrically connected directly in the dielectric layer 206 without being electrically connected through the conductive plugs 211 and '211a and the conductive layer 203, for example, the dielectric layer is located in FIG. 3C. Conductive layers 203a and 203b in 204 are shown. Referring to Fig. 3C, there is shown a cross-sectional view of another embodiment taken along line 3-3' in Fig. 2, wherein the same components as those of Figs. 3A and 3B are designated by the same reference numerals and the description thereof will be omitted. In the present embodiment, the spiral inductance element includes a spiral wire 221 having m匝 and n stacked layer structures, where η is not larger than m. Furthermore, the stacked layer structures are electrically connected to each other. A stacked layer structure corresponds to one of the spiral wires 221. When η is smaller than m (for example, η is 2 and m is 3), a stacked layer structure is not provided under at least one turn of the spiral wire 221. For example, the bottom layer of the spiral wire 221 is not provided with a stacked layer structure. Furthermore, the number of conductive layers in the stacked layer structure of each of the corresponding spiral wires 221 can be increased from the outer turn to the inner turn, so that the innermost turn of the corresponding spiral wire 221 has the largest number of conductive layers, such as 6A, 6B,
Clienfs Docket No.:VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王琮郁/ 1330879 及6C圖所示,其分別繪出第3C圖的堆疊層結構在介電詹 208、206、及204的平面示意圖。在本實施例中’位於螺 旋導線221最内匝的一端與下方堆疊層結構中導電層的對 應端連接並藉由一内連線結構連接至接地端G。 在本實施例中,對應於螺旋導線221最内匝的堆疊層 結構包括複數導電層203b、205b及207b以及複數導電插 塞211a、213a、及215a。舉例而言,導電層203b、205b 及207b可對應設置於介電層204、206及208内。導電層 203b、205b及207b之間藉由導電插塞211a及213a彼此 電性連接,並藉由導電插塞215a而電性連接至螺旋導線 221與内連線結構。在本實施例中,内連線結構包括複數 導電層203a、205a及207a及複數導電插塞211、213、及 215。導電層203a、205a及207a可對應設置於介電層204、 206及208内。導電插塞211及213電性連接於導電層 203a、205a及207a之間,而導電插塞215電性連接於導電 層207a與209之間。另外,對應於螺旋導線221中間匝的 堆疊層結構包括複數導電層205c及207c以及複數導電插 • 塞213b及215b。舉例而言,導電層205c及207c可對應 設置於介電層206及208内。導電層205c及207c之間藉 由導電插塞213b彼此電性連接,並藉由導電插塞215b電 性連接至螺旋導線221。 請參照第4A圖,其繪示出沿第2圖中4-4,線之一實 施例剖面示意圖,其中相同於第3A圖之部件係使用相同 之標號並省略其說明。在本實施例中,堆疊層結構嵌入於 介電層204、206、208及210内且連接至螺旋導線221與 一接地端G。而堆疊層結構連接至位於螺旋導線221最外Clienfs Docket No.:VIT06-0124/2007-01-24 TT's Docket No:0608-A40974-TW/final/Wang Yuyu/1330879 and 6C are shown in Fig. 3, which respectively depict the stacked layer structure of the 3C figure in dielectric Zhan A schematic plan view of 208, 206, and 204. In the present embodiment, 'the innermost end of the spiral wire 221 is connected to the corresponding end of the conductive layer in the lower stacked layer structure and is connected to the ground terminal G by an interconnect structure. In the present embodiment, the stacked layer structure corresponding to the innermost turn of the spiral wire 221 includes a plurality of conductive layers 203b, 205b, and 207b and a plurality of conductive plugs 211a, 213a, and 215a. For example, conductive layers 203b, 205b, and 207b may be disposed within dielectric layers 204, 206, and 208, respectively. The conductive layers 203b, 205b, and 207b are electrically connected to each other by the conductive plugs 211a and 213a, and are electrically connected to the spiral wires 221 and the interconnect structure by the conductive plugs 215a. In the present embodiment, the interconnect structure includes a plurality of conductive layers 203a, 205a, and 207a and a plurality of conductive plugs 211, 213, and 215. Conductive layers 203a, 205a, and 207a may be disposed within dielectric layers 204, 206, and 208, respectively. The conductive plugs 211 and 213 are electrically connected between the conductive layers 203a, 205a and 207a, and the conductive plugs 215 are electrically connected between the conductive layers 207a and 209. Further, the stacked layer structure corresponding to the middle turn of the spiral wire 221 includes a plurality of conductive layers 205c and 207c and a plurality of conductive plugs 213b and 215b. For example, conductive layers 205c and 207c may be disposed within dielectric layers 206 and 208, respectively. The conductive layers 205c and 207c are electrically connected to each other by the conductive plugs 213b, and are electrically connected to the spiral wires 221 by the conductive plugs 215b. Referring to Fig. 4A, there is shown a cross-sectional view of one of the lines taken along line 4-4 of Fig. 2, wherein the same components as those of Fig. 3A are denoted by the same reference numerals and the description thereof will be omitted. In the present embodiment, the stacked layer structure is embedded in the dielectric layers 204, 206, 208, and 210 and connected to the spiral wires 221 and a ground terminal G. And the stacked layer structure is connected to the outermost of the spiral wire 221
Client's Docket No. :VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/fmal/王琮郁/ 1330879 匝的一端。 在第4A圖中’堆疊層結構包括複數導電層3〇3、3〇5、 307及223以及複數導電插塞3〇9、311及313。舉例而言, 導電層303、305、307及223可對應設置於介電層204、 206、208及210内。特別地,導電層223與螺旋導線221 位於同的層位’且與位於螺旋導線221最外匝的一端連 接。導電插塞309、311及313設置於導電層303、305、 307及223之間,以電性連接導電層3〇3、3〇5、307及223。 在本實施例中’螺旋導線221之厚度大於導電層303、305、 307及223之至少一層,而螺旋導線221的線寬大體相同 於導電層303、305、307及223。另外,堆疊層結構藉由 導電層223而連接至接地端g。 請參照第4B圖’其繪示出沿第2圖中4-4,線之另一實 • 施例剖面示意圖。而本實施例之堆疊層結構係對應設置於 螺旋導線221最外匝下方的介電層208、206及204,如第 7A至7C圖所示’其分別繪出第4B圖的堆疊層結構在介 電層208、206、及204的平面示意圖。亦即,堆疊層結構 # 與螺旋導線221最外匝重疊,且包括複數導電層303a、305a 及307a以及複數導電插塞309a、311a及313a。舉例而言, 導電層303a、305a及307a可對應設置於介電層204、206 及208内,且彼此重疊並分開。導電插塞309a、311a及 313a設置於導電層303a、305a及307a之間,以作為電性 連接,其中藉由設置於介電層208内的導電插塞313a連接 堆疊層結構與螺旋導線221最外匝的一端,並藉由同樣連 接於螺旋導線221最外匝的一端的導電層223而連接至接 地端G。Client's Docket No. :VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/fmal/王琮郁/ 1330879 One end of the 匝. In Fig. 4A, the stacked layer structure includes a plurality of conductive layers 3?3, 3?5, 307 and 223 and a plurality of conductive plugs 3?9, 311 and 313. For example, conductive layers 303, 305, 307, and 223 may be disposed within dielectric layers 204, 206, 208, and 210, respectively. Specifically, the conductive layer 223 is located at the same layer position as the spiral wire 221 and is connected to the end located at the outermost turn of the spiral wire 221. The conductive plugs 309, 311 and 313 are disposed between the conductive layers 303, 305, 307 and 223 to electrically connect the conductive layers 3〇3, 3〇5, 307 and 223. In the present embodiment, the thickness of the spiral wire 221 is larger than at least one of the conductive layers 303, 305, 307, and 223, and the wire width of the spiral wire 221 is substantially the same as that of the conductive layers 303, 305, 307, and 223. Further, the stacked layer structure is connected to the ground terminal g by the conductive layer 223. Referring to Figure 4B, a cross-sectional view of another embodiment of the line taken along line 4-4 of Figure 2 is shown. The stacked layer structure of the present embodiment corresponds to the dielectric layers 208, 206, and 204 disposed under the outermost turns of the spiral wires 221, as shown in FIGS. 7A to 7C, which respectively depict the stacked layer structure of FIG. 4B. A schematic plan view of dielectric layers 208, 206, and 204. That is, the stacked layer structure # overlaps with the outermost turns of the spiral wires 221, and includes a plurality of conductive layers 303a, 305a, and 307a and a plurality of conductive plugs 309a, 311a, and 313a. For example, the conductive layers 303a, 305a, and 307a may be disposed in the dielectric layers 204, 206, and 208, and overlap and separate from each other. The conductive plugs 309a, 311a, and 313a are disposed between the conductive layers 303a, 305a, and 307a for electrical connection, wherein the stacked layer structure and the spiral wire 221 are connected by the conductive plug 313a disposed in the dielectric layer 208. One end of the outer casing is connected to the ground terminal G by a conductive layer 223 which is also connected to the outermost end of the spiral wire 221.
Client's Docket No.:VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/fmal/王琮郁 / 11 1330879 請參照第4C圖’其繪示出沿第2圖中4_4,線之另一實 施例剖面示意圖,其中相同於第4B圖之部件係使用相同 之標號並省略其說明。本實施例的螺旋電感元件包括且有 m租的螺旋導線221及„個堆疊層結構,其中n不大於爪 (例如’m與η為3)。而本實施例中對應螺旋導線22i 每一阻的堆豐層結構中導電層層數可由内阻向外阻增加, 使得對應螺旋導線221最外阻的導電層層數最多,如第8Α 至8D圖所*,其分別繪示出第4〇圖的堆疊層結構在介電 層208、206、204、及202的平面示意圖。此外,在本實 _施例中’位於螺旋導線221最外_ 一端與下方堆疊層結 構中導電層的對應端連接並藉由同樣連接於螺旋導線221 最外Ε的一端的導電層223而連接至接地端 • 對應於螺旋導線221最外阻的堆疊層結構包括複數導 電層301、303a、305a及307a以及複數導電播塞3〇9a、 311a、313a 及 315。舉例而言’導電層 3〇1、3〇3a、3〇5a 及307a可對應設置於介電層202、204、206及208内。導 電層301、303a、305a及307a之間藉由導電插塞309a、311a φ 及315彼此電性連接’並藉由導電插塞313a電性連接至螺 旋導線221。 再者,對應於螺旋導線221中間匝的堆疊層結構包括 複數導電層303b、305b及307b以及複數導電插塞309b、 311b及313b。舉例而言,導電層303b、305b及307b可對 應設置於介電層204、206及208内。導電層204、206及 208之間藉由導電插塞309b及311b彼此電性連接,並藉 由導電插塞313b電性連'接至螺旋導線221。另外,對應於 螺旋導線221最内匝的堆疊層結構包括複數導電層305c及Client's Docket No.:VIT06-0124/2007-01-24 TT's Docket No:0608-A40974-TW/fmal/王琮郁/ 11 1330879 Please refer to Figure 4C', which shows the 4_4 along the 2nd line, the other line BRIEF DESCRIPTION OF THE DRAWINGS A cross-sectional view of an embodiment in which components are the same as those in FIG. 4B are denoted by the same reference numerals and their description is omitted. The spiral inductor element of this embodiment includes and has a spiral conductor 221 and a stacked layer structure, wherein n is not larger than the claw (for example, 'm and η are 3). In this embodiment, the corresponding spiral wire 22i is blocked. The number of layers of the conductive layer in the stacking structure can be increased by the internal resistance, so that the number of conductive layers corresponding to the outermost resistance of the spiral wire 221 is the largest, as shown in the eighth to eighth figures, which respectively show the fourth layer. The stacked layer structure of the figure is a schematic plan view of the dielectric layers 208, 206, 204, and 202. Further, in the present embodiment, the corresponding end of the conductive layer in the outermost_end of the spiral wire 221 and the lower stacked layer structure Connected and connected to the ground by a conductive layer 223 also connected to the outermost end of the spiral wire 221. The stacked layer structure corresponding to the outermost resistance of the spiral wire 221 includes a plurality of conductive layers 301, 303a, 305a, and 307a and a plurality Conductive plugs 3〇9a, 311a, 313a and 315. For example, the conductive layers 3〇1, 3〇3a, 3〇5a and 307a may be correspondingly disposed in the dielectric layers 202, 204, 206 and 208. Between 301, 303a, 305a and 307a by conductive plugs 309a, 311a Φ and 315 are electrically connected to each other' and electrically connected to the spiral wire 221 by the conductive plug 313a. Further, the stacked layer structure corresponding to the middle turn of the spiral wire 221 includes a plurality of conductive layers 303b, 305b and 307b and a plurality of conductive plugs Plugs 309b, 311b, and 313b. For example, conductive layers 303b, 305b, and 307b may be disposed in dielectric layers 204, 206, and 208. Conductive layers 204, 206, and 208 are electrically connected to each other by conductive plugs 309b and 311b. Electrically connected, and electrically connected to the spiral wire 221 by the conductive plug 313b. In addition, the stacked layer structure corresponding to the innermost turn of the spiral wire 221 includes a plurality of conductive layers 305c and
Client’s Docket No. :VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/final/王琮郁 / 1.330879 307c以及複數導電插塞311c及313c。舉例而言,導電層 305c及307c可對應設置於介電層206及208内。導電層 305c及307c之間藉由導電插塞311c彼此電性連接,並藉 由導電插塞313c電性連接至螺旋導線221。需注意的是, 螺旋導線221之最内匝的下方亦可沒有設置堆疊層結構。 應注意的是,在本發明的實施例中,堆疊層結構中導 電層間是藉由許多導電插塞而電性並聯。 在上述實施例中,堆疊層結構的作用在於減少螺旋導 線221的導體損失(conductor loss ),藉以在不增加螺旋 * 導線221的厚度情形下提升電感元件的品質因素。再者, 堆疊層結構或是具有最多導電層層數的堆疊層結構係電性 連接於螺旋導線221之接地的一端G (即,位於螺旋導線 221最内匝或最外匝之一端)。由於螺旋導線221之接地 端具有較南的電流密度(即5較南的磁場)與較低電場’ 故可緩和堆疊層結構與基底之間的寄生電容效應。因此, 根據本發明之螺旋電感元件可在提升電感元件品質因素的 同時,維持電感元件可用的頻率範圍。 • 雖然本發明已以較佳實施例揭露如上,然其並非用以 限定本發明,任何熟習此項技藝者,在不脫離本發明之精 神和範圍内,當可作更動與潤飾,因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係繪示出習知電感元件剖面示意圖。 第2圖係繪示出根據本發明實施例之具有多層結構之 螺旋電感元件平面示意圖。Client's Docket No. :VIT06-0124/2007-01-24 TT’s Docket No: 0608-A40974-TW/final/Wang Yuyu / 1.330879 307c and a plurality of conductive plugs 311c and 313c. For example, conductive layers 305c and 307c may be disposed in dielectric layers 206 and 208, respectively. The conductive layers 305c and 307c are electrically connected to each other by a conductive plug 311c, and are electrically connected to the spiral wire 221 by a conductive plug 313c. It should be noted that the stacked layer structure may not be disposed under the innermost turn of the spiral wire 221 . It should be noted that in the embodiment of the present invention, the conductive layers in the stacked layer structure are electrically connected in parallel by a plurality of conductive plugs. In the above embodiment, the function of the stacked layer structure is to reduce the conductor loss of the spiral wire 221, thereby improving the quality factor of the inductance element without increasing the thickness of the spiral wire 221 . Furthermore, the stacked layer structure or the stacked layer structure having the largest number of conductive layers is electrically connected to one end G of the ground of the spiral wire 221 (i.e., at the innermost or outermost end of the spiral wire 221). Since the grounding end of the spiral wire 221 has a souther current density (i.e., a 5 souther magnetic field) and a lower electric field, the parasitic capacitance effect between the stacked layer structure and the substrate can be alleviated. Therefore, the spiral inductor element according to the present invention can maintain the frequency range available for the inductor element while improving the quality factor of the inductor element. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional inductive element. Fig. 2 is a plan view showing a spiral inductor element having a multilayer structure according to an embodiment of the present invention.
Client's Docket No.:VIT06-0124/2007-01-24 TT’s Docket No:0608-A40974-TW/fmal/王琮郁 / 1330879 第3A至3C圖係繪示出沿第2圖中3-3’線之具有多層 結構之螺旋電感元件實施例剖面示意圖。 第4A至4C圖係繪示出沿第2圖中4-4’線之具有多層 結構之螺旋電感元件實施例剖面示意圖。 第5A及5B圖係分別繪示出第3B圖的堆疊層結構在 介電層208及206的平面示意圖。 第6A、6B、及6C圖係分別繪示出第3C圖的堆疊層 結構在介電層208、206、及204的平面示意圖。 第7A、7B、及7C圖係分別繪示出第4B圖的堆疊層 結構在介電層208、206、及204的平面示意圖。 第8A、8B、8C、及8D圖係分別繪示出第4C圖的堆 疊層結構在介電層208、206、204、及202的平面示意圖。 【主要元件符號說明】 〜螺旋導線;ioo、200〜基底;102、104、202、 204、 206、208、210〜介電層;107、111、203、203a、 205、 205a、205b、205c、207、207a、207b、207c、209、 223、301、303、303a、303b、305、305a、305b、305c、 307、307a、307b、307c〜導電層;105、109、2n、211a、 213、213a、213b、215、215a、215b、309、309a、309b、 311、311a、311b、311c、313、313a、313b、313c、315〜 導電插塞;G〜接地端。Client's Docket No.:VIT06-0124/2007-01-24 TT's Docket No:0608-A40974-TW/fmal/王琮郁/ 1330879 Figures 3A to 3C show the 3-3' line along the 2nd figure A schematic cross-sectional view of an embodiment of a multi-layered spiral inductor element. 4A to 4C are cross-sectional views showing an embodiment of a spiral inductor element having a multilayer structure along the line 4-4' in Fig. 2. 5A and 5B are plan views showing the stacked layer structures of Fig. 3B at dielectric layers 208 and 206, respectively. 6A, 6B, and 6C are schematic plan views showing the stacked layer structures of the 3Cth layer in the dielectric layers 208, 206, and 204, respectively. 7A, 7B, and 7C are plan views showing the stacked layer structures of Fig. 4B at dielectric layers 208, 206, and 204, respectively. 8A, 8B, 8C, and 8D are schematic plan views of the stacked structures of the 4Cth layer at dielectric layers 208, 206, 204, and 202, respectively. [Description of main component symbols] ~ spiral wire; ioo, 200~ substrate; 102, 104, 202, 204, 206, 208, 210 to dielectric layer; 107, 111, 203, 203a, 205, 205a, 205b, 205c, 207, 207a, 207b, 207c, 209, 223, 301, 303, 303a, 303b, 305, 305a, 305b, 305c, 307, 307a, 307b, 307c~ conductive layer; 105, 109, 2n, 211a, 213, 213a , 213b, 215, 215a, 215b, 309, 309a, 309b, 311, 311a, 311b, 311c, 313, 313a, 313b, 313c, 315~ conductive plug; G~ ground.
Client’s Docket No. :VIT06-0124/2007-01 -24 TT’s Docket No:0608-A40974-TW/final/王琮郁/ 14Client’s Docket No. :VIT06-0124/2007-01 -24 TT’s Docket No:0608-A40974-TW/final/王琮郁/ 14
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