1329915 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構’且特別是有關於一種 以晶圓來製作電路板之方法與應用結構。 【先前技術】 隨著電子產品的應用領域日漸廣泛，電子產品除了必須 忍受嚴苛環境，還可能曝露在劇烈的溫度波動中，或承受激 烈振動。目前，電子產品之應用電路，幾乎由半導體晶片結 • 合傳統印刷電路板來製作。因此’爲了提高電子產品可靠度， 必須強化半導體晶片與印刷電路板之結合強度。 由於習知電路板製作技術，幾乎皆將晶片銲接於傳統印 刷電路板上，週邊再佈設應用電路，因此產生許多嚴重的問 ' 題。由於晶片與傳統印刷電路板之膨脹係數不同，因此在受 ； 熱時，晶片與傳統印刷電路板之接觸點，容易損毀，造成電 路運作異常。另外，傳統印刷電路板易吸收水氣，造成電氣 特性改變，易使晶片運作不正常。再者，就製造時程而言， 習知技術在製作傳統印刷電路板後，其製作時程需時數週， • 時程相當長。在成本的考量上，由於晶片與習知印刷電路板 係分離製造，因此容易造成印刷電路板之庫存問題。 【發明內容】 有鑒於此，本發明的目的就是在提供一種以晶圓製作電 路板之方法與其應用結構。藉由本發明之應用結構，可使電 •子產品之可靠度提高，並且不易造成庫存。 爲達成上述及其他目的，本發明提出一種以晶圓製作電 路板之方法。此方法包括下列步驟：藉由半導體製程技術， 於一片第一晶圓中製作複數片矽電路板。之後，藉由半導體 1329915 製程技術，於一片第二晶圓中製作複數片晶片。接著，切割 第二晶圓，將這些晶片設置於對應之矽電路板。接下來，將 複數條導電線之一端銲接於晶片之對應接點，另一端銲接矽 電路板之對應銲接點。之後，藉由這些導電線，使此晶片電 • 性耦接此矽電路板後，使晶片與矽電路板結合成一體。經壓 模後，再硏磨第一晶圓背面至銲墊裸露。接下來，於第一晶 圓背面植球，切割第一晶圓，成爲複數片電路模組。 爲達成上述及其他目的，本發明提出一種以晶圓製作電 路板之應用結構。此應用結構包括矽電路板、晶片與複數條 瞻 導電線。其中’矽電路板具有複數個接點。晶片貼合於前述 矽電路板，並具有複數個接點。複數條導電線之一端銲接晶 片之對應接點’另一端銲接矽電路板之對應銲接點。再者， 藉由半導體製程，於第一晶圓中製作複數片矽電路板，每一 片矽電路板設置應用電路，並以η層製作，其中，η係爲整數， -且η大於1。藉由這些導電線，使此晶片電性耦接此矽電路板 後，使晶片與矽電路板結合成一體，切割第一晶圓，成爲複 數片電路模組。 依照本發明的較佳實施例所述，上述之方法，更包括運 • 用半導體製程技術，於矽電路板佈設複數條電路跑線。 依照本發明的較佳實施例所述，上述之電路跑線之材質 係爲金或銅。 依照本發明的較佳實施例所述，上述之方法，更包括利用半 導體製程，於矽電路板設置複數個金屬接點。 依照本發明的較佳實施例所述，上述之金屬接點之材質 係爲金或銅。 依照本發明的較佳實施例所述，上述之矽電路板具有複 數個灌孔。 1329915 依照本發明的較佳實施例所述，切割第二晶圓後，將此 些晶片黏著於對應之此些矽電路板上。 綜合上述，本發明提出一種以晶圓來製作電路板之方法 與應用結構。由於本發明係利用矽來製作電路板，因此晶片 • 與矽電路板不會因膨脹係數不同，而造成損毀。再者，矽電 . 路板不易吸收水氣，造成晶片功能異常。因此，本發明能大 幅提高電子產品之可靠度。本發明不僅能克服習知技術之缺 點，更具有極高之新穎性與進步性。 【實施方式】 • 請參照第1圖，其繪示的是依照本發明一較佳實施例之 以晶圓製作電路板之應用結構立體分解圖。應用結構1〇〇包 括膠餅102、晶片104、黏著層105(圖中未繪出)與矽電路板 106。矽電路板106在本實施例中由四層電路板組成，分別爲 / 第一電路板108、第二電路板110、第三電路板112與第四電 路板114。其中，第一電路板108上除銲接點204外，會覆 蓋一層護層（圖中未繪出），以保護電路板108內含複數條電 路跑線116與複數個金屬接點118，其中，護層之材質係爲聚 亞醯胺。第二電路板110內含複數個灌孔120。類似的，第三 • 電路板112內含複數條電路跑線122。第四電路板114內含 複數個金屬植球接點124，藉由雷射或其他習知可行之方式可 形成這些金屬植球接點，然後再進行電鍍（Plating)。第四電路 板之另一表面經硏磨，以形成複數個金屬植球接點，該些金 ' 屬植球接點經植球後可電性耦接傳統印刷電路板。晶片104 與矽電路板106以複數條導電線電性耦接（圖中未繪出）。 第2A〜2C圖係第1圖之應用結構100實際組裝後之示意 圖（第2A圖與第2C圖之金屬接點數與第1圖不一致，在此僅 爲舉例之用）。請參照第2A圖，其繪示的是依照本發明一較 1329915 佳實施例之以晶圓製作電路板之應用結構俯向透視圖。如圖 所示，晶片104與矽電路板106以複數條導電線202電性耦 接。矽電路板106具有複數個銲接點204。晶片104透過黏 著層105貼合於矽電路板106，且具有複數個接點。再者， • 數條導電線之一端耦接晶片1〇4之對應接點，另一端耦接矽 . 電路板1〇6之對應銲接點204。其中，藉由半導體製程，於 第一晶圓中製作複數片矽電路板，每一片矽電路板設置應用 電路，並以η層製作，其中，η係爲整數，且η大於1。在本 實施例中，η係等於4，其實施結構如第1圖所示，不再重述。 • 請參照第2Β圖，其繪示的是依照本發明一較佳實施例之以晶 圓製作電路板之應用結構剖面圖。請參照第2C圖，其繪示的 是依照本發明一較佳實施例之以晶圓製作電路板之應用結構 仰視圖。如第2C圖所示，應用結構100之底部經硏磨後，使 / 植球接點裸露。之後，再植金屬球206於應用結構100之底 部，使應用結構1〇〇可電性耦接傳統印刷電路板。 再者，利用半導體製程，可於矽電路板106佈設複數條 電路跑線。並且，電路跑線之材質可爲金或銅。另外，利用 半導體製程，可於矽電路板106設置複數個金屬接點。並且， • 電路跑線之材質可爲金或銅。藉由導電線使晶片1〇4電性耦 接矽電路板106後，可切割第一晶圓。接著，將晶片104黏 著於對應之矽電路板106上。 本發明提供一種以晶圓製作電路板之方法，包括下列步 驟：利用半導體製程，於第一晶圓中製作複數片矽電路板。 之後，利用半導體製程，於第二晶圓中製作複數片晶片。接 下來，切割第二晶圓，將晶片設置於對應之矽電路板。接著， 將複數條導電線之一端耦接晶片之對應接點，另一端耦接矽 電路板之對應銲接點。藉由該些導電線，使該晶片電性耦接 1329915 該矽電路板後，切割該第一晶圓。再者，利用半導體製程， 可於矽電路板佈設複數條電路跑線與複數個金屬接點。 綜合上述，本發明提出一種以晶圓來製作電路板之方法 與應用結構。由於本發明係利用半導體製造來製作電路板， • 因此在產量上相較於傳統刷電路板更具有優勢。再者，晶圓 . 製作矽電路板之時程短，只需要數日即可完成，相較於傳統 刷電路板之製造時程爲數週，更具有時效。因此，本發明可 有效提升量產效率，具有極高之產業利用性。 晶片與矽電路板不會因膨脹係數不同，而造成損毀。 • 値得注意的是，上述的說明僅是爲了解釋本發明，而並 非用以限定本發明之實施可能性，敘述特殊細節之目的，乃 是爲了使本發明被詳盡地了解。然而，熟習此技藝者當知此 並非唯一的解法。在沒有違背發明之精神或所揭露的本質特 徵之下，上述的實施例可以其他的特殊形式呈現，而隨後附 .* 上之專利申請範圍則用以定義本發明。 【圖式簡單說明】 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明 • 如下： 第1圖繪示的是依照本發明一較佳實施例之以晶圓製作 電路板之應用結構立體分解圖； 第2A圖繪示的是依照本發明一較佳實施例之以晶圓製作 電路板之應用結構俯視圖； • 第2B圖繪示的是依照本發明一較佳實施例之以晶圓製作 電路板之應用結構剖面圖；以及， 第2C圖繪示的是依照本發明一較佳實施例之以晶圓製作 電路板之應用結構仰視圖。 1329915 【主要元件符號說明】 圖式之標示說明： 100 :應用結構 102 :膠餅 104 :晶片 105 :黏著層 1 06 :砍電路板 108 :第一電路板 110 :第二電路板 112 :第三電路板 114 :第四電路板 116，122 :電路跑線 204:銲接點 118 :金屬接點 120 :灌孔 124 :金屬植球接點 202 :導電線 206 :金屬球1329915 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor structure and, more particularly, to a method and an application structure for fabricating a circuit board using a wafer. [Prior Art] With the increasing use of electronic products, electronic products may be exposed to severe temperature fluctuations or subjected to severe vibrations in addition to being subjected to harsh environments. At present, the application circuit of electronic products is almost made of semiconductor wafers and conventional printed circuit boards. Therefore, in order to improve the reliability of electronic products, it is necessary to strengthen the bonding strength between the semiconductor wafer and the printed circuit board. Due to the conventional circuit board manufacturing technology, almost all of the wafers are soldered to the conventional printed circuit board, and the application circuit is disposed in the periphery, thus causing many serious problems. Since the expansion coefficient of the wafer is different from that of the conventional printed circuit board, the contact point between the wafer and the conventional printed circuit board is easily damaged when subjected to heat, resulting in abnormal operation of the circuit. In addition, the conventional printed circuit board is easy to absorb moisture, causing changes in electrical characteristics, which may cause the wafer to operate abnormally. Moreover, in terms of manufacturing time, the conventional technology of manufacturing a conventional printed circuit board requires a few weeks to make the production process, and the time course is rather long. In terms of cost considerations, since the wafer is manufactured separately from the conventional printed circuit board, it is easy to cause inventory problems of the printed circuit board. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a method of fabricating a circuit board from a wafer and an application structure thereof. With the application structure of the present invention, the reliability of the electric product can be improved and it is difficult to cause inventory. To achieve the above and other objects, the present invention provides a method of fabricating a circuit board from a wafer. The method includes the steps of: fabricating a plurality of germanium circuit boards in a first wafer by semiconductor processing techniques. Thereafter, a plurality of wafers are fabricated in a second wafer by semiconductor 1329915 process technology. Next, the second wafer is diced, and the wafers are placed on the corresponding 矽 board. Next, one end of the plurality of conductive lines is soldered to the corresponding contacts of the wafer, and the other end is soldered to the corresponding solder joint of the circuit board. Then, by electrically connecting the wafer to the germanium circuit board by using the conductive wires, the wafer and the germanium circuit board are integrated into one body. After compression molding, the back side of the first wafer is honed to the bare pad. Next, the ball is implanted on the back side of the first crystal, and the first wafer is cut to become a plurality of circuit modules. To achieve the above and other objects, the present invention provides an application structure for fabricating a circuit board by wafer. This application structure includes a 矽 board, a wafer, and a plurality of conductive lines. The '矽 board has a plurality of contacts. The wafer is bonded to the aforementioned circuit board and has a plurality of contacts. One end of the plurality of conductive wires is soldered to the corresponding solder joint of the wafer, and the other end is soldered to the corresponding solder joint of the circuit board. Furthermore, a plurality of germanium circuit boards are fabricated in the first wafer by a semiconductor process, and each of the germanium circuit boards is provided with an application circuit and fabricated in an n-layer, wherein η is an integer, and η is greater than 1. After the conductive circuit is electrically coupled to the circuit board, the wafer and the germanium circuit board are integrated into one body, and the first wafer is cut into a plurality of circuit modules. According to a preferred embodiment of the present invention, the above method further includes using a semiconductor process technology to lay a plurality of circuit running lines on the circuit board. According to a preferred embodiment of the present invention, the circuit running line is made of gold or copper. In accordance with a preferred embodiment of the present invention, the method further includes the use of a semiconductor process to place a plurality of metal contacts on the circuit board. According to a preferred embodiment of the invention, the metal contacts are made of gold or copper. In accordance with a preferred embodiment of the present invention, the above-described circuit board has a plurality of holes. 1329915 In accordance with a preferred embodiment of the present invention, after the second wafer is diced, the wafers are adhered to the corresponding NMOS boards. In summary, the present invention proposes a method and an application structure for fabricating a circuit board using a wafer. Since the present invention uses a crucible to fabricate a circuit board, the wafer and the germanium circuit board are not damaged by the difference in expansion coefficient. Furthermore, the circuit board is not easy to absorb moisture, resulting in abnormal function of the wafer. Therefore, the present invention can greatly improve the reliability of electronic products. The present invention not only overcomes the shortcomings of the prior art, but also has a very high novelty and progress. [Embodiment] Referring to Figure 1, there is shown an exploded perspective view of an application structure of a circuit board fabricated in accordance with a preferred embodiment of the present invention. The application structure 1 includes a blanket 102, a wafer 104, an adhesive layer 105 (not shown), and a germanium circuit board 106. The circuit board 106 is composed of four layers of circuit boards in this embodiment, which are / first circuit board 108, second circuit board 110, third circuit board 112, and fourth circuit board 114, respectively. The first circuit board 108 is covered with a protective layer (not shown) in addition to the solder joint 204, so as to protect the circuit board 108 from a plurality of circuit running lines 116 and a plurality of metal contacts 118, wherein The material of the sheath is polyamine. The second circuit board 110 includes a plurality of filling holes 120 therein. Similarly, the third circuit board 112 contains a plurality of circuit running lines 122. The fourth circuit board 114 contains a plurality of metal ball joints 124 which can be formed by laser or other conventional means and then plated. The other surface of the fourth circuit board is honed to form a plurality of metal ball joints, and the gold ball joints are electrically coupled to the conventional printed circuit board after the ball is implanted. The wafer 104 and the germanium circuit board 106 are electrically coupled by a plurality of conductive lines (not shown). 2A to 2C are schematic diagrams of the application structure 100 of Fig. 1 after actual assembly (the number of metal contacts in Figs. 2A and 2C is inconsistent with Fig. 1 and is merely exemplary here). Please refer to FIG. 2A, which is a perspective view showing the application structure of a wafer-made circuit board according to a preferred embodiment of the present invention. As shown, the wafer 104 and the germanium circuit board 106 are electrically coupled by a plurality of conductive lines 202. The circuit board 106 has a plurality of solder joints 204. The wafer 104 is bonded to the germanium circuit board 106 through the adhesive layer 105 and has a plurality of contacts. Furthermore, one of the plurality of conductive lines is coupled to the corresponding contact of the wafer 1〇4, and the other end is coupled to the corresponding solder joint 204 of the circuit board 1〇6. Wherein, a plurality of germanium circuit boards are fabricated in the first wafer by a semiconductor process, and each of the germanium circuit boards is provided with an application circuit and is fabricated in an n-layer, wherein η is an integer and η is greater than 1. In the present embodiment, the η system is equal to 4, and the implementation structure is as shown in Fig. 1, and will not be repeated. • Referring to Figure 2, there is shown a cross-sectional view of an application structure for fabricating a circuit board in accordance with a preferred embodiment of the present invention. Referring to FIG. 2C, a bottom view of an application structure of a wafer fabricated circuit board in accordance with a preferred embodiment of the present invention is shown. As shown in Fig. 2C, the bottom of the application structure 100 is honed to expose the / ball joint. Thereafter, the metal ball 206 is replanted at the bottom of the application structure 100 to electrically couple the application structure to the conventional printed circuit board. Furthermore, a plurality of circuit running lines can be disposed on the circuit board 106 by using a semiconductor process. Moreover, the material of the circuit running line can be gold or copper. In addition, a plurality of metal contacts can be provided on the germanium circuit board 106 by means of a semiconductor process. And, • The material of the circuit running line can be gold or copper. After the wafer 1 4 is electrically coupled to the circuit board 106 by conductive wires, the first wafer can be diced. Next, the wafer 104 is adhered to the corresponding germanium circuit board 106. The present invention provides a method of fabricating a circuit board from a wafer, comprising the steps of: fabricating a plurality of germanium circuit boards in a first wafer using a semiconductor process. Thereafter, a plurality of wafers are fabricated in the second wafer using a semiconductor process. Next, the second wafer is diced, and the wafer is placed on the corresponding 矽 board. Then, one end of the plurality of conductive lines is coupled to the corresponding contact point of the chip, and the other end is coupled to the corresponding solder joint of the 电路 circuit board. After the conductive circuit is electrically coupled to the 1329915 circuit board, the first wafer is cut. Moreover, by using a semiconductor process, a plurality of circuit running lines and a plurality of metal contacts can be disposed on the circuit board. In summary, the present invention proposes a method and an application structure for fabricating a circuit board using a wafer. Since the present invention utilizes semiconductor fabrication to fabricate circuit boards, it is therefore advantageous in terms of throughput over conventional brushed circuit boards. Furthermore, wafers have a short time frame for making 矽 boards, which can be completed in a few days. Compared to traditional brush boards, the manufacturing time is several weeks, which is more time-efficient. Therefore, the present invention can effectively improve mass production efficiency and has extremely high industrial utilization. The wafer and the 矽 circuit board are not damaged by the difference in expansion coefficient. It is to be understood that the foregoing description is only illustrative of the invention and is not intended to However, those skilled in the art are aware that this is not the only solution. The above-described embodiments may be presented in other specific forms without departing from the spirit and scope of the invention, and the scope of the appended claims is intended to define the invention. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent and understood from An exploded perspective view of an application structure of a wafer fabricated circuit board in accordance with a preferred embodiment of the present invention; and FIG. 2A illustrates an application of a wafer fabricated circuit board in accordance with a preferred embodiment of the present invention. FIG. 2B is a cross-sectional view showing an application structure of a wafer fabricated circuit board in accordance with a preferred embodiment of the present invention; and FIG. 2C is a view showing a preferred embodiment of the present invention. A bottom view of the application structure of a circuit board fabricated on a wafer. 1329915 [Explanation of main component symbols] Description of the designation of the drawing: 100: Application structure 102: adhesive cake 104: wafer 105: adhesive layer 106: chopping circuit board 108: first circuit board 110: second circuit board 112: third Circuit board 114: fourth circuit board 116, 122: circuit running line 204: solder joint 118: metal contact 120: filling hole 124: metal ball joint 202: conductive line 206: metal ball