1329852 P92152 13243twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種殘影消除電路，且特別是有關於 種適用於當發生非正常斷電時，可提供充電電力給顯示 面板和驅動電路的殘影消除電路。 【先前技術】 液晶材料乃是在歐洲被發現、在美國得以發展、在曰 本被應用於若干領域。目前，已有許多種液晶技術被廣泛 地應用於顯示器，尤其是液晶顯示器（丨丨叩记 display ’ LCD)。LCD 已從 TN-LCD、STN-LCD 發展到了 TFT-LCD。一些製造商又開始開發LpTS_LCD。 圖1是一種習知LCD面板。這種LCD面板100包括 一閘極驅動電路11〇、一資料驅動電路12〇、多條閘極線 (gatelme) 112、多條資料線（data line) 122、以及多個 畫素單元130。其中每個晝素單元13〇包括一電晶體132、 二電谷态134、以及一液晶元件136。當寫入資料（亦即， 當資料顯示在LCD面板1〇〇上）時，閘極驅動電路11〇 將使閘極線112從低電壓電位上升到高電壓電位以使電晶 體132導通。然後資料驅動電路120經由資料線122把資 料寫入電容器134。當寫入資料於電容器134之後，閘極 驅動電路110將使閘極線112從高電壓電位變爲低電壓電 位以使液晶元件136可繼續顯示此資料，直到下一資料被 寫入。但是，當LCD面板1〇〇發生非正常斷電時，資料仍 保留在電容器134中，如此就產生了殘影。 消除或減少殘影的習知方法是使電晶體132的I-V曲 6 1329852 P92152 13243twf.doc/e ==圖2所示）向左㈣，使此電晶體i32❸ i 132 〇v 時電日日體132仍可導通，以使儲存於雷 料可被釋放到資料線〗22上。 、 "σ 中的貧 但是，要得到較好的解析度， ;’因爲這也會影響到LCD面板二移曲1329852 P92152 13243twf.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to an afterimage erasing circuit, and in particular to a type suitable for charging power when an abnormal power failure occurs. An afterimage removal circuit for the display panel and the driver circuit. [Prior Art] Liquid crystal materials have been discovered in Europe, developed in the United States, and used in several fields. At present, many kinds of liquid crystal technologies have been widely used in displays, especially liquid crystal displays (display display 'LCD). LCD has evolved from TN-LCD and STN-LCD to TFT-LCD. Some manufacturers have begun to develop LpTS_LCD. Figure 1 is a conventional LCD panel. The LCD panel 100 includes a gate driving circuit 11A, a data driving circuit 12A, a plurality of gate lines 112, a plurality of data lines 122, and a plurality of pixel units 130. Each of the pixel units 13A includes a transistor 132, a second valley state 134, and a liquid crystal element 136. When data is written (i.e., when data is displayed on the LCD panel 1), the gate driving circuit 11 turns the gate line 112 from a low voltage potential to a high voltage potential to turn on the transistor 132. Data drive circuit 120 then writes the data to capacitor 134 via data line 122. After writing data to capacitor 134, gate drive circuit 110 will cause gate line 112 to change from a high voltage potential to a low voltage level so that liquid crystal element 136 can continue to display this data until the next data is written. However, when an abnormal power-off occurs in the LCD panel 1 , the data remains in the capacitor 134, and a residual image is generated. A conventional method for eliminating or reducing image sticking is to make the IV curve of the transistor 132 6 1329852 P92152 13243 twf.doc/e == shown in FIG. 2 to the left (four), so that the transistor i32 ❸ i 132 〇v 132 can still be turned on so that the stored material can be released onto the data line 22. , "poor in σ, but to get better resolution, 'because this will also affect the LCD panel second shift
=題方_在不影響LCD面板解析度=下因解此決I 【發明内容】 生非正常斷電時，儲;口顯示面板。當發 線的電Μ上升抑電㈣位使巧電荷將使閘極 通。這樣儲存在影像電荷儲存元件中思的tt70内的開關導 以減少或消除殘影。 中的衫像電荷將被釋放 本發明提供一種罝右& 括多個由閘極驅動電路和資^驅于動電示面板，其包 π。閘極驅動電路藉由笫—貝二驅之電路來驅動的畫素單 第-電壓使畫素單元導電屢和第二電愿而驅動，其中 號’而第二電壓使書辛^接收來自貧料驅動電路的信 件，其具有第-端與第路包括、電荷儲存元 第二端與第三端；以及元件，其具有第一端、 所驅動的資料線與 1關，其麵接於由資料驅動電 端乃疋接地。隔離元件 i 電何儲存兀件的第二 端耦接到電荷儲存元件的第 1329852 P92152 13243twf.doc/e 一端，而隔離元件的第二端耦接到第一電壓，以及 件的第三端耦接到第二電壓。當發生非正常斷電時，= 離7L件導通。開關適用根據施加於隔離元件 ' 二 其自身是否導通，且當發生非正常“ 在本發明的一實施例中，殘影消除電路又包括—二 體，其具有第-端與第二端，其中此二極體的第 = 電壓’而此二極體的第二端耦接到電荷儲存元件的 一本發明提供一種顯示單元的殘影消除電路，此 Μ 。包括多個由閘極驅動電路和資料驅動電路所驅動的== 二=閘極鶴電路是㈣壓與第二電壓來驅動1 素單1晝素單元導通以接收f料信號，且第二電壓使ί 包括，=阻ΐ晝素單元接收資料信號。殘影消除ΐί 雷、奋2 間及一殘影消除電路’由第—電厥二 晝素i元生非正常斷電時’輸出充電電力以使開關和 t發明另提供具有多個晝素單元的辭面板的 第乂，動電路包括：—電壓轉換器，其輸出第-電^1 : -閣極驅動電路，其根據第一與第二電壓= 條厂單;_多條開極線中的: - 電I使旦素早凡導通，而第二電壓使查表= The problem _ does not affect the LCD panel resolution = the next solution to this decision I [Summary] When the abnormal power is off, the storage; port display panel. When the power line of the transmitter rises and the power is suppressed (four), the charge will make the gate pass. This is stored in the tt70 of the image charge storage element to reduce or eliminate image sticking. The shirt-like charge will be released. The present invention provides a 罝 right & a plurality of gate drive circuits and a power-driven display panel, which includes π. The gate driving circuit drives the pixel single-voltage by the circuit of the 笫-Bei two-drive circuit to make the pixel unit conductive and the second electric drive are driven, wherein the second voltage makes the book sin ^ receive from the poor a letter of the material drive circuit having a first end and a second path, a second end and a third end of the charge storage element; and an element having a first end, the driven data line and the 1st switch, the surface of which is connected by The data drive terminal is grounded. The second end of the isolation element i is connected to one end of the 139852 P92152 13243 twf.doc/e of the charge storage element, and the second end of the isolation element is coupled to the first voltage, and the third end of the component is coupled Received a second voltage. When an abnormal power failure occurs, = 7L is turned on. The switch is adapted to be applied to the isolation element 'two, whether it is turned on itself, and when abnormality occurs." In an embodiment of the invention, the afterimage removal circuit further includes a two-body having a first end and a second end, wherein The second voltage terminal of the diode is coupled to the charge storage element. The invention provides a residual image erasing circuit for the display unit, and includes a plurality of gate driving circuits and The data driving circuit drives the == two = gate crane circuit is (four) voltage and the second voltage to drive the 1-cell single-cell unit to conduct to receive the f-signal, and the second voltage causes ί to include, = statin The unit receives the data signal. The afterimage is removed 雷ί, 奋 2 and an afterimage elimination circuit 'from the first-electron dioxin i-yuan abnormal power-off' output charging power to enable the switch and the t invention to provide The third circuit of the panel of the plurality of pixel units includes: a voltage converter, the output of the first-electrode: - the gate drive circuit, which is based on the first and second voltages = a factory order; In the open line: - The electric I turns the element on, and the second Press the look-up table
資料驅動電路’驅動多條資料線;多個“I #關耦接於一相應貧料線與一 ESD電路之間；以戈 8 1329852 P92J52 13243twf.doc/e 殘影消除電路，由第一雷m 則輸出充電電力以使查辛單-盘’而當發生非正當斷電時， 本發明乃是使開關導通。 電時，儲存在電荷館存元件d，路’當發生非正常斷 到足以使晝素單元和連接到SD ^使閘極線電壓上升 電位。如此，儲存在存電=開關導通的· 路徑’故可更=二導釋放影像電荷的接地 易懂爲下讓===特徵和優點能更明顯 明如下。 貫％例’並配合所附圖式，作詳細說 【實施方式】 圖3是根據本發明所提出的一實施例中，且 m其他相關電路的LCD面板，更於描述本： 明，百先’先描述晝素單元33Ge在此實施例中， 元330包括-開關元件332、一影像電荷儲存元件^^以 及-液晶元件336。開關元件332的第一端366耦接到 極線312。開關元件332的第二端368耦接到資料線η】。 開關元件332的第三端370耦接到影像電荷儲存元件幻4 的第一端372。影像電荷儲存元件334的第二端374則接 地。液晶元件330的一端耦接到影像電荷儲存元件334的 第一端372，而液晶元件330的另一端則接地。 雖然開關元件332繪示爲NM0S，但是熟悉此技蓺者 都明白PMOS、MOSFET或JFET都可用來形成此開^元 件 332。 1329852 P92152 13243twf.doc/eThe data driving circuit 'drives multiple data lines; multiple "I #off couplings between a corresponding lean line and an ESD circuit; to 8 8329852 P92J52 13243twf.doc/e afterimage removal circuit, by the first mine m then outputs the charging power to make the Chasing single-disk'. When the improper power-off occurs, the present invention turns on the switch. When the electricity is stored, it is stored in the charge storage element d, and the road 'is abnormally broken. Make the halogen unit and connect to SD ^ to increase the voltage of the gate line. Therefore, the path stored in the memory = switch is turned on. Therefore, the ground of the image charge can be more easily defined as the lower === feature. And the advantages can be more clearly as follows. The embodiment of the present invention is described in detail with reference to the accompanying drawings. FIG. 3 is an LCD panel of another related circuit according to an embodiment of the present invention. In the description of the present invention, the first element 366 of the switching element 332 is included in the embodiment. The element 330 includes a switching element 332, an image charge storage element, and a liquid crystal element 336. The first end 366 of the switching element 332 Coupled to the pole line 312. The second end 368 of the switching element 332 The third end 370 of the switching element 332 is coupled to the first end 372 of the image charge storage element 4. The second end 374 of the image charge storage element 334 is grounded. One end of the liquid crystal element 330 is coupled. To the first end 372 of the image charge storage element 334, and the other end of the liquid crystal element 330 is grounded. Although the switching element 332 is illustrated as NM0S, those skilled in the art will appreciate that PMOS, MOSFET or JFET can be used to form this ^Element 332. 1329852 P92152 13243twf.doc/e
參照圖3，電壓轉換器340把來自DC電壓源的電力 轉換爲兩個電壓VDD和VEE，其中電壓Vdd例如約爲12V， 電壓VEE例如約爲-2V。殘影消除電路3〇〇和閘極驅動電路 310耦接到電壓VDD和VEE。此外，閘極驅動電路31 〇根 據電壓VDD和VEE驅動至少一條閘極線312，且資料驅動 電路320驅動至少一條資料線322以傳送資料信號。 當DC電壓源提供電力給電壓轉換器34〇時，電壓轉 換器340給閘極驅動電路31〇提供高電壓VDD和低電壓 VEE。由於繪示於實施例中的開關元件332是NM〇s，故 而尚電壓VDD用來使開關元件332導通，而低電壓VEE 用來使開關元件332關閉。當畫素單元33〇要接收資料時， 閘極驅動電路310使用高電壓VDD以經由閘極線312使 開關元件332導通。當開關元件332導通之後，資料驅動 電路320可經由資料線322把資料寫入晝素單元33〇。當 寫入資料於晝素單元330之後，閘極驅動電路31〇提供低 ，壓VEE以使開關元件332關閉以阻止晝素單元33〇接收 資料。晝素單元330將把資料儲存在影像電荷儲存元件334 中，使液晶元件336能夠繼續顯示資料，直到下一資料被 寫入（亦即，開關元件332再次導通）。但是，者發生非 正常斷電時，資料仍被儲存在影像電荷儲存元件 如此就導致了殘影。 在本實施例中’殘影消除電路3⑻包括—隔離 3〇2、一二極體3〇4、以及一電荷儲存元件3〇6。 3〇2包括第一端360、第二端362、以及第三端: 體304包括第-端352和第二端354。電“存元件= 1329852 P92152 13243twf.doc/e 包括第一端356和第二端358。在本實施例中，隔離元件 302可以是p型M〇SFET或p型，但不局限於此。 電荷儲存元件306可以是一電容器，但不局限於此❶二極 ，304的第—端352耦接到電壓VDD，二極體3〇4的第二Referring to Figure 3, voltage converter 340 converts power from a DC voltage source to two voltages VDD and VEE, wherein voltage Vdd is, for example, about 12V, and voltage VEE is, for example, about -2V. The afterimage removal circuit 3A and the gate drive circuit 310 are coupled to the voltages VDD and VEE. In addition, the gate driving circuit 31 drives at least one gate line 312 according to the voltages VDD and VEE, and the data driving circuit 320 drives the at least one data line 322 to transmit the data signal. When the DC voltage source supplies power to the voltage converter 34, the voltage converter 340 supplies the gate drive circuit 31 with a high voltage VDD and a low voltage VEE. Since the switching element 332 shown in the embodiment is NM 〇 s, the voltage VDD is also used to turn on the switching element 332, and the low voltage VEE is used to turn the switching element 332 off. When the pixel unit 33 is to receive data, the gate driving circuit 310 uses the high voltage VDD to turn on the switching element 332 via the gate line 312. After the switching element 332 is turned on, the data driving circuit 320 can write the data to the pixel unit 33A via the data line 322. After writing the data to the pixel unit 330, the gate driving circuit 31 provides a low voltage VEE to turn off the switching element 332 to prevent the pixel unit 33 from receiving data. The pixel unit 330 will store the data in the image charge storage element 334 to enable the liquid crystal element 336 to continue to display data until the next data is written (i.e., the switching element 332 is again turned on). However, when an abnormal power failure occurs, the data is still stored in the image charge storage element, which results in image sticking. In the present embodiment, the afterimage erasing circuit 3 (8) includes - isolation 3 〇 2, a diode 3 〇 4, and a charge storage element 3 〇 6. 3〇2 includes a first end 360, a second end 362, and a third end: The body 304 includes a first end 352 and a second end 354. The electrical storage element = 1329852 P92152 13243 twf.doc/e includes a first end 356 and a second end 358. In the present embodiment, the isolation element 302 may be a p-type M 〇 SFET or a p-type, but is not limited thereto. The storage element 306 can be a capacitor, but is not limited to the second diode. The first terminal 352 of the 304 is coupled to the voltage VDD, and the second terminal of the diode 3〇4.
，354耦接到電荷儲存元件3〇6的第一端356。此外，電 存7〇件306的第二端358乃是接地。對於隔離元件3〇2 s^第一端360耦接到電荷儲存元件3〇6的第—端 而第二端耦接到電壓Vdd，以及第三端364執接 到電壓Vm。 ΑφΓ、電壓轉換器340提供電力給閘極驅動電路310時， 和雷Ϊ轉換4 同時也提供電壓VDD給隔離元件302 儲广何儲存①件3G6 ’分別使畴元件3〇2關、給電荷 兩仔凡件306充電。 壓-時，d據t發明所提出的—實施例中’閘極線的電 件30,ί參照圖4，當發生非正常斷電時，隔離元 導通。的電壓接近gv，因此隔離元件地 關如圖4所示地上升。於此同時，』 資料線=而334可釋放電荷到 但日，i.有效地減少或消除殘影。 且開關m知枝. 六'丨冰與一 ESD電路之 接到端子364，當發生非正常斷電時， 此來自：影:3 =時杜則資料驅動電路320關閉，因 被傳導到地。的電荷只可經由漏電流而 供1關姐或減少速度，本實施例提 333減:m抖線322與一勘電路之間， 則開 1329852 P92152 13243twf.doc/e 關333導通。在此實施例中，開關333使用—NM〇s來執 行操作。當電路正常工作時，電壓VEE被施加於ΝΜ〇 δ 3 3 3 的閘極，因而關閉此NMOS 333。但是，當發生非正常斷 電時，電荷儲存元件306釋放儲存於其中的電荷，使得端 子364的電壓升高，因此導通NMOS 333。然後，來自影 像電荷儲存元件334的電荷可經由ESD電路而接地。' 在此實施例中，二極體304是用於從二極體304之第 一端352流向二極體304之第二端354的電流。也就是說， 當電荷健存元件306放電時，電流僅從隔離元件302的第 一端360流向隔離元件302的第三端364，但電流不會流 經二極體304。當電壓轉換器340不提供電壓VDD時，將 導通隔離元件302。 一在本發明的一實施例中，電荷儲存元件306可以是顯 示器的電容器’而不必是一額外的電容器。 在本發明的另一實施例中，隔離元件的第一端 可到一大電阻器392以避免隔離元件3〇2被過大電流 ，，壞。此外，一 RC電路（圖3所示之電阻器394和電 容器396)可耦接到電壓轉換器34〇以確保電壓上升（如 上升到0.7V)，使電壓轉換器34〇可正常工作，且壓 VEE可維持穩定。 3 5疋根據本發明所提出的另一較佳實施例中，另一 種^影消除電路及其他相關電路。與圖3相比，隔離 403 是—N 型 M〇SFET，而不是 P 型 MOSFET，而 t ί ΐΓ 433是一p型mosfet。第—電壓（在此實施例 為VEE)耦接到閘極驅動電路410和二極體404的第一 12 1329852 P92152 13243twf.doc/e .电/变[在此貫施例中爲VDD)耦接到電阻哭 的第-=二端454輕接到電荷儲存元件^ ί Γ I 電荷經二極體404從電荷儲存元件406 j二因此，電荷儲存元件概㈣壓電位將與電屢卿 、電整電位幾乎相同。當電㈣換器不提 ^士 發生非正常斷電時，則電荷儲存元件梅㈣^立 為負，而隔離元件403之閘極端462的電 ^電位 元件403,且編 爲了提高殘影消除速度’本實施例提# 其耦接於資料線422與ESD電路之 s 3 5 子464，且當發生非正當斷# m 耦接到端 施例中，開關=it _開關433 °在此實 被施加於· 元件==存:ί中 近似-的電壓，因此 電荷儲存元件434的電荷可經由ESD電路而接地。影像 圖6是根據本發明所提出的一路而接地 方塊圖。_ 6，細肖除電路心二的 與ESD電路㈣之_ _ :=於貝jH線622 藝者能夠瞭解本發明。在此总施 ^以使热悉此技, 354 is coupled to the first end 356 of the charge storage element 3〇6. In addition, the second end 358 of the capacitor 306 is grounded. The first terminal 360 is coupled to the first terminal of the charge storage element 3〇6 and the second terminal is coupled to the voltage Vdd, and the third terminal 364 is coupled to the voltage Vm. When the voltage converter 340 supplies power to the gate driving circuit 310, it also supplies the voltage VDD to the isolation element 302 at the same time as the Thunder conversion 4, and stores 1 piece of 3G6' respectively, and the domain element 3〇2 is turned off, respectively. The piece 306 is charged. The voltage-time, d, according to the invention of the invention, the gate electrode of the embodiment 30, ί refers to Figure 4, when an abnormal power failure occurs, the isolation element is turned on. The voltage is close to gv, so the isolation element ground rises as shown in Figure 4. At the same time, the data line = and 334 can release the charge to the day, i. effectively reduce or eliminate the afterimage. And the switch m knows. The six '丨冰 and one ESD circuit are connected to the terminal 364. When an abnormal power failure occurs, this comes from: shadow: 3 = time, the data driving circuit 320 is turned off, and is transmitted to the ground. The charge can only be supplied to the Sister or reduce the speed via the leakage current. In this embodiment, 333 is subtracted: between the m-shake line 322 and a survey circuit, the open 1329852 P92152 13243 twf.doc/e 333 is turned on. In this embodiment, switch 333 uses -NM〇s to perform the operation. When the circuit is operating normally, the voltage VEE is applied to the gate of ΝΜ〇 δ 3 3 3 , thus turning off the NMOS 333. However, when an abnormal power failure occurs, the charge storage element 306 releases the charge stored therein, causing the voltage of the terminal 364 to rise, thereby turning on the NMOS 333. The charge from image charge storage element 334 can then be grounded via an ESD circuit. In this embodiment, the diode 304 is a current for flowing from the first end 352 of the diode 304 to the second end 354 of the diode 304. That is, when the charge-storing element 306 is discharged, current flows only from the first end 360 of the isolation element 302 to the third end 364 of the isolation element 302, but current does not flow through the diode 304. When voltage converter 340 does not provide voltage VDD, isolation element 302 will be turned on. In one embodiment of the invention, charge storage element 306 can be a capacitor' of the display and need not be an additional capacitor. In another embodiment of the invention, the first end of the isolation element can be brought to a large resistor 392 to prevent the isolation element 3〇2 from being subjected to excessive current, which is undesirable. In addition, an RC circuit (resistor 394 and capacitor 396 shown in FIG. 3) can be coupled to voltage converter 34 to ensure that the voltage rises (eg, rises to 0.7V), allowing voltage converter 34 to operate properly, and The pressure VEE can be kept stable. In another preferred embodiment of the present invention, another method is used to eliminate the circuit and other related circuits. Compared to Figure 3, isolation 403 is a -N type M〇SFET instead of a P-type MOSFET, and t ί 433 is a p-type mosfet. The first voltage (VEE in this embodiment) is coupled to the first 12 1329852 P92152 13243 twf.doc/e of the gate drive circuit 410 and the diode 404. The electrical/variable (VDD in this embodiment) coupling The first-second terminal 454 connected to the resistor is lightly connected to the charge storage element ^ Γ I charge from the charge storage element 406 j through the diode 404. Therefore, the charge storage element (four) piezoelectric position will be connected with the electric The electrical potential is almost the same. When the electric (four) converter does not mention that the abnormal power is off, the charge storage element Mei (4) is negative, and the electric potential element 403 of the gate terminal 462 of the isolation element 403 is edited to improve the afterimage elimination speed. 'This embodiment mentions that it is coupled to the data line 422 and the s 3 5 sub-464 of the ESD circuit, and when an improper break #m is coupled to the end embodiment, the switch =it_ switch 433 ° is actually Applied to the component == stored: ί approximates the voltage, so the charge of the charge storage element 434 can be grounded via the ESD circuit. Image Figure 6 is a block diagram of a grounding circuit in accordance with the present invention. _6, in addition to the circuit core two and the ESD circuit (four) _ _: = Yubei jH line 622 artists can understand the present invention. Always apply here to make this technology
過轉換來自π nr贵厂在此戶例中’電屋轉換器640通 轉換來自於DC電壓源的電力以提供兩麵VDD和VEE 1329852 P92152 13243twf.doc/e 給閘極驅動電路610。閘極驅動電路610根據來自電壓轉 換器640的電壓而經由閘極線612來決定導通或關閉晝紊 單元630。當晝素單元63〇導通時，此晝素單元63〇經由 資料線622而接收來自於資料驅動電路62〇的資料信號。 ^之，當晝素單元630關閉時，畫素單元630被禁止接吹 ，料線622上的資料信號。殘影消除電路6〇〇是用第一電 壓來充電，而此第一電壓用來使晝素單元63〇導通，且輪 出充電電力以經由閘極驅動電路61〇來使晝素單元63〇 ‘ 通二以及根據信號605而使開關624導通。開關624耦接 於資料線622與ESD電路65〇之間，其中當驅動電路正常 工作時，則信號605使開關624關閉，而當發生斷電時， 信號605使開關624導通。 。。總之，本發明所提出的殘影消除電路將不必調整晝素 羊兀的I-V曲線，故此殘影消除電路不會影響顯示器 路的性能：當發生斷電時，儲存在電荷儲存元件巾的電荷 將^晝素ΐ元和減到資料線的開畴導通。因此，儲存 在影像電荷儲存元件巾的影像電荷將轉朗ESD亓杜 而接地，從而消除殘影。 牛 雖然本發明已以較佳實施例揭露如上，鈇 =本發明，任何熟習此技藝者，在不脫離;發 :乾圍内，當可作些許之更動與潤飾，因此本發明之：: 把圍當視後附之申請專利範圍所界定者為準。 ’、遂 【圖式簡單說明】 圖1是一種習知LCD面板。 圖2是薄膜電晶體的ι·ν曲線。 14 1329852 P92152 13243twf.doc/e 圖3是根據本發明所提出的一實施例中，具有一種殘 影消除電路及其他相關電路的LCD面板。 圖4是根據本發明所提出的一實施例中，閘極線的電 壓-時間曲線。 圖5是根據本發明所提出的另一實施例中，具有另一 種殘影消除電路及其他相關電路的LCD面板。 圖6是根據本發明所提出的一實施例中’其驅動電路 的方塊圖。 【主要元件符號說明】 100 : LCD 面板 110 :閘極驅動電路 112 :閘極線 120 :資料驅動電路 122 :資料線 130 :晝素單元 132 :電晶體 134 :電容器 136 :液晶元件 140 :電壓轉換器 300 :殘影消除電路 302 :隔離元件 304 :二極體 306 :電荷儲存元件 310 :閘極驅動電路 312 :閘極線 320 :資料驅動電路 15 1329852 P92152 13243twf.doc/e 322 :資料線 330 :畫素單元 332 :開關元件 333 :開關 334 :影像電荷儲存元件 336 :液晶元件 340 :電壓轉換器 352 :第二端 354 :第三端 356 :第一端 358 :第二端 360 :第一端 362 :第二端 364 :第三端 366 :第一端 368 :第二端 370 :第三端 372 :第一端 374 :第二端 392、394 :電阻器 396 :電容器 400 :殘影消除電路 403 :隔離元件 404 :二極體 406 :電荷儲存元件 16 1329852 P92152 13243twf.doc/e 410 :閘極驅動電路 422 :資料線 432、433 :開關元件 434 :影像電荷儲存元件 440 :電壓轉換器 452 :第一端 454 :第二端 456 :第一端 462 :閘極端 494 :電阻器 600 :殘影消除電路 605 :信號 610 :閘極驅動電路 612 :閘極線 620 :資料驅動電路 622 :資料線 624 :開關 630 :畫素單元 640 :電壓轉換器 650 : ESD 電路 17Over-conversion from π nr in this case, the electric house converter 640 turns the power from the DC voltage source to provide two-sided VDD and VEE 1329852 P92152 13243 twf.doc/e to the gate drive circuit 610. The gate driving circuit 610 determines to turn on or off the turbulence unit 630 via the gate line 612 based on the voltage from the voltage converter 640. When the pixel unit 63 is turned on, the pixel unit 63 receives the data signal from the data driving circuit 62A via the data line 622. ^, when the pixel unit 630 is turned off, the pixel unit 630 is prohibited from picking up the data signal on the feed line 622. The afterimage erasing circuit 6 is charged with a first voltage, and the first voltage is used to turn on the pixel unit 63, and the charging power is turned on to cause the pixel unit 63 to pass through the gate driving circuit 61. Pass 2 and turn on switch 624 according to signal 605. Switch 624 is coupled between data line 622 and ESD circuit 65A, wherein signal 605 causes switch 624 to turn off when the drive circuit is operating normally, and switch 624 turns "on" 624 when a power outage occurs. . . In summary, the afterimage removal circuit proposed by the present invention does not need to adjust the IV curve of the alizarin alpaca, so the afterimage removal circuit does not affect the performance of the display path: when a power failure occurs, the charge stored in the charge storage element towel will ^ The prime element is reduced to the domain conduction of the data line. Therefore, the image charge stored in the image charge storage device will be grounded to eliminate the residual image. Although the present invention has been disclosed in the preferred embodiments as above, 鈇 = the present invention, any person skilled in the art, without departing from; hair: dry circumference, when some changes and retouching can be made, therefore the present invention: The scope defined in the patent application scope is subject to the definition of patent application. ‘, 遂 [Simplified illustration of the drawings] Fig. 1 is a conventional LCD panel. Figure 2 is a ι·ν curve of a thin film transistor. 14 1329852 P92152 13243 twf.doc/e Figure 3 is an LCD panel having a ghost removal circuit and other associated circuitry in accordance with an embodiment of the present invention. Figure 4 is a graph showing the voltage-time curve of a gate line in accordance with an embodiment of the present invention. Figure 5 is an LCD panel with another afterimage removal circuit and other associated circuitry in accordance with another embodiment of the present invention. Figure 6 is a block diagram of a drive circuit thereof in accordance with an embodiment of the present invention. [Main component symbol description] 100 : LCD panel 110 : gate drive circuit 112 : gate line 120 : data drive circuit 122 : data line 130 : halogen unit 132 : transistor 134 : capacitor 136 : liquid crystal element 140 : voltage conversion Device 300: afterimage removal circuit 302: isolation element 304: diode 306: charge storage element 310: gate drive circuit 312: gate line 320: data drive circuit 15 1329852 P92152 13243twf.doc/e 322: data line 330 : pixel unit 332: switching element 333: switch 334: image charge storage element 336: liquid crystal element 340: voltage converter 352: second end 354: third end 356: first end 358: second end 360: first End 362: second end 364: third end 366: first end 368: second end 370: third end 372: first end 374: second end 392, 394: resistor 396: capacitor 400: afterimage removal Circuit 403: isolation element 404: diode 406: charge storage element 16 1329852 P92152 13243twf.doc / e 410: gate drive circuit 422: data line 432, 433: switching element 434: image charge storage element 440: voltage converter 452: first end 454: second end 456 : first end 462 : gate terminal 494 : resistor 600 : afterimage removal circuit 605 : signal 610 : gate drive circuit 612 : gate line 620 : data drive circuit 622 : data line 624 : switch 630 : pixel unit 640 : Voltage Converter 650 : ESD Circuit 17