1329776 99-7-16 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晝素陣列結構及其製造方法，且 特別是有關於一種具有高顯示開口率的畫素陣列結構及其 製造方法。 【先前技術】 由於顯不器的需求與日遽增’加上近年來綠色環保概 念的興起’具有南畫質、空間利用效率佳、低消耗功率、 無輻射等優越特性之薄膜電晶體液晶顯示器（thin film transistor liquid crystal display, TFT-LCD)已逐漸成為顯示 器市場之主流。為了滿足使用者的需求，薄瞑電晶體液晶 顯示器的性能不斷朝向高對比(high contrast ratio)、無灰階 反轉(no gray scale inversion)、色偏小（little color shift)、亮 度高(high luminance)、高色彩豐富度、高色飽和度、快速 反應、顯示畫面穩定與廣視角等特性發展。 一般而言’薄膜電晶體液晶顯示器主要由分別配置有 晝素陣列與彩色濾光陣列的兩基板以及配置於此兩基板間 的液晶層所組成。圖1繪示為習知之晝素陣列結構的局部 示意圖。晝素陣列結構1〇〇包括多條掃描線102、多條資 料線104以及與這些掃描線1〇2、資料線104電性連接的 多個晝素結構110。掃描線102與資料線104相交而圍成 多個晝素區P (圖1僅繪示一個），且晝素結構110配置於 畫素區P中。晝素結構11〇包括主動元件112與畫素電極 114。主動元件112電性連接其中一條掃描線1〇2與其中一 5 1329776 99-7-16 條賢料線104,而畫素電極114 另外，晝素陣列結構100更包括主動元件m。 其與畫素電極114構成儲存電下電極m， 影像之穩定。处料電容結構m顯示 屬線所組成，而可能影響畫素Ϊ構^大夕由大面積的金 此，：存電容下電極120多配 口率。因 實際上，儲存電容下雷 一素周邊。 相同媒層製作，所描線1〇2以 ;Τ〇;=Γ良率’避免館存電容：=掃: 提高背光_發光效液晶顯視科，則必須 素_===的顯示亮度。因此，畫 素結構110顯示畫面的穩定性又;：了維持晝 口率’甚至進-步降低能源的耗費，必須對‘知 列結構1GG進行改良。 胃纟腳s知的晝素陣 【發明内容】 構的供—種畫素陣舰構，以提昇晝素陣列結 本發明另提供—種晝素陣列結構的製造方法，以 j陣列轉的製程良率錢晝鱗赌有高顯示開 本發明提出-種畫素陣列結構，包括多條掃描線、多 6 1329776 99-7-16 條^料線以及多個畫素結構。掃描線與資料線圍出多個晝 素區’而各畫素結構電性連接所對應的掃描線與資料線Γ 各晝素結構位於所對應的畫素區内。各晝素結構包括一主 ，兀件、一電性連接主動元件之晝素電極以及一儲存電 容。儲存電容下電極配置於晝素區周邊並與晝素電極部分 重疊以構_存電容。儲存電容下電極包括鄰近資料線的 至少一第一線段以及鄰近掃描線的至少一第二線段。第一 線段與第二線段為不同膜層且第一線段與鄰近之其中一資 料線為不同膜層而第二線段與鄰近之其中一掃描線為不同 膜層。 本發明另提出一種畫素陣列結構的製造方法，包括下 列步驟。在一基板上形成一第一金屬層，第一金屬層包括 多個閘極、多條掃描線與多個第一線段。閘極與掃描線連 接，而第一線段與掃描線分離。接著，於基板上依序形成 一閘絕緣層以及一半導體層，且閘絕緣層覆蓋第一金屬 層。然後，移除部份閘絕緣層以及部份半導體層以形成一 圖案化半導體層以及多個接觸窗。圖案化半導體層位於閘. 極上方而接觸窗暴露出第一線段之末端。隨之，於基板上 形成一第二金屬層。第二金屬層包括鄰近掃描線之多個第 二線段、鄰近第一線段之多條資料線、連接資料線之多個 源極以及多個汲極。資料線與掃描線相交而圍成多個畫素 區。源極與汲極位於閘極上方。第二線段藉由接觸窗電性 連接第一線段以形成多個儲存電容下電極，其中儲存電容 下電極位於晝素區周邊。 7 1-329776 99-7-16 段，闕料料電容下不同線 體绫路亦A 各下電極的各線段與相鄰的掃描與資料導 本發明之畫素陣列結構及其 的情形H ^ 不易與鄰近的線路發生短路 有較高的良i。另外列結構及_^^法具 防止短拉66恭4 本發月之1素陣列結構中不需為了 維持h 66 ί而使儲存電容Tf極與其_導體線路間 的顯“:。’本發明之畫素陣列結構具有較高 為，本發明之上述和其他目的、特徵和優點能更明顯 明如下。文特舉較佳實施例，並配合所附圖式，作詳細說 【實施方式】 圖2為本發明之—實施例之晝素陣列結構之示意圖。 ^照圖2’晝素陣列結構包括多條掃描線2G2、多條 資以及多個畫素結構21G。掃描線2()2與資料線 相父，並圍出多個晝素區P。晝素結構21〇則配置於 畫素區P中。各個畫素結構210包括主動元件212、畫素 電，2M以及儲存電容。主動元件212與對應的掃描線旦2〇2 及資料線204電性連接，而晝素電極214電性 件212» 期^ —儲存電容下電極216配置於晝素區P周邊，且儲存電 ^下電極216與晝素電極m部分重疊以構成儲存電容。 當畫素結構210進行顯示時’儲存電容有助於維持晝素電 8 99-7-16 極214的顯示電壓。因此，應用晝素陣列結構2〇〇的液晶 顯示器所顯示的影像較為穩定，也就是顯示影像中不會發 生殘影或是閃爍的現象。然而，儲存電容下電極216由不 透光的金屬材質製成，所以儲存電容下電極216的配置可 月b會影響晝素結構210的顯示開口率。為解決上述問題， 本發明在此提出以不同膜層分段製作儲存電容下電極 216’使得儲存電容下電極216與鄰近的線路不易發生短路 現象。如此一來，可縮短儲存電容下電極216與鄰近的線 路間的距離以提南顯示開口率，更進一步提高晝素陣列結 構200的製程良率。 具體來說’儲存電容下電極216包括第一線段216A 與第二線段216B。第一線段216A與第二線段216B由不 同膜層所組成。第一線段216A鄰近資料線204配置，而 第二線段216B鄰近掃描線202配置。另外，第一線段216A 與其鄰近的資料線204為不同的膜層而第二線段216B與 其鄰近的掃描線202為不同的膜層。以本實施例而言，儲 存電容下電極216之外形例如為Πί，且儲存電容下電極 216包括二個第一線段216A，而第二線段216B的兩端分 別與此二個第一線段216A交疊。此外，畫素結構21〇中 更包括有位於第一線段216A與第二線段216B交疊處的接 觸窗218 ’且第一線段216A與第二線段216B藉由接觸窗 218電性連接。 當然’本發明之儲存電容下電極216並不限定於门型 外形。在其他實施例中，儲存電容下電極216例如不與主 9 1329776 99-7-16 動元件212相交或重疊而構成接近C字型圖案，圍繞於畫 素區P周邊大部分區域。舉例而言，儲存電容下電極216 例如配置於畫素區P的四周，且具有一對應主動元件212 的開口部位。 圖3繪示為圖2之畫素結構210的上視示意圖。請參 照圖2與圖3,在畫素結構210中，第二線段216B與掃描 線202由不同膜層製作而成。由上視圖觀之，即使縮短第 二線段216B與掃描線202間的距離d，第二線段216B與 掃描線202間仍不易發生短路的問題。因此，相較於習知 的晝素結構110而言’儲存電容下電極216的第二線段 216B部分可以更靠近掃描線202，因而有助於增加晝素結 構210的顯示開口率。此外，第一線段216A與資料線206 亦為不同膜層，因此也有助於提昇晝素結構21〇的顯示開 口率。 根據實際測試結果發現，與習知畫素結構110比較， 本實施例之晝素結構210有較高的顯示開口率（依晝素設 計而定，一般至少大於1%)，所以在相同的光源條件下， 應用晝素結構210之液晶顯示面板也具有較高的光線穿透 度。因此，畫素結構210的設計可以提升背光源的光線使 用率，因而有助於降低背光源的能源耗費。換言之，應用 畫素結構210的液晶顯示器不需搭配高亮度的背光模組或 是昂責的增亮骐就可以達到足夠的顯示亮度，以進一步節 省成本。 圖4A〜圖4D繪示為圖2之晝素陣列結構沿剖線AA, 10 1329776 99-7-16 的製作方法剖面圖。請先同時參照圖2與圖4A，在一基板 400上形成一第一金屬層410。第一金屬層410包括一 ^極 212A、一掃描線202以及一第一線段216Α»閘極212A與 掃描線202連接，而第一線段216A遠離掃描線202。實^ 上，第一線段216A與掃描線202互不接觸或重疊，且第 線4又216A的延伸方向與掃描線202的延伸方向相交。 對應於各晝素區P中，第一線段216A例如會與相鄰畫素 區P的第一線段216A連接》 接著，請同時參照圖2與圖4B，於基板400上依序 形成一閘絕緣層420以及一圖案化半導體層43〇，且閘絕 緣層420覆蓋閘極212A。此外，閘絕緣層420上具有一接 觸窗218。圖案化半導體層43〇位於閘極212A上方，而接 觸窗218暴露出第一線段216A之末端。 然後’請同時參照圖2與圖4C，於基板400上形成 一第二金屬層440。第二金屬層44〇包括鄰近掃描線2〇2 之一第二線段216B、鄰近第一線段216A之一資料線204、 連接資料線204之一源極212B以及一汲極212C。源極 212B與汲極212C位於閘極212A上方之圖案化半導體層 430上。第二線段216B藉由接觸窗218電性連接第一線段 216A以形成儲存電容下電極216，其中儲存電容下電極 216位於晝素區p周邊。 由於’相鄰近的掃描線202與第二線段216B分別為 第一金屬層410與第二金屬層44〇，其中第一金屬層41〇 與第二金屬層440之間至少配置有閘絕緣層42〇。因此， 11 1329776 99-7-16 Γ線近的第二線段216B不容易發生短路的現 象，而使晝素陣列結構200具有較高的製程良率。掃描線 202與鄰近的第二線段216B之間的距離可以較f知晝素 結構11G之設計更為縮短’以增加畫素陣列結構遍^顯 π開口率。此外’資料線2〇4與相鄰近的第'線段216八 也是不同的金屬層，所以也具有上述之優點。 再者’請同時參照圖2與圖4D，於基板·上形成 -保護層450以覆蓋第二金屬層44()，並於保護層45〇上 形成多個晝素電極2…晝素電極214電性連接沒極21兀 且畫素電極214之邊緣與儲存電容下電極216實質上部分 ^ ’以構成儲存電容。如此，晝素陣列結構200即製作 在本實施例中，接觸窗218與圖案化半導體層43〇例 如是使關5所示之半透光罩進雜㈣程而形成的。請 同時參照圖4D與參照圖5,半透光罩篇具有多個不同透 光度的透光區T。對應於單一晝素區p中，透光區T1對應 於接觸窗218上方’透光區T2對應於圖案化半導體層43〇 上方，而透光區T3則位於其他區域中。詳細而言，形成 圖案化半導體層430以及接觸窗218之方法如圖6A〜圖6E 所繪示。 首先，清參照圖6A，於基板400上依序形成閘絕緣 層420、半導體層432以及光阻材料層（未繪示）。同時，使 用半透光罩500將光阻材料層（未繪示）圖案化，而形成一 圖案化光阻層610。閘絕緣層420與半導體層432覆蓋第 12 99-7-16 =屬層41卜在本實施例中，半導體層43 ㈣層436。接雜非晶梦= 當中成方式例如疋進行摻雜製程以將摻質摻入非晶石夕材料 =====二= 二且層⑽具有至少一開口 612 =先 區域6工4與開口 612之外的 祕614以及第一 位置對應於第—線段216第一£域616 °開口 612的 閘極212A卜古。w 末端，第一區域614則對應於 之屋序士 ，圖案化光阻層610在第一區域614 之厚度大於在第二區域616的厚度。 然後’請參照圖6B，移险間σ & ^^ s 導體層432以及間絕綾屉4fn 612所暴露出來之半 例如是進行-侧製程而形成接觸窗218。此步驟 層极以及閑絕的半導體 二二區域616的圖案化★阻層61〇可 3 = 體層432以及閘絕緣層㈣以避免祕=/、下方之+導 化弁參照圖叱，移除第二區域㈣之部分圖荦 =層：此步驟例如是進行一 』圖： Γ區域616之部分圖案化光阻層⑽具有= 度，而第一區域014之部分圄垒A u 八啕衩居的与 厚度。所以，第二區垃^ 化光阻層610具有較厚的 °w 之部分圖案化光阻層610在灰 ^29776 99-7-16 化製程中被完全移除時，第一區域614之 物仍有部份未被移除，以在後續㈣作為^罩化之先用阻 八隨之，請參照圖6D與圖6E，利用第一區域614 i圖ΐίί阻層610為罩幕，移除部份半導體層432。之 ’將第-區域214的圖案化光阻層51〇移除可 層430。第二區域616中的半導體層432 3 被移除，而僅留下位於閘極212A上方 =二不需以不同的光罩就可:完 因此有助於節省購買以及製 =罩之成本。當然’在不同的製程設計之下，本發 2除以不同的光罩在不同的_製程中分別形成 218與圖案化半導體層430。 ^騎’本發明之畫料躲構及其製造方法中， 思存電谷下電極的各個線段與鄰近的金屬線路為不同金 i或=途儲存電容下電極與鄰近的金屬線路，例如掃= 之線之間不易發生短路的現象。也就是說，本發明 素陣列結構及其製造方法具有較高的製程良率人另 ，儲存電容下電極與鄰近的金屬線路間不易發生短路， =而儲存電容下電極與鄰近的掃描線或資料線之間的距離 可以縮短，以有助於提高晝素結構的顯示開口率。簡言 ===高製程良率與高顯示開口率的晝素陣列0結°構及 ，然本發明已以較佳實施例揭露如上，然其並非用以 疋發明，任何所屬技術領域中具有通常知識者，在不 1329776 99-7-16 脫離本發明之精神和範圍内’當可作些許之更動 ， 因此本㈣之保護範圍當視_之_請專概_ 為準。 【圖式簡單說明】 圖1緣示為習知之晝素陣列結構的局部示意圖。 圖2為本發明之-實施例之畫素陣列結構之示意圖。 圖3繪示為圖2之晝素結構的上視示意圖。 圖4A〜® 4时示為圖2之畫素陣列結構沿剖線aa， 的製作方法剖面圖。 圖5繪示為本發明之一實施例之半透光罩的示意圖。 圖6A〜圖6E緣示圖2之晝素陣列結構的圖案 體層以及接觸窗之製造方法。 〃 【主要元件符號說明】 100、200 :畫素陣列結構 102、202 :掃描線 104、204 :資料線 110、210 :畫素結構 112、212 :主動元件 114、214 :晝素電極 120、216:儲存電容下電極 212A :閘極 212B :源極 212C :汲極 216A :第一線段 1329776 99-7-16 216B:第二線段 218 :接觸窗 400 :基板 410 :第一金屬層 420 :閘絕緣層 430 :圖案化半導體層 432 :半導體層 434:未摻雜非晶矽層 436 :摻雜非晶矽層 440 :第二金屬層 450 :保護層 500 :半透光旱 610 :圖案化光阻層 612:開口 614 :第一區域 616 :第二區域 A-A’ ：剖線 . P :晝素區 T、ΤΙ、T2、T3 :透光區 16BACKGROUND OF THE INVENTION 1. Field of the Invention Its manufacturing method. [Prior Art] Due to the demand for the display device and the increase in the future, plus the rise of the concept of green environmental protection in recent years, it has a thin film transistor liquid crystal display with superior characteristics such as south image quality, good space utilization efficiency, low power consumption, and no radiation. (Thin film transistor liquid crystal display, TFT-LCD) has gradually become the mainstream of the display market. In order to meet the needs of users, the performance of thin-film LCD displays continues to be high contrast ratio, no gray scale inversion, little color shift, and high brightness. Highlights, high color richness, high color saturation, fast response, stable display and wide viewing angle. In general, a thin film transistor liquid crystal display mainly consists of two substrates each having a halogen array and a color filter array, and a liquid crystal layer disposed between the substrates. Figure 1 is a partial schematic view of a conventional halogen array structure. The pixel array structure 1 includes a plurality of scan lines 102, a plurality of data lines 104, and a plurality of pixel structures 110 electrically connected to the scan lines 1 and 2 and the data lines 104. The scan line 102 intersects the data line 104 to form a plurality of pixel regions P (only one is shown in FIG. 1), and the pixel structure 110 is disposed in the pixel region P. The halogen structure 11 includes an active element 112 and a pixel electrode 114. The active component 112 is electrically connected to one of the scan lines 1〇2 and one of the 5 1329776 99-7-16 sage lines 104, and the pixel electrode 114 additionally includes the active element m. It forms a storage electric lower electrode m with the pixel electrode 114, and the image is stable. The material capacitor structure m shows the composition of the genus line, which may affect the pixel structure. The large area of gold is used for the large area. Because in fact, the storage capacitor is under the ray. The same medium layer is produced, and the line drawn is 1〇2; Τ〇;=Γ yield 避免 avoids the storage capacitor: = Sweep: Improve the backlight _ luminescence effect liquid crystal display, then the display brightness of _===. Therefore, the pixel structure 110 displays the stability of the picture; the maintenance rate is maintained, and even the energy consumption of the energy source must be improved.昼 阵 s s 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 The yield of the money has a high display. The present invention proposes a pixel array structure comprising a plurality of scanning lines, a plurality of 6 1329776 99-7-16 lines, and a plurality of pixel structures. The scanning line and the data line enclose a plurality of pixel regions, and the scanning lines and the data lines corresponding to the electrical connection of the pixel elements are located in the corresponding pixel regions. Each of the pixel structures includes a main body, a component, a halogen electrode electrically connected to the active component, and a storage capacitor. The storage capacitor lower electrode is disposed around the halogen region and overlaps the halogen electrode portion to form a capacitor. The storage capacitor lower electrode includes at least a first line segment adjacent to the data line and at least a second line segment adjacent to the scan line. The first line segment and the second line segment are different film layers and the first line segment and the adjacent one of the data lines are different film layers and the second line segment and the adjacent one of the scanning lines are different film layers. The present invention further provides a method of fabricating a pixel array structure comprising the following steps. A first metal layer is formed on a substrate, and the first metal layer includes a plurality of gates, a plurality of scan lines and a plurality of first line segments. The gate is connected to the scan line, and the first line segment is separated from the scan line. Then, a gate insulating layer and a semiconductor layer are sequentially formed on the substrate, and the gate insulating layer covers the first metal layer. Then, a portion of the gate insulating layer and a portion of the semiconductor layer are removed to form a patterned semiconductor layer and a plurality of contact windows. The patterned semiconductor layer is located above the gate of the gate and the contact window exposes the end of the first line segment. A second metal layer is then formed on the substrate. The second metal layer includes a plurality of second line segments adjacent to the scan line, a plurality of data lines adjacent to the first line segment, a plurality of sources connected to the data lines, and a plurality of drains. The data line intersects the scan line to form a plurality of pixel regions. The source and drain are above the gate. The second line segment is electrically connected to the first line segment through the contact window to form a plurality of storage capacitor lower electrodes, wherein the storage capacitor lower electrode is located around the pixel region. 7 1-329776 99-7-16, the different line body of the 阙 material capacitor is also the line segment of each lower electrode and the adjacent scanning and data guides of the pixel array structure of the invention and its situation H ^ It is not easy to have a short circuit with a short circuit in the adjacent line. In addition, the column structure and the _^^ method prevent the short pull 66. The present invention is not required to maintain the h 66 ί and the storage capacitor Tf pole and its _ conductor line. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 2 is a schematic diagram of a structure of a halogen array according to an embodiment of the present invention. 2. The pixel array structure includes a plurality of scanning lines 2G2, a plurality of elements, and a plurality of pixel structures 21G. The scanning line 2() 2 and The data line is the father and encloses a plurality of pixel regions P. The halogen structure 21〇 is disposed in the pixel region P. Each pixel structure 210 includes an active element 212, a pixel power, 2M, and a storage capacitor. 212 is electrically connected to the corresponding scanning line 2 2 and the data line 204, and the halogen electrode 214 is electrically connected to the periphery of the pixel region P, and the storage electrode is disposed. 216 is partially overlapped with the halogen electrode m to constitute a storage capacitor. When the pixel structure 210 is performed When displaying, the 'storage capacitor helps to maintain the display voltage of the halogen battery 8 99-7-16 pole 214. Therefore, the image displayed by the liquid crystal display using the halogen array structure is stable, that is, the display image is not There is a phenomenon of image sticking or flickering. However, the storage capacitor lower electrode 216 is made of an opaque metal material, so the arrangement of the storage capacitor lower electrode 216 may affect the display aperture ratio of the halogen structure 210. To solve the above problems, the present invention proposes to fabricate the storage capacitor lower electrode 216' with different film layers so that the storage capacitor lower electrode 216 and the adjacent circuit are less prone to short circuit. Thus, the storage capacitor lower electrode 216 can be shortened and adjacent. The distance between the lines shows the aperture ratio in the south, and further improves the process yield of the pixel array structure 200. Specifically, the storage capacitor lower electrode 216 includes a first line segment 216A and a second line segment 216B. The first line segment The 216A and the second line segment 216B are composed of different film layers. The first line segment 216A is disposed adjacent to the data line 204, and the second line segment 216B is disposed adjacent to the scan line 202. In addition, the first The segment 216A is a different film layer from its adjacent data line 204 and the second line segment 216B is a different film layer from its adjacent scan line 202. In this embodiment, the storage capacitor lower electrode 216 is shaped as, for example, Πί, and stored. The capacitor lower electrode 216 includes two first line segments 216A, and two ends of the second line segment 216B overlap the two first line segments 216A, respectively. Further, the pixel structure 21〇 further includes a first line segment. The contact window 218 ′ at the intersection of the 216A and the second line segment 216B and the first line segment 216A and the second line segment 216B are electrically connected by the contact window 218. Of course, the storage capacitor lower electrode 216 of the present invention is not limited to the gate type. shape. In other embodiments, the storage capacitor lower electrode 216, for example, does not intersect or overlap with the main 9 1329776 99-7-16 moving element 212 to form a near C-shaped pattern that surrounds a substantial portion of the perimeter of the pixel region P. For example, the storage capacitor lower electrode 216 is disposed, for example, around the pixel region P and has an opening portion corresponding to the active device 212. 3 is a top plan view of the pixel structure 210 of FIG. 2. Referring to FIG. 2 and FIG. 3, in the pixel structure 210, the second line segment 216B and the scan line 202 are made of different film layers. From the top view, even if the distance d between the second line segment 216B and the scanning line 202 is shortened, the problem of short circuit between the second line segment 216B and the scanning line 202 is less likely to occur. Therefore, the portion of the second line segment 216B of the storage capacitor lower electrode 216 may be closer to the scanning line 202 than the conventional halogen structure 110, thereby contributing to an increase in the display aperture ratio of the pixel structure 210. In addition, the first line segment 216A and the data line 206 are also different film layers, and thus also contribute to the display opening ratio of the halogen structure 21〇. According to the actual test results, compared with the conventional pixel structure 110, the halogen structure 210 of the embodiment has a higher display aperture ratio (depending on the design of the element, generally at least greater than 1%), so the same light source is used. Under the condition, the liquid crystal display panel using the halogen structure 210 also has high light transmittance. Therefore, the pixel structure 210 is designed to increase the light usage of the backlight, thereby helping to reduce the energy cost of the backlight. In other words, the liquid crystal display using the pixel structure 210 can achieve sufficient display brightness without the need for a high-brightness backlight module or an acclaimed brightening , to further save costs. 4A-4D are cross-sectional views showing the fabrication method of the pixel array structure of FIG. 2 along the line AA, 10 1329776 99-7-16. Referring to FIG. 2 and FIG. 4A simultaneously, a first metal layer 410 is formed on a substrate 400. The first metal layer 410 includes a cathode 212A, a scan line 202, and a first line segment 216, the gate 212A is connected to the scan line 202, and the first line segment 216A is away from the scan line 202. Actually, the first line segment 216A and the scanning line 202 do not contact or overlap each other, and the extending direction of the first line 4 216A intersects with the extending direction of the scanning line 202. Corresponding to each of the pixel regions P, the first line segment 216A is connected to the first line segment 216A of the adjacent pixel region P, for example. Next, please refer to FIG. 2 and FIG. 4B simultaneously, and sequentially form a substrate 400. The gate insulating layer 420 and a patterned semiconductor layer 43 are covered, and the gate insulating layer 420 covers the gate 212A. In addition, the gate insulating layer 420 has a contact window 218 thereon. The patterned semiconductor layer 43 is located above the gate 212A, and the contact window 218 exposes the end of the first line segment 216A. Then, please refer to FIG. 2 and FIG. 4C simultaneously to form a second metal layer 440 on the substrate 400. The second metal layer 44A includes a second line segment 216B adjacent to the scan line 2〇2, a data line 204 adjacent to the first line segment 216A, a source 212B connecting the data line 204, and a drain 212C. Source 212B and drain 212C are located on patterned semiconductor layer 430 over gate 212A. The second line segment 216B is electrically connected to the first line segment 216A via the contact window 218 to form a storage capacitor lower electrode 216, wherein the storage capacitor lower electrode 216 is located around the pixel region p. Since the adjacent scan lines 202 and the second line segments 216B are the first metal layer 410 and the second metal layer 44, respectively, at least the gate insulating layer 42 is disposed between the first metal layer 41 and the second metal layer 440. Hey. Therefore, 11 1329776 99-7-16 The second line segment 216B near the twist line is not prone to short circuit, and the halogen array structure 200 has a high process yield. The distance between the scan line 202 and the adjacent second line segment 216B can be made shorter than that of the design of the pixel structure 11G to increase the aperture ratio of the pixel array structure. In addition, the data line 2〇4 and the adjacent ''line segment 216' are also different metal layers, so they also have the above advantages. Furthermore, please refer to FIG. 2 and FIG. 4D simultaneously, a protective layer 450 is formed on the substrate to cover the second metal layer 44 (), and a plurality of halogen electrodes 2 are formed on the protective layer 45. The electrical connection is not poled 21 and the edge of the pixel electrode 214 and the storage capacitor lower electrode 216 are substantially partially formed to constitute a storage capacitor. Thus, the halogen array structure 200 is formed in the present embodiment, and the contact window 218 and the patterned semiconductor layer 43 are formed, for example, by the half-transparent cover shown in the off-state 5. Referring to FIG. 4D and FIG. 5 simultaneously, the translucent cover has a plurality of transparent regions T of different transmittances. Corresponding to the single halogen region p, the light transmitting region T1 corresponds to the upper side of the contact window 218. The light transmitting region T2 corresponds to the upper portion of the patterned semiconductor layer 43A, and the light transmitting region T3 is located for other regions. In detail, the method of forming the patterned semiconductor layer 430 and the contact window 218 is as shown in Figs. 6A to 6E. First, referring to FIG. 6A, a gate insulating layer 420, a semiconductor layer 432, and a photoresist layer (not shown) are sequentially formed on the substrate 400. At the same time, a photoresist layer (not shown) is patterned using the translucent cover 500 to form a patterned photoresist layer 610. The gate insulating layer 420 and the semiconductor layer 432 cover the 12th 99-7-16 = genus layer 41. In the present embodiment, the semiconductor layer 43 (four) layer 436. Incoming amorphous dream = when a medium-prepared method such as 疋 is doped to dope the dopant into the amorphous material ===== two = two and the layer (10) has at least one opening 612 = first region 6 4 and opening The secret 614 outside the 612 and the first position correspond to the gate 212A of the first line 616 ° opening 612 of the first line segment 216. At the end of w, the first region 614 corresponds to the house, and the patterned photoresist layer 610 has a thickness in the first region 614 that is greater than the thickness in the second region 616. Then, referring to Fig. 6B, the exposed portion σ & ^^ s conductor layer 432 and the half exposed by the intermediate drawer 4fn 612 are, for example, subjected to a side-side process to form a contact window 218. The step of the step and the patterning of the semiconductor diode region 616 of the faint layer ★ the resist layer 61 〇 3 = the body layer 432 and the gate insulating layer (four) to avoid the secret = /, the lower + conduction 弁 reference map, remove the first Part of the second region (4) 荦 = layer: This step is, for example, a picture: a portion of the patterned photoresist layer (10) of the germanium region 616 has = degrees, and a portion of the first region 014 is blocked by A u With thickness. Therefore, when the second region of the photoresist layer 610 has a thicker portion of the patterned photoresist layer 610, the first region 614 is completely removed during the ash 29776 99-7-16 process. There are still some parts that have not been removed, so as to follow the first (4) as the first mask, please refer to FIG. 6D and FIG. 6E, and use the first area 614 i to remove the resist layer 610 as a mask. Part of the semiconductor layer 432. The patterned photoresist layer 51 of the first region 214 is removed from the layer 430. The semiconductor layer 432 3 in the second region 616 is removed, leaving only over the gate 212A = two without the need for a different mask: this helps to save on the cost of the purchase and the mask. Of course, under different process designs, the present invention 2 is divided into different masks to form 218 and patterned semiconductor layer 430, respectively, in different processes. ^ Riding in the painting material hiding method of the present invention and the manufacturing method thereof, each line segment of the lower electrode of the thinking storage valley is different from the adjacent metal line, or the storage capacitor lower electrode and the adjacent metal line, for example, sweep = A short circuit is unlikely to occur between the lines. That is to say, the pixel array structure and the manufacturing method thereof have high process yield, and the short circuit between the storage capacitor lower electrode and the adjacent metal line is not easy to occur, and the storage capacitor lower electrode and the adjacent scan line or data are stored. The distance between the lines can be shortened to help increase the display aperture ratio of the halogen structure. Briefly, === high process yield and high display aperture ratio of the pixel array 0, and the present invention has been disclosed in the preferred embodiment as above, but it is not used for the invention, and has any technical field. Generally, the knowledge holder, within the spirit and scope of the invention, does not deviate from the spirit and scope of the present invention. Therefore, the scope of protection of this (4) is subject to _ _ _ _ _ _. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial schematic view showing a conventional halogen array structure. 2 is a schematic diagram of a pixel array structure of an embodiment of the present invention. 3 is a top plan view of the halogen structure of FIG. 2. 4A to 4 are cross-sectional views showing the fabrication method of the pixel array structure of Fig. 2 along the line aa. FIG. 5 is a schematic view of a translucent cover according to an embodiment of the present invention. 6A to 6E illustrate a pattern body layer of the pixel array structure of Fig. 2 and a method of manufacturing the contact window. 〃 [Main component symbol description] 100, 200: pixel array structure 102, 202: scan lines 104, 204: data lines 110, 210: pixel structure 112, 212: active elements 114, 214: halogen electrodes 120, 216 : storage capacitor lower electrode 212A: gate 212B: source 212C: drain 216A: first line segment 1329776 99-7-16 216B: second line segment 218: contact window 400: substrate 410: first metal layer 420: gate Insulation layer 430: patterned semiconductor layer 432: semiconductor layer 434: undoped amorphous germanium layer 436: doped amorphous germanium layer 440: second metal layer 450: protective layer 500: semi-transparent dry 610: patterned light Resistive layer 612: opening 614: first region 616: second region A-A': line. P: halogen region T, ΤΙ, T2, T3: light transmissive region 16