1328859 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多重金屬内連線結構及其製作方 法，特別是指一種運用交錯設計之多重金屬内連線結構及 其製作方法。 【先前技術】 互補式金氧半導體電晶體影像感測器（CMOS image sensor，CIS)和載子偶合裝置（charge-coupled devices， CCDs)都是習知技術中常用來將光轉換為電子訊號的光學 電路元件，兩者的應用範圍皆很廣泛，包括有掃描器、攝 影機、以及照相機等等，但是因為載子偶合裝置受限於價 位高以及體積大的問題，所以目前市面上以互補式金氧半 導體電晶體影像感測器較為普及。 由於互補式金氧半導體電晶體影像感測器是以傳統的 半導體製程製作，因此可以大幅減少所需成本及元件尺 寸，而其應用範圍包括個人電腦相機以及數位相機等數位 電子商品，目前互補式金氧半導體電晶體影像感測器大致 分為線型、面型兩種，而線型互補式金氧半導體電晶體影 像感測器以應用在掃瞄器等產品為主，面型互補式金氧半 導體電晶體影像感測器則以應用在數位相機等產品為主。 1328859, 請參考第1圖至第2圖，第1圖至第2圖為習知技術 中製作用於互補式金氧半導體電晶體影像感測器之多重金 屬内連線結構之製程剖面示意圖。如第1圖所示，習知互 補式金氧半導體電晶體影像感測包含一像素陣列區域 (pixel array area ) 102以及一邏輯電路區域1 〇4，分別製 作於一半導體基底110上，且像素陣列區域102包含複數 個淺溝隔離（shallow trench isolation，STI) 112 以及複數 個感光二極體（photodiode) 114，而邏輯電路區域104包 含複數個邏輯元件115。其中，各感光二極體114係另電連 接相對應之重置電晶體（reset transistor )、電流汲取元件 (current source follower)及列選擇開關（row selector)等 之金氧半導體（M0S)電晶體（未顯示），而且淺溝隔離 112係用來作為任兩相鄰之感光二極體114與金氧半導體 電晶體之間的絕緣體（insulator)，以避免感光二極體114 因和其他元件相接觸而發生短路。 · 隨後於半導體基底no上形成一層間介電（interlayer dielectric，ILD )層116，覆蓋感光二極體114、邏輯元件 115與淺溝隔離112,接著於層間介電層116上進行一金屬 化製程，以形成一第一圖案化金屬層118與一第一阻擋金 屬層120。由於此金屬化製程係先蝕刻層間介電層116 ’接 著於層間介電層116上沉積一金屬層，例如一銅金屬層， 最後再於此金屬層與層間介電層116上進行一平坦化製 1328859 程，例如一化學機械研磨（chemical mechanical polishing， CMP)製程，以形成第一圖案化金屬層118與第一阻擋金 屬層120.，而又因為習知技術之第一阻擋金屬層120常利 用形成大面積金屬圖案來作為光遮蔽性結構，因此第一阻 擔金屬層120之圖案密度（pattern density)遠大於第一圖 案化金屬層118之圖案密度，所以在經過此平坦化製程之 後，第一阻擋金屬層120會因為圖案密度過高而導致表面 發生凹陷（dishing)，而導致之後一連串之金屬化製程與平 坦化製程都會產生不均勻的問題，並且此種不均勻的問題 會隨著往後金屬化製程與平坦化製程的數量增加而變得更 加嚴重，如第2圖所示，接續於層間介電層116、第一圖 案化金屬層118、與一第一阻擔金屬層120上形成一金屬 間介電（inter metal dielectric，IMD)層 122，並再形成一 第二圖案化金屬層124與一第二阻擋金屬層126以及於第 二圖案化金屬層124與第二阻擋金屬層126上沉積一介電 層128，就更會加劇邏輯電路區域104與像素陣列區域102 的高低落差，導致嚴重平坦化不均勻的問題。 【發明内容】 本發明之目的係提供一種多重金屬内連線結構及其製 作方法，特別是指一種運用交錯設計之多重金屬内連線結 構及其製作方法，以解決上述習知技術所遭遇到的限制與 問題。 7 1328859. 根據本發明之申請專利範圍，係提供一種製作具光遮 蔽性之多重金屬内連線結構之方法，該方法至少包含下列 步驟’提供-基底，且該基底表面具有—像素陣列區域 (piWy嶋）與一邏輯電路區域，於該基底上沉積一 第-介電層’於該第-金屬間介電層上進行—第—金屬化 製程，以於該像素陣列區域與該邏輯電路區域上方分別形 成-第-圖案化金屬層以及—第二圖案化金屬層，於該第 -圖案化金屬層、該第二圖案化金屬層與該第—介電層上 沉積-第二介電層，於該第二介電層上進行—第二金屬化 製程，以於該像素陣列區域與該邏輯電路區域上方分別形 成一第二圖案化金屬層以及一第四圖案化金屬層，且該第 四圖案化金屬層之圖案與該第二圖案化金屬層之圖案係為 父錯設計，以完全遮蔽該邏輯電路區域，以及於該第三圖 案化金屬層與該第四圖案化金屬層上沉積一平坦化介電層。 根據本發明之申請專利·範圍，另提供一種具光遮蔽性 之夕重金屬内連線結構，其至少包含有一基底，且該基底 表面具有一像素陣列區域與一邏輯電路區域；一第一介電 層，置放於該基底上；一第一圖案化金屬層，置放於該第 一介電層上，且位於該基底表面之該像素陣列區域上方； 一第二圖案化金屬層’置放於該第一介電層上，且位於該 基底表面之該邏輯電路區域上方；一第二介電層，置放於 該第一圖案化金屬層與該第二圖案化金屬層上；一第三圖 1328859 案化金屬層，置放於該第二介電層上，且位於該基底表面 之該像素陣列陣列區域上方；一第四圖案化金屬層，置放 於該第二介電層上’且位於該基底表面之該邏輯電路區域 上方，該第四圖案化金屬層之圖案與該第二圖案化金屬層 之圖案係為交錯設計’以完全遮蔽該邏輯電路區域；以及， 一平坦化介電層，置放於該第三圖案化金屬層與該第四圖 案化金屬層上。 【實施方式】 請參考第3圖至第4圖’第3圖至第4圖為本發明第 一較佳實施例之多重金屬内連線結構之製程剖面示意圖。 如第3圖所示，本發明首先提供一基底210，且基底210 表面具有一像素陣列區域202與一邏輯電路區域204，其 中，基底210係為一半導體基底，但不限制為一矽晶圓 (wafer)或一石夕覆絕緣（SOI)等之基底，且像素陣列區 202更包含複數個感光性之結構214，例如感光二極體 (photodiode)等，用來接收外部的光線並感測光照的強 度，而且該等感光性之結構另電連接有重置電晶體、電流 汲取元件或列選擇開關等之CMOS電晶體（未顯示），以 及複數個絕緣體212，例如淺溝隔離（STI)或局部矽氧化 絕緣層（local oxidation of silicon isolation layer，LOCOS )， 用以避免感光性之結構214、MOS電晶體與其他元件相接 觸而發生短路，而邏輯電路區204則可包含複數個邏輯元1328859 IX. Description of the Invention: [Technical Field] The present invention relates to a multi-metal interconnect structure and a method of fabricating the same, and more particularly to a multi-metal interconnect structure using a staggered design and a method of fabricating the same. [Prior Art] Complementary CMOS image sensor (CIS) and charge-coupled devices (CCDs) are commonly used in the prior art to convert light into electronic signals. Optical circuit components, both of which are used in a wide range of applications, including scanners, cameras, and cameras, but because of the high price and large size of the carrier coupling device, the current market is complementary gold. Oxygen semiconductor transistor image sensors are more popular. Since the complementary MOS transistor image sensor is fabricated by a conventional semiconductor process, the cost and component size can be greatly reduced, and the application range includes digital electronic products such as personal computer cameras and digital cameras, and is currently complementary. The MOS transistor image sensor is roughly classified into a line type and a surface type, and the line type complementary MOS transistor image sensor is mainly applied to a scanner and the like, and the surface type complementary MOS semiconductor is used. The transistor image sensor is mainly applied to products such as digital cameras. 1328859, please refer to FIG. 1 to FIG. 2, and FIG. 1 to FIG. 2 are schematic cross-sectional views showing a process of fabricating a multi-metal interconnect structure for a complementary MOS transistor image sensor in the prior art. As shown in FIG. 1 , the conventional complementary MOS transistor image sensing includes a pixel array area 102 and a logic circuit area 1 〇 4, which are respectively fabricated on a semiconductor substrate 110 and have pixels. The array region 102 includes a plurality of shallow trench isolation (STI) 112 and a plurality of photodiodes 114, and the logic circuit region 104 includes a plurality of logic elements 115. Each of the photodiodes 114 is electrically connected to a corresponding metal oxide semiconductor (M0S) transistor such as a reset transistor, a current source follower, and a row selector. (not shown), and the shallow trench isolation 112 is used as an insulator between any two adjacent photodiodes 114 and a MOS transistor to prevent the photodiode 114 from interfacing with other components. A short circuit occurs during contact. An interlayer dielectric (ILD) layer 116 is then formed on the semiconductor substrate no, covering the photodiode 114, the logic element 115 and the shallow trench isolation 112, and then a metallization process is performed on the interlayer dielectric layer 116. To form a first patterned metal layer 118 and a first barrier metal layer 120. Since the metallization process first etches the interlayer dielectric layer 116' and then deposits a metal layer, such as a copper metal layer, on the interlayer dielectric layer 116, and finally planarizes the metal layer and the interlayer dielectric layer 116. Process 1328859, such as a chemical mechanical polishing (CMP) process to form the first patterned metal layer 118 and the first barrier metal layer 120. And because the first barrier metal layer 120 of the prior art is often By forming a large-area metal pattern as the light-shielding structure, the pattern density of the first resistive metal layer 120 is much larger than the pattern density of the first patterned metal layer 118, so after passing through the planarization process, The first barrier metal layer 120 may cause the surface to be dished because the pattern density is too high, which may cause unevenness in a series of metallization processes and planarization processes, and the problem of such unevenness may The number of metallization processes and planarization processes increases and becomes more serious. As shown in FIG. 2, the interlayer dielectric layer 116 is connected. A patterned metal layer 118 and an inter-metal dielectric (IMD) layer 122 are formed on the first resistive metal layer 120, and a second patterned metal layer 124 and a second barrier metal are formed. The layer 126 and the deposition of a dielectric layer 128 on the second patterned metal layer 124 and the second barrier metal layer 126 further aggravate the difference between the logic circuit region 104 and the pixel array region 102, resulting in uneven planarization unevenness. problem. SUMMARY OF THE INVENTION The object of the present invention is to provide a multi-metal interconnect structure and a manufacturing method thereof, and more particularly to a multi-metal interconnect structure using a staggered design and a manufacturing method thereof, to solve the above-mentioned conventional techniques. Limitations and issues. 7 1328859. According to the patent application scope of the present invention, there is provided a method for fabricating a light-shielding multi-metal interconnect structure, the method comprising at least the following steps: providing a substrate, and the substrate surface has a pixel array region ( piWy嶋) and a logic circuit region, depositing a first dielectric layer on the substrate to perform a first metallization process on the first inter-metal dielectric layer, and the pixel array region and the logic circuit region Forming a first-first patterned metal layer and a second patterned metal layer on the top, and depositing a second dielectric layer on the first patterned metal layer, the second patterned metal layer and the first dielectric layer And performing a second metallization process on the second dielectric layer to form a second patterned metal layer and a fourth patterned metal layer respectively on the pixel array region and the logic circuit region, and the first The pattern of the four patterned metal layers and the pattern of the second patterned metal layer are designed as a parent to completely shield the logic circuit region, and the third patterned metal layer and the fourth patterning A planarizing dielectric layer is deposited on the metal layer. According to the patent application scope of the present invention, there is further provided a light-shielding metal-heavy interconnect structure comprising at least one substrate, wherein the substrate surface has a pixel array region and a logic circuit region; a first dielectric a layer disposed on the substrate; a first patterned metal layer disposed on the first dielectric layer and over the pixel array region of the surface of the substrate; a second patterned metal layer disposed a second dielectric layer disposed on the first patterned metal layer and the second patterned metal layer; FIG. 1328859 is a patterned metal layer disposed on the second dielectric layer and above the pixel array array region on the surface of the substrate; a fourth patterned metal layer disposed on the second dielectric layer And above the logic circuit region of the surface of the substrate, the pattern of the fourth patterned metal layer and the pattern of the second patterned metal layer are in a staggered design to completely shield the logic circuit region; and, Tan dielectric layer disposed on the third patterned metal layer and the fourth metal layer is patterned. [Embodiment] Please refer to Figs. 3 to 4'. Figs. 3 to 4 are schematic cross-sectional views showing a process of a multi-metal interconnect structure according to a first preferred embodiment of the present invention. As shown in FIG. 3, the present invention first provides a substrate 210 having a pixel array region 202 and a logic circuit region 204. The substrate 210 is a semiconductor substrate, but is not limited to a single wafer. A wafer or a substrate such as a SOI, and the pixel array region 202 further includes a plurality of photosensitive structures 214, such as photodiodes, for receiving external light and sensing illumination. The intensity, and the photosensitive structure is additionally electrically connected to a CMOS transistor (not shown) such as a reset transistor, a current extraction element or a column select switch, and a plurality of insulators 212, such as shallow trench isolation (STI) or A local oxidation of silicon isolation layer (LOCOS) is used to prevent the photosensitive structure 214, the MOS transistor from being in contact with other components, and the logic circuit region 204 may include a plurality of logic elements.