TWI327434B - Video processing - Google Patents

Description

1327434

发明, invention description: [Technical field to which the invention pertains] The field of the invention relates to a digital electronic computer system. In particular, the present invention relates to a system for efficiently processing video information on a computer system. In one aspect, the latent time system for performing video processing operations is disclosed. Another aspect is the stream processing in the video processor. The progressive revealer is a multi-dimensional data path processing in the video processor. Also disclosed are video processors with scalar and vector components. [Prior Art] The display of video and full-motion video allows for the improvement of the electronics industry in recent years. The display and rendering of high-quality video (especially high-definition digital) is the first standard for modern video technology applications and devices. Video technology is used in a variety of applications from mobile phones, personal video recorders, video projectors, high-definition televisions and the like. The emergence and continuous emergence of devices capable of generating and displaying high-definition video has undergone significant innovation and progress in the electronics industry. The technology developed in many consumer electronic and professional-level devices relies on one or more video processors to format and/or enhance the displayed video signals. This is especially true for digital video applications. For example, one or more video processors are incorporated into a typical transponder and used to convert HDTV broadcast signals into video signals that can be used by the display. Converting, for example, a video signal from a non-16 X 9 video image for proper display on a real 16x9 (eg widescreen) display This transfer ί1327434

The whole ratio. One or more video processors can be used to perform the scan conversion, where a video signal is converted from a staggered format (where the odd and even lines are displayed separately) to a continuous format in which the entire frame is in a single scan. Additional examples of video processor applications include, for example, signal decompression, which is received in a compressed format such as MPEG-2 and decompressed and formatted for use in a display. Another example is a re-interlaced scan conversion involving the entry of a digital video signal from a DVI (Digital Video Interface) format into a composite video format compatible with a large number of old television displays installed on the market. Most proficient users require more sophisticated video processor functions such as In-Loop/Out-of-Loop deblocking, adaptive de-interlacing, and input noise for encoding operations. Filtering, polyphase adjustment/re-sampling, sub-picture synthesis, and processor-amplifier operations (such as color space conversion, adjustment, pixel point operations (such as sharpening, histogram adjustment, etc.) and various video surface format conversion support operations. The problem with complex video processor functions is the fact that video processors with strong enough architecture to implement these functions can be incorporated into many types of devices that are too expensive. In terms of die area, total number of transistors, memory rate requirements, etc. The more complex the video processor function, the more expensive the integrated circuit device that needs to perform the functions. Therefore, the prior art system designers are forced to trade off the performance cost of the video processor. It is widely regarded as having an acceptable cost/performance ratio. The first technical video processor is usually limited only in the latent time (for example, to avoid making the video break in the ground) )) can be this and the previous 7 1327434

It is sufficient to delay the video processing application and to calculate the density (such as the number of processor operations per square millimeter of the die). Furthermore, prior art video processors are largely unsuitable for a linear adjustment performance requirement, such as where a video device is expected to process multiple video streams (e.g., simultaneously processing multiple input streams and output streams). What is therefore needed is a new video processor system that overcomes the limitations of the prior art. The new video processor system should be scalable and highly computationally intensive to handle the growing number of video processor functions that are proficient in user expectations. SUMMARY OF THE INVENTION A specific embodiment of the present invention provides a novel video processor system that supports complex video processing functions while efficiently using integrated circuit die areas, total transistor counts, memory rate requirements, and the like. Embodiments of the invention maintain high computational density and are easily scalable for multi-streaming. In a specific embodiment, a latent time permitting system is implemented for performing video processing operations in the video processor. The system includes a host surface for communicating between a video processor and a host CPU; a pure execution unit coupled to the host interface and configured to perform a pure volume processing operation; and a vector execution unit The host interface configuration is lightly coupled to perform vector video processing operations. A command FIFO is included to allow the vector execution unit to operate on a drive-by-drive basis by accessing the memory command FIFO. A memory interface includes communication between the video processing system and the user interface 8 1327434 and a frame buffer memory. A DMA engine is built into the memory interface for performing DMA transfers between a plurality of different memory locations and for loading a data storage memory and an instruction cache with data and instructions of the vector execution unit.

In a specific embodiment, the vector execution unit is configured to operate on a demand driven basis by accessing the command FIFO to operate asynchronously with the scalar execution unit. The demand-driven basis can be configured to hide the latency of data transferred from a different memory location (such as buffer memory, system memory, cache memory, etc.) to the command FIFO of the vector execution unit. The command FIFO can be a piped FIFO to avoid stalling vector execution units.

In one embodiment, the invention is embodied in a video processor for performing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. The video processor includes a memory interface for communicating between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and memory interface and configured to perform scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and configured to perform vector video processing operations. The video processor can be an independent video processor integrated circuit or can be a component integrated into a GPU integrated circuit. In a specific embodiment, the function of the scalar execution unit is a controller of the video processor and controls the operation of the vector execution unit. The scalar execution unit is configurable to execute an application flow control algorithm, and the vector execution unit is configurable to perform pixel processing operations of the application. The video processor can include a vector interface unit for causing the scalar execution unit to interface with the vector 9 1327434 execution unit. In a specific embodiment, the scalar execution unit and the vector execution unit are configured to operate asynchronously. The scalar execution unit can be executed at a first clock frequency, and the vector execution unit can be executed at a different clock frequency (e.g., faster, slower, etc.). The vector execution unit can operate on a demand driven basis under the control of a scalar execution unit.

In one embodiment, the invention is embodied in a multi-dimensional data path processing system for a video processor for performing video processing operations. The video processor includes a scalar execution unit configured to perform scalar video processing operations, and a vector execution unit configured to perform vector video processing operations. A data storage memory system is included to store the data of the vector execution unit. The data storage memory includes a plurality of tiles having a symmetric memory library data structure disposed in an array. The memory data structure is configured to support access to different partitions of each memory bank.

Depending on the requirements of a particular configuration, each bank (b a n k ) data structure may contain at least a plurality of blocks (e.g., 4x4, 8x8, 8x16, 16x24, or the like). In one embodiment, the memories are configured to support access to different blocks of each bank. This allows a single access to fetch a column or row of blocks from two adjacent banks. In one embodiment, a crossbar is used to select a configuration for accessing blocks of the plurality of memory material structures (e.g., columns, rows, blocks, etc.). A collector may be included to accommodate the partitions of the memory accessed by the crossbars and to provide the blocks to the front end of a vector data path based on each clock. In one embodiment, the invention is embodied as a stream-based memory access system for a video processor. The video processor includes a scalar execution unit configured to perform scalar video processing operations at 10 1327434, and a vector execution unit configured to perform vector video processing operations. A frame buffer memory is included to store data for the scalar execution unit and the vector execution unit. A memory interface is included to implement communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory contains at least a plurality of blocks. The memory interface implements a first stream for the first sequential access of the block of scalar execution units and implements a second stream for the second sequential access of the block of vector execution units.

In a specific embodiment, the first stream and the second stream include at least one of the pre-fetched blocks, and the pre-fetching method is to hide the position from the starting memory (such as the buffer memory, the system memory). Waiting for access latency. In a specific embodiment, the memory interface is configured to manage a plurality of different streams from a plurality of different starting positions to different ending positions of the plurality. In one embodiment, a DMA engine built into the memory interface is used to implement a plurality of memory reads and complex memory writes to support the majority stream. In general, the present disclosure discloses at least the following four methods.

(A) The method generally taught in the present specification is a multi-dimensional data path processing system for performing a video processing operation in a video processor, comprising at least: performing a scalar video processing operation by using a scalar execution unit; Performing a vector video processing operation by using a vector execution unit; storing data for a vector execution unit by using a data storage memory, wherein the data storage memory includes at least a plurality of blocks, at least comprising having an array configured Symmetric memory data 11 1327434

Structure, and wherein the memory data structure is configured to support access to different partitions of each memory bank. In addition, the method A includes at least a memory data structure including a plurality of blocks arranged in a 4x4 pattern. Meanwhile, the method A includes at least a memory data structure including a plurality of blocks configured as 8x8, 8x16 or 16x24 patterns. In addition, the method A includes at least a memory data structure configured to support access to different partitions of each memory data structure, wherein at least one access system to two adjacent memory data structures includes at least the two memory banks. A column of data structures. The method A is also configured to support access to different blocks of each memory data structure, wherein at least one access is to two adjacent memory data structures, and the at least two memory data are included A row of blocks of the structure. In addition, the method A includes at least selecting a configuration for accessing a plurality of memory data structures by using a crossbar coupled to the data storage. In this selection step, the crossbar accesses a plurality of blocks of the memory data structure to provide data to a vector data path based on each clock. At the same time, it relates to the use of a collector to accommodate the partitions of the plurality of memories accessed by the crossbar; and to provide the blocks to the front end of a vector data path based on each clock. (B) The method generally taught in the present specification is also a method for performing a video processing operation, the method implemented using a video processor of a computer system that executes a computer readable code, the method comprising at least: by using A host interface establishes 12 1327434 between the video processor and a host CPU

Communication; establishing communication between the video processor and a frame buffer memory by using a memory interface; performing scalar video processing operations by using a scalar execution unit coupled to the host interface and the memory interface; The vector video processing operation is performed by using a vector execution unit coupled to the host interface and the memory interface. The method B further includes the function of the scalar execution unit as a controller of the video processor, and controls the operation of the vector execution unit. The method B further includes at least a vector interface unit for causing the scalar execution unit and the vector execution unit to generate an interface. The method B disclosed above also includes at least a scalar execution unit and a vector execution unit configured to operate asynchronously. At the same time, the scalar execution unit is executed at a first clock frequency and the vector execution unit is executed at a second clock frequency. The method B further includes at least a scalar execution unit configured to execute an application flow control algorithm, and the vector execution unit is configured to perform pixel processing operations of the application. Furthermore, the vector execution unit is configurable to operate on a demand driven basis under the control of the scalar execution unit. In addition, the scalar execution unit is configured to call to the vector execution unit using a memory command FIFO transfer function, the vector execution unit operating on a demand driven basis by accessing the memory FIFO. At the same time, the asynchronous execution of the vector execution unit is configured to support separate updates of the vector subnormal or scalar subnormal of the application. Finally, the method B described above includes at least a scalar execution unit configured to operate using a VLIW (very long instruction) code. (C) This specification also generally teaches a method of performing video processing operations 13 1327434

a method for stream-based memory access in a video processor, the method comprising: performing a scalar video processing operation by using a scalar execution unit; performing a vector video processing operation by using a vector execution unit; Data for storing scalar execution units and vector execution units by using a frame buffer memory; and implementing communication between the scalar execution unit and the vector execution unit and the frame buffer memory by using a memory interface The frame buffer memory includes at least a plurality of blocks, and wherein the memory interface implements a first stream including at least a first sequential access of the block, and the implementation one includes at least a vector execution unit or a scalar The second stream of the second sequential access of the chunks of the execution unit. The method c also has a first stream and a second stream comprising at least one prefetched block. The method C further includes a first stream starting from a first position in the frame buffer memory and a second stream starting at a second position in the frame buffer memory. The method C also includes at least a memory interface configured to manage a plurality of streams from a plurality of different starting positions to a plurality of different ending positions. In this aspect, at least one of the starting positions or at least one of the ending positions is in a system memory. The method C further includes performing at least a memory reading by using a DMA engine built in the memory interface to support the first stream and the second stream; and performing a plurality of memory writes to support the first stream And the second stream. In addition, the method C includes at least a first stream experiencing a higher number of potentials than the second stream, wherein the first stream combines a buffer having a larger number of streams than the second stream for storing the blocks. The method c also includes at least a memory interface configured to prefetch an adjustable number of first streams 14 1327434 or blocks of the second stream to compensate for the latency of the first stream or the second stream.

(D) The method described herein also includes a method for substantially allowing video processing operations in a latent manner, the method comprising: at least: communicating between the video processor and a host CPU by using a host interface; Performing a scalar video processing operation using a scalar execution unit coupled to the host interface; performing a vector video processing operation by using a vector execution unit coupled to the host interface; allowing the vector execution unit to access a memory The command FIFO operates on a demand-driven basis; by using a memory interface to implement communication between the video processor and a frame buffer memory; and implementing DMA transfer between a plurality of different memory locations by using A DMA engine built into the memory interface and configured to load a data storage memory and an instruction cache for data and instructions for the vector execution unit. The method D further includes the vector execution unit configured to operate asynchronously with the scalar execution unit by accessing the command FIF 0 to operate on a demand driven basis. The above method D also includes at least the demand-driven basis configured to hide the latency of a data transfer from a different memory location to the command FIFO of the vector execution unit. In addition, the method D includes at least the scalar execution unit configured to implement an algorithm flow control process, and wherein the vector execution unit is configured to perform most video processing workloads. Here, the scalar execution unit is configured to pre-calculate operating parameters for the vector execution unit to hide the material transfer latency. The above method D includes at least the vector execution unit configuration to execute a memory library via the DMA engine to prefetch commands for the order of the vector 15 1327434. Here, the memory reading system is arranged before the execution of the vector subroutine by the scalar execution unit call to the vector subroutine. Safe

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments embodiments While the invention will be described in conjunction with the preferred embodiments, the invention Instead, the invention is intended to cover alternatives and modifications of the invention and the scope of the invention as defined by the appended claims. In addition, in the following detailed description of the embodiments of the invention, various specific details are However, it will be apparent to those skilled in the art that the present invention may be embodied in the specific details. In other instances, methods, procedures, components, and circuits that are not described in detail are intended to not obscure the features of the embodiments. Show the god of the disk

Notes and Terminology Some of the following detailed descriptions are presented in terms of procedures, steps, logical blocks, processing, and other symbolic representations of operations on computer data. These instructions and representations are used by those who are familiar with the data processing techniques to best convey the true meaning of their work to other people who are familiar with the technology. Here, a program, computer execution steps, logical chunking process, etc. are generally considered to be the self-consistent sequence of steps or instructions leading to a demand result. These steps are the actual controllers that require physical quantities. Usually positional surgery but 16 1327434 is not necessarily a form of electrical or magnetic signals that can be stored, transferred, combined, compared or manipulated in a computer system. It has proven convenient at times (primarily for common use reasons) that such signals are bits, values, components, symbols, characters, terms, numbers or the like.

It should be noted, however, that all such and similar terms are to be construed as being Unless specifically stated otherwise in the following discussion, a discussion such as "processing" or "access" or "execution" or "storage" or "description" or similar terms throughout the present invention refers to a computer system (eg, The operation and processing of the computer system 1 00), or similar electronic computing device of Figure 1, which manipulates and converts data represented by physical (electronic) quantities in the registers and memory of the computer system, to be similarly represented Other data in the physical quantities of the computer system memory or scratchpad or other such information storage, transmission or display device. Computer system platform:

Figure 1 shows a computer system 100 in accordance with an embodiment of the present invention. Computer system 100 depicts a basic computer system component in accordance with an embodiment of the present invention that provides an execution platform for certain hardware and software based functions. In general, computer system 100 includes at least one C P U 1 0 1 , a system memory 1 15 , and at least one processor unit (GPU) 110 and a video processor unit (VPU) 111. The CPU 101 can be coupled to the system memory 1 15 via the bridge component 105 or directly coupled to the system memory 115»bridge component 105 (eg, Northbridge) via a memory controller (not shown) internal to the CPU 101. Support for connecting various I/Os 17 1327434

Expansion bus for devices (such as one or more hard drives, Ethernet adapters, CD ROM, DVD, etc.). The GPU 110 and the video processor unit ηι are lightly coupled to a display 112. One or more additional GPUs may additionally be consumed to system 100 to further increase its computing power. The GPU 110 and the video processor unit 1 1 1 are coupled to the CPU 1 0 1 via the bridge component 1 〇 5 and the system memory 1 1 5 » The system 1 0 0 can be implemented, for example, as a desktop computer system or a server computer system. It has a powerful general purpose CPU 1 01 coupled to a dedicated graphics depicting GPU 110. In this embodiment, components may be included to increase peripheral busbars, dedicated graphics memory and system memory, 10 devices, and the like. Similarly, system 100 can be implemented as a handheld device (such as a mobile phone, etc.) or a video game control device, such as the Xbox® available from Microsoft Corporation of Redmond, Washington, USA, or the PlayStation 3® from Sony Computer Entertainment, Tokyo, Japan.

It should be appreciated that GPU 1 10 can be implemented as a discrete component, a discrete graphics card, a discrete device, designed to be coupled to a computer system via a connector (eg, an AGP slot, a PCI-Express slot, etc.) The integrated circuit die (e.g., mounted directly on the motherboard) or integrated GPU 100 (e.g., integrated into the bridge wafer 105) included in the integrated circuit die of a computer system chipset assembly. In addition, a partial graphics memory can be included for the GPU 11 高频 of the high frequency wide graphics data storage. In addition, it should be understood that the GPU 11 and the video processor unit 111 can be integrated on the same integrated circuit die (eg, component 120)' or can be a discrete discrete integrated circuit connected to or mounted on the motherboard of the computer system 100. Component. 18 1327434

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 2 shows a diagram depicting the internal components of the processor unit 111 in accordance with an embodiment of the present invention. As shown in FIG. 2, the processor unit 111 includes a scalar execution unit 201, a vector implementation 202, a memory interface 203, and a host interface 204. In the particular embodiment of Figure 2, the video processor unit (as the video processor) 111 includes functionality for performing video processing operations. The video processor 111 uses the host interface 204 to communicate between the video processor 1 1 1 and the host C P U 1 0 1 via the bridge. The video 111 uses a memory interface 203 (e.g., for coupling the display 112, > to establish a video processor 11 1 and a frame buffer memory 205. The scalar execution unit 201 couples the host interface 204 and the face. 2 0 3, and configured to perform a scalar video processing operation. The directional unit is coupled to the host interface 204 and the memory interface 203, and performs vector video processing operations. The specific embodiment of FIG. 2 shows the video processor 111. The execution function becomes a scalar operation and a vector operation. The scalar operation is implemented by the execution unit 201. The vector operation is performed by the vector execution unit. In a specific embodiment, the vector execution unit 202 is configured with a scalar execution unit 201. A slave coprocessor. In this embodiment, the scalar execution unit manages the workload of the vector execution unit 202 by the feed control flow to the vector execution unit, and manages the data input/output for the vector element 2 0 2 . The control flow usually includes at least the functional video location, the video unit, the energy component, the processor, and the processor. A real scalar 202 to 202 as an embodiment to perform a single parameter, 191,327,434 subroutine arguments, and the like. In a typical video processing application, the control flow of the application's processing algorithm will be executed on the scalar execution unit 201, and the actual pixel/data processing operations will be performed on the vector execution unit 202.

Referring again to Figure 2, the scalar execution unit 201 can be implemented as a RISC model scalar execution unit incorporating RISC-based execution techniques. Vector execution unit 202 can be implemented as a SIMD machine having, for example, one or more SIMD pipes. In a 2 SIMD pipeline embodiment, for example, each SIMD pipeline can be implemented with a 16 pixel wide data path (or wider), and thus vector execution unit 202 is provided with raw computational power to produce up to 32 pixels per clock. Data output. In one embodiment, scalar execution unit 201 includes hardware configured to operate using VLIW (very long instruction) software code to optimize parallel execution of the scalar operation based on each clock.

In the particular embodiment of FIG. 2, scalar execution unit 201 includes an instruction cache 2 1 1 coupled to scalar processor 2 1 0 and a data cache 212. The cache 211-212 and the memory interface 203 create an interface for access to external memory, such as the frame buffer 205. The scalar execution unit 201 further includes a vector interface unit 213 to establish communication with the vector execution unit 202. In a specific embodiment, vector interface unit 213 can include one or more synchronization mailboxes 2 1 4 configured to allow for asynchronous communication between scalar execution unit 201 and vector interface unit 213. In the particular embodiment of Figure 2, vector execution unit 202 includes a vector control unit 220 configured to control the operation of a vector execution data path (vector data path 2 2 1 ). Vector control unit 220 includes a command 20 1327434 FIFO 225 to receive instructions and data from scalar execution unit 201. An instruction cache 2 2 2 is coupled to provide instructions to the vector control unit 2 2 0. A data storage memory 2 2 3 is coupled to provide input data to the vector data path 22 1, and the generated data is received from the vector data path 22 1 . The function of the data storage 223 is the instruction cache of the vector data path 22 1 and the data RAM.

Instruction cache 222 and data store 223 are coupled to memory interface 203 for accessing external memory, such as frame buffer 205. The specific embodiment of Fig. 2 also shows a second vector data path 2 3 1 and a second data storage 2 3 3 (e.g., a dotted line profile). It should be understood that the display second vector data path 2 3 1 and the second data storage 2 3 3 are used to demonstrate that the vector execution unit 202 has a two vector execution pipeline (e.g., a dual SIMD pipeline configuration). Particular embodiments of the present invention are suitable for vector control units having a large number of vector execution pipes (e.g., four, eight, sixteen, etc.). The scalar execution unit 201 provides data and commands for the vector control unit 220. In one embodiment, scalar execution unit 207 transfers a function call to vector execution unit 202 using a memory map command FIFO 225. The vector execution unit 202 commands the system to be listed in this command FIFO 225.

The use of command FIFO 225 effectively decouples scalar execution unit 201 from vector execution unit 202. The scalar execution unit 201 can operate on its own individual clock, on its own individual clock frequency different from the clock frequency of the vector execution unit 202, and be separately controlled. The command FIFO 225 enables the vector execution unit 202 to operate as a demand drive unit. For example, the work may be handed over to the command FIFO 225 from the scalar execution unit 201, and then accessed by the vector execution unit 202 for processing in an unsynchronized manner of a decoupling of 21 1327434. The vector execution unit 202 will therefore process its workload as needed or as a scalar execution unit 2 0 1 requirement. This function will allow vector execution unit 202 to conserve power when maximum performance is not required (e.g., by reducing/stopping one or more internal clocks).

The distinction between the video processing function becomes a scalar portion (as performed by the scalar execution unit 201) and a vector portion (as performed by the vector execution unit 202) allows the video processing program created for the video processor 111 to be compiled into separate Scalar software code and vector software code. The scalar software code and the vector software code can be separately encoded and subsequently joined together to form a coherent application.

The distinction allowed vector software code function is written separately and is different from the scalar software code function. For example, vector functions can be written separately (eg at different times, by engineers of different teams, etc.) and can be provided as one or more subnormal or library functions for scalar functions (eg scalar) Use or use with threads, processes, etc.). This allows scalar software codes and/or vector software codes to be updated independently, respectively. For example, a vector subroutine may be updated independently of a scalar subroutine (e.g., by a previous allocation program update, a new feature added to increase the functionality of the assigned program), or vice versa. The zone is implemented by a scalar processor 210 (e.g., cache 2 1 1 to 2 1 2) and a separate vector cache of vector control unit 220 and vector data path 221 (e.g., caches 222 to 223). As described above, the scalar execution unit 201 and the vector execution unit 202 communicate via the command FIFO 225. Figure 2 shows a diagram of an exemplary software program 300 of video processor 111 in accordance with an embodiment of the present invention. As shown in FIG. 3, the software program 300 displays the attributes of the programming mode of the video processor 111, wherein a 22 1327434 scalar control thread 3 Ο 1 is a video processor 1 1 coupled by a vector data thread 021 1 execution.

The software program of the embodiment of the third embodiment shows a programming mode for the video processor 111, wherein a scalar control program (such as a scalar control thread 3 0 1) on the scalar execution unit 201 is A subroutine call (e.g., vector data thread 302) is executed on vector execution unit 02. The software program 300 example shows a situation in which a compiler or software programmer has decomposed a video processing application into a scalar portion (such as a first thread) and a vector portion (such as a second thread). As shown in Fig. 3, the scalar control thread 3 0 1 executed on the scalar execution unit 2 0 1 pre-calculates the operational parameters, and feeds the parameters to the vector execution unit 202, which performs the main processing work. As described above, the software codes of the two threads 301 and 302 can be written and compiled separately. The scalar thread is responsible for the following: 1. Generate interface with host unit 204 and implement a class interface; 2. Initialize, set and configure vector execution unit 2 0 2; and 3. Work unit in primary loop , block, working set execution algorithm,

In each iteration; a. parameters for the current working set are calculated; b. initially the input data is transferred to the vector execution unit; and c. the initial self-vector execution unit transfers the output data. The typical execution mode of a scalar thread is "fire-and-forget". The term "unexpected after shooting" refers to the typical mode of a video baseband processing application, in which the commands and data are from 23 1327434.

The scalar execution unit 2 Ο 1 is transferred to the vector execution unit 2 Ο 2 (e.g., via FIFO 225), and no data is returned from the vector grant 2 0 2 until the algorithm is completely complete. In the example of the program 300 of Figure 3, the scalar execution unit 201 holds the work for the vector execution unit 202 until the command FIFO 225 has any more space (e.g., 'lend_of_alg&!cmd_fifo_full). The parameters are calculated by the execution unit 2 0 1 scheduling and the parameters are passed to the vector subroutine, and the vector subroutine is subsequently called to execute the working routine (eg, vector_funcB) by the vector execution unit 2〇2 The delay in execution time is mainly used to hide the latency from the main memory (such as system record 115). Thus, the architecture of video processor 111 illustrates these latent time compensation mechanisms in greater detail for the command material flow to provide a latent time compensation mechanism on the vector execution unit 202 side. It should be noted that in the case where there are two or more vector execution pipelines (such as the vector data path 221 and the second vector data path 231 of the figure), the software program 300 instance will be more complicated. Similarly, the software program 300 will be more complicated for the ability of the program 300 to perform on a system with two vector execution pipelines while still maintaining a single vector execution pipeline. Thus, as discussed above in Figures 2 and 3, the scalar unit 201 is responsible for the calculations on the start vector execution unit 202. In the embodiment, the command passed from the scalar execution unit 2 0 1 to the vector execution unit is the following main types: 1. The read command (eg, memRd) is commanded by the scalar execution unit 201. Baozhong is not sent to the amount. The secondary system in the memory and the resource 0 in the second case, in one case, a '202 start, 24 1327434 to transfer the current working set data from the memory to the data RAM of the vector execution unit 202; 2. parameters, from The scalar execution unit 201 passes to the vector execution unit 202; 3. executes the command, in the form of a PC (eg, a program counter) of the vector subroutine to be executed; and a 4_ write command (eg, memWr), The result of the copy vector calculation is started by the scalar execution unit 201 into the memory.

In one embodiment, upon receiving such commands, vector execution unit 202 immediately schedules the mmRd command to memory interface 203 (e.g., reads the requested data from frame buffer 205). Vector execution unit 202 also checks the execution command and prefetches the vector subroutine to be executed (if not present in cache 222).

In this case, the goal of vector execution unit 202 is to pre-arrange the instructions and data streams for subsequent executions, while vector execution unit 02 operates on the current execution. The pre-scheduling feature effectively hides the latency associated with the fetch instructions/data from its memory location. In order for these read requests to be made in advance, the vector execution unit 202, the data store (e.g., data store 223), and the instruction cache (e.g., cache 222) are implemented using high speed optimized hardware. As described above, the data store (e.g., data store 223) functions as the work RAM of vector execution unit 202. The scalar execution unit 201 senses and interacts with the data store as if it were a collection of FIFOs. The FIFO contains at least the "stream" operated by the video processor 111. In one embodiment, the stream is substantially the scalar execution unit 201 that initiates the transfer (to vector execution unit 202) 25 1327434 the input/output FIFO. As described above, the operations of the scalar execution unit 201 and the vector execution unit 202 are decoupled. Once the input/output stream is full, one of the vector control units 220 stops processing the command FIFO 225. This immediately causes the command FIFO 225 to be full. When the command FIFO 225 is full, the scalar execution unit 201 stops transmitting additional work to the vector execution unit 202.

In a specific embodiment, vector execution unit 202 may require an intermediate stream in addition to the input and output streams. Thus the entire data store 2 2 3 can be viewed as a collection of streams relating to the scalar execution unit 201. Figure 4 shows an example of using a video processor to mix sub-pictures and video in accordance with an embodiment of the present invention. Figure 4 shows a representative case where one video surface is mixed with a sub-picture and then converted into an ARGB surface. The data containing at least the surfaces resides in the frame buffer memory 205 to become the Luma parameter 412 and the Chroma parameter 413. Sub-picture pixel element 414 is also resident in frame buffer memory 205 as shown. The vector subroutine instruction and parameter 4 1 1 are instantiated in memory 250 as shown.

In one embodiment, each stream contains at least one FIFO that operates 2D block data called "tiles." In this embodiment, the vector execution unit 202 maintains a read block pointer and a write block pointer for each stream. For example, for an input stream, when performing a vector subroutine, the vector subroutine can consume a current (read) block or read from it. In the background, the data is transferred to the current (write) block by the memRd command. The vector execution unit also produces an output block for the output stream. These blocks are then moved to memory by following the memWr command that executes the command. This effectively operates on 26 1327434, effectively hiding the latency. In the hybrid example, the vector data path 2 2 1 and the parameter 411 (eg, & v a subp_blend) are instantiated. This is shown by * 42]. The scalar execution unit ^ is read into the surface of a block (e.g., a block) and loaded into the data store 223 using the DMA engine 40 1 (e.g., in the memory interface 203). The load operation is indicated by line 422, line 423, and line 424.

Prefetch the block and prepare it in the picture in Figure 4. By the vector subroutine instruction. Please refer to Fig. 4. Since there are multiple input surfaces, it is necessary to maintain multiple input streams. Each stream has a corresponding FID〇. Each stream can have a different number of points

A case where the surface of the sub-picture is attached to the system memory 115 (e.g., sub-picture pixel element 414), and thus there will be additional buffers (e.g., η, n+i, n + 2, n + 3, etc.) Etc.), while video streams (such as Luma 412, Chroma 413, etc.) can have a smaller number of chunks. The number of buffers/FIFOs used can be adjusted based on the degree of latency experienced by the stream.

The data storage 223 as described above utilizes a forward look-ahead method to hide the latency. Since this 'first class' can have data in two or more blocks, the data is prefetched for the appropriate vector data path execution software (e.g., as FIFOn 'n+1, n + 2, etc.). Once loaded into the data store, the FIF is accessed by the vector data path hardware 221 and operated by a vector subroutine (e.g., subroutine 430). The result of the vector data path operation includes at least the _output stream 403. This output stream is copied back to the frame buffer memory 205 (e.g., ARGB OUT 415) by the scalar execution unit 2 0 1 via the D Μ A engine 401. This is shown by line 425. Thus, embodiments of the present invention use the important features of stream processing, 27 1327434

Its data storage and memory system is extracted into a plurality of blocks, which can be regarded as a continuous access set of blocks. Flow system material. This information is in the form of chunks. The blocks are prefetched with the potential of a particular memory source (such as system memory, frame, or the like) from which the data begins. Similarly, the stream can be specified (e.g., for vector execution unit cache, for scalar execution fetches, frame buffer memory, system memory, etc.). The stream is generally accessed in a pre-fetch mode to access the tiles. The higher the above, the deeper the prefetch and the more buffers used per stream (as described above). Figure 5 shows a diagram depicting the internal components of a row unit in accordance with an embodiment of the present invention. The diagram of Figure 5 illustrates the configuration of various functional units and scratchpad resources of a vector execution unit 202. In the specific embodiment of Fig. 5, vector execution unit 202 is a VLIW digital signal processor that is most suitable for the performance of video baseband processing and the execution compression algorithm of various codes. Therefore, the meta 202 has some attributes that directly point to increasing the efficiency of video processing/decoding. In the specific embodiment of Figure 5, the attributes include at least 1. by providing an option performance for combining multiple vector execution pipelines; 2_ each pipeline 2 data address generator (DAG) allocation; Body/scratch operator; fact. Therefore, the pre-funding hides the fast-characteristic feature from the location unit of the buffer memory, and the vector display of the submersible 4 image viewer/SRAM contains at least (the compression-decompression execution of the single-code execution expandable 28 1327434 4. 2D (x, y) pointer / iterator; 5 · deep pipeline (such as 1 1 to 12) level; 6 scalar (integer) / branch unit; * 7 · variable instruction width (long / Short instruction); \8. Data aligner for operand extraction: • 9. 2D data depth (4x4) shape of typical operands and results; and 10. Dependent vector execution unit of scalar execution unit, executing remote Program call Φ In general, the programmer of vector execution unit 202 has a SIMD data depth of 2DAG 503. The instruction is transmitted in VLIW mode (for example, the instruction system is both vector data depth 5 0 4 and address generator). 5 0 3 is transmitted) and decoded by the instruction decoder 501 and dispatched to the appropriate execution unit. The instruction is variable length, wherein the most commonly used instructions are encoded in a short form. The full instruction set can be in a long form (such as a VLIW type instruction). )use.

Legend 502 shows three clock cycles with three of these VLIW instructions. According to the legend 510, the uppermost VLIW instruction 502 includes at least two address instructions (e.g., for 2DAG 503) and an instruction for vector data depth 504. The intermediate V LIW instruction includes at least one integer instruction (e.g., integer unit 505), an address instruction, and a vector instruction. The bottommost VLIW instruction contains at least one branch instruction (e.g., for branch unit 5 0 6), an address instruction, and a vector instruction. The vector execution unit can be configured to have a single data pipeline or multiple data pipelines. Each data pipeline is comprised of a local RAM (e.g., data storage 51 1 1), a crossbar 516, 2 DAG 503, and a SIMD execution unit (e.g., vector data 29 1327434 depth 504). Figure 5 shows a basic configuration for illustrative purposes, in which only the data pipeline is illustrated. When exemplifying 2 data pipelines, they can be executed as independent threads or as collaborative threads. Six different 埠 (such as 4 sf take and 2 write unit 515 access. These registers receive parameters from scalar execution units or results from integer unit 505 or address unit 503. DAG 503 also acts as a collection control And manage the distribution of the scratchpad to address the data store

Contents of 511 (such as RAO, RA1, RA2, RA3, WA0, and WA1). A crosspiece 5 16 is coupled to distribute the output data bee R 〇, Rl, R2, R3 to the vector data depth 5 〇 4 in any order/combination to implement a given s command. The wheel of vector data depth 504 can be fed into data store 511 as shown. A fixed RAM 517 is used to provide the commonly used transport-to-vector data depth 504 and data store 511 from the integer unit 5〇5. Figure 6 shows a plurality of memory banks 〇1 to 604 and a data storage 61 具有 layout having a symmetrical block array in accordance with the present invention. As shown in Figure 6, only for the purpose of understanding

(4) Part of the 61G register. The data payload (4) logically contains at least a (or plural) block array. Each block is 4χ4 ?1| _ heart-shaped sub-blocks. In fact, as shown in memory 600, the data is stored in the memory of the "Ν" entity of the memory: the 61G system. , S memory library 601 to 604) ~ logical division in the stream 6-bit tuple high and 16 in 4 X 4) array. In addition, the data store 610 visually describes the block embodiment of Figure 6, which is the width of the ι byte group. This block is a sub-block (in this example 30 1327434 each sub-block is stored in a physical memory. In the case of 8 memory entities (such as memory bank 〇 to 7), this is shown in The number in each 4x4 sub-block. The organization of the sub-blocks in the memory does not share the memory in the 2x2 configuration of the sub-block. This allows any quasi-access (as in the X and y directions) to be absent. Any memory conflict line. The memory library 60 1 to 604 are configured to support access to the same block of each memory. For example, in one case, the crossbar 5丨6 can take a block of 2x4 set from the memory stock. (For example, the first two columns of group 601.) In another case, the crosspiece 516 can take 1 χ 8 sets of blocks from two adjacent memory stocks. In the other case, the crossbar 5 i 6 can be taken from two adjacent memory stocks. i] Blocking. In each case, because the memory banks are stored by the crossbar 516, the DAG/collector 5 〇3 can receive the blocks, and the blocks are provided to the depth of the vector data according to the base clock. 5〇4 front end. In this way, the specific embodiment of the present invention provides a novel visual Is architecture It supports complex video processing functions while effectively integrating the integrated circuit area, the total number of transistors, and the memory rate requirements. Embodiments of the present invention maintain high computational density and are easily scalable to handle multi-view streams. A specific embodiment of the present invention can provide a video processing operation, such as MPEG-2/WMV9/H.264 encoding co-J loop decoder, MPEG_2/WMV9/H.264 decoding (such as post-entropy solution and intra-loop/ An out-of-loop deblocking filter. An additional video processor package provided by a specific embodiment of the present invention, such as an advanced motion adaptive deinterlacing, and a 6-character input noise filter library, so that the unrealized non-60 1 Next, i, [8 episodes, used at each telegram, and some versatile (such as coder), wave, 31 1327434

Multiphase adjustment/resampling and subpicture synthesis. The video processor of the present invention can be used in some video processor-procamp applications such as spatial conversion, color space adjustment, pixel point operations (such as sharpening, map adjustment, etc.) and various video surface format conversions. In general and without limitation, the present specification has been disclosed below. A latent time allowing system for performing a video processing operation is shown. The system includes a host interface for authenticating between the video processor and a host CPU; a scalar execution unit coupled to the host interface and configured for line-quantity video processing operations; and a vector execution unit The host interface is coupled and configured to perform vector video processing operations. A command is included to allow the vector execution unit to operate on a demand driven basis by accessing a memory FIFO. A memory interface is included to implement communication between the video processor and a frame buffer memory. An engine is built into the memory interface for performing D Μ A transfers between a plurality of different locations and loaded into the command FIFO with the instructions for the vector execution unit. A video processor for performing video processing has been disclosed. The video processor includes a host interface for communicating between the processor and a host CPU. The memory surface is configured to perform a scalar execution unit coupling between the video processor and a frame buffer memory to the host interface and the memory interface and to perform a scalar video processing operation. A vector execution unit is called a host interface and a memory interface and is configured to perform vector video operations. A multi-dimensional data path processing system for performing a video processing operation for a video processor has been disclosed. The video processor includes a configuration to structure the color histograms, and to perform the FIFO command to use the DMA memory material and operate in the visual communication. Matching to the operation of the operation 32 1327434

A scalar execution unit of a scalar video processing operation, and a vector execution unit configured to perform a video processing operation. A data storage memory system package stores the data of the vector execution unit. The data storage memory includes a plurality of blocks having a symmetric memory data structure configured in an array. The library data structure is configured to support access to different partitions of each bank. A stream-based document access system for a video processor for performing video operations is disclosed. The video processor includes a scalar execution unit configured to perform a scalar video operation and a vector execution unit configured to perform vector video processing. A frame buffer memory system is included for storing data of scalar execution units and vector execution units. A memory interface includes communication between the scalar execution unit and the vector execution unit and the frame buffer memory. The frame buffer memory includes at least a plurality of block memory interfaces to perform a first sequential access of the block, and a second sequence of at least one block for the vector execution unit or the scalar execution unit is implemented. Second stream. The foregoing description of the specific embodiments of the invention has been presented The invention is not intended to be exhaustive or to limit the invention. The embodiment was chosen and described in order to best explain the principles of the invention way. The scope of the invention is intended to be defined by the scope of the appended claims and their equivalents. Quantitative Recollections have been recalled in the Department of Operational Memory 0. Included in the context of the syllabus> User 33 1327434 [Simplified illustration of the drawings] The present invention is exemplified by the drawings of the drawings without being limited thereto, and wherein The same reference element numbers refer to like elements, and wherein: * Figure 1 shows a schematic diagram illustrating the basic components of a computer system in accordance with an embodiment of the present invention. Figure 2 is a diagram showing the internal components of a video processing unit in accordance with an embodiment of the present invention. Figure 3 shows a diagram of an exemplary software program for a video processor in accordance with an embodiment of the present invention. Figure 4 shows an example of a sub-picture mixed with video using a video processor in accordance with an embodiment of the present invention. Figure 5 shows a diagram depicting the internal components of vector execution in accordance with an embodiment of the present invention. Figure 6 is a diagram showing the layout of a data storage memory having a symmetric block array in accordance with an embodiment of the present invention.

[Main component symbol description] 100 Computer system 101 CPU 105 Bridge component 110 Graphics processor unit / GPU 111 Video processor unit / VPU 112 Display 115 System memory 120 Component 201 Scalar execution unit 202 Vector execution unit 203 1 Recall Interface 204 Host Interface 205 Frame Buffer Memory 2 10 scalar processor 34 1327434 211 Instruction Cache 2 12 Data Cache 2 13 Vector Interface Unit 2 14 Sync Mailbox 220 Vector Control Unit 221 Vector Data Path • 222 Instruction 223 Data storage memory 225 «Command FIFO 23 1 Second vector data path - 233 Second data storage 300 Software program 301 sine control thread 302 Vector data thread 401 DMA engine 403 Stream Φ 412 Video surface / Luma parameter 4 13 Video Surface / Chro 414 Sub Picture Pixel Element 4 15 ARGBOUT 42 1 Line 422 Line 423 Line 424 Line 425 Line 430 Times Normal 501 Instruction Decoder 502 VLIW Instruction 503 Address Generator 504 Vector Data Depth 505 Integer unit 506 Branch unit 5 10 Legend 5 11 Data storage • 515 Address register File unit 5 16 Crossbar • 517 Fixed RAM 600 Memory ν 601- 6 04 Memory 610 Data storage 35

Claims (1)

1327434 Ua Day Butterfly Scale _ Case Supplementary Year Correction Pickup, Patent Application Range: 1. A system for video processing operations, the system includes: a scalar execution unit configured to perform a scalar video processing operation; a vector execution unit configured to perform a vector video processing operation; a data storage memory configured to store data of the vector execution unit, wherein The data storage memory includes at least a plurality of tiles, and the blocks include at least a bank data structure configured as an array, and wherein the memory data structures are configured to support Access to different partitions of each memory bank. 2. The system of claim 1, wherein the system is a multidimensional data path processing system for performing video processing operations. 3. A system for multidimensional data path processing to support video processing operations, comprising: a motherboard (motherboard); a host CPU coupled to the motherboard; a video processor coupled to the motherboard and coupled to the CPU and including the system of claim 1 . 4. The system of claim 1, 2 or 3, wherein each of the memory data structures comprises a plurality of blocks arranged in a 4x4 pattern. 36 1327434 i 4^23 5. The system of claim 1, 2 or 3, wherein each of said memory data structures comprises a plurality of blocks arranged in a pattern of 8x8, 8x16 or 16x24. 6. The system of claim 1, 2 or 3, wherein the memory data structures are configured to support access to different partitions of each memory data structure, and wherein the two phases are At least one access to the adjacent memory data structure includes one of the two adjacent memory data structures. 7. The system of claim 1, wherein the blocks are configured to support access to different partitions of each memory data structure, and wherein the two adjacent memories At least one access to the data structure includes a row partition of the two adjacent memory data structures. 8. The system as described in claim 1, 2 or 3 includes: A crossbar coupled to the data storage memory for selecting a block for configuring access to the plurality of memory data structures. 9. The system of claim 8, wherein the crossbar accesses the plurality of memory data structures to provide data to a vector data path based on each clock. 10. The system of claim 9, further comprising a collector, 37 1327434 The plurality of blocks of the plurality of memory data structures accessed by the crossbar are received, and the blocks are provided to a front end of the one of the vector data paths based on each clock. 11. A video processor for performing a video processing operation, comprising: a host interface for performing communication between the video processor and a host CPU; a memory interface for performing communication between the video processor and a frame buffer memory; a scalar execution unit coupled to the host interface and the memory interface, and configured to perform A singular video processing operation; and a vector execution unit coupled to the host interface and the memory interface and configured to perform a vector video processing operation. 12. The video processor of claim 11, wherein the scalar execution unit function is a controller of the video processor and controls operation of the vector execution unit. 13. The video processor of claim 11, further comprising a vector interface unit for causing the scalar execution unit to generate an interface with the vector execution unit. 14. The video processor of claim 11, wherein the scalar execution unit and the vector execution unit are configured to operate asynchronously. 38 1327434 卺/1 si repair {seven replacement page 15. The video processor of claim 14, wherein the quantity execution unit is executed according to a first clock frequency and the vector element is executed according to a second clock frequency. 16. The video processor of claim 11, wherein the quantity interface unit is configured to perform an application flow control algorithm. The vector execution unit is configured to perform pixel processing of the application. The video processor of claim 16, wherein the quantity execution unit is configured to operate on the basis of command driving under the control of the scalar execution unit. 18. The video processor of claim 16, wherein the quantity execution unit is configured to call the vector execution unit using a command FIFO transfer function, and wherein the vector execution unit causes the FIFO to be in demand by accessing Drive based on operation. 19. The video processor of claim 16, wherein the asynchronous operation of the processor is configured to support separate or independent updates of the one-time routine or the scalar sub-normal of the application. The video processor of claim 11, wherein the quantity execution unit is configured to operate the pure ir using the VLIW (very long instruction) code, and ‘made. The direction of the pure call to the life of the visual vector of the pure 39 1327434 21. A stream-based system for performing a video processor, the system comprising: a scalar execution unit configured to execute a pure d-vector execution unit, Configuring to: a frame buffer memory for storing metadata and the vector execution unit; and a memory interface for implementing the pure vector execution unit and the frame slow The inter-memory pass buffer memory includes at least a plurality of blocks, and wherein a first stream of the first sequential access including one of the blocks is used for the vector execution unit or the sequential access of the scalar execution unit The second stream. 2 2. A system for performing stream-based memory access, comprising: a motherboard; a host CPU coupled to the motherboard; a video processor coupled to the mother The video processor includes: a host interface for establishing communication between the video CPUs; a scalar execution unit coupled to the stream-based memory access t video processing operation; t video processing Operating the scalar, executing the scalar execution unit and the letter, wherein the 'frame' of the memory interface is implemented, and implementing a block containing one of the second compliant video processing operations coupled to the CPU, the processor and The host host interface is configured with 40 1327434 i. y/ί to perform a scalar video processing operation; a vector execution unit coupled to the host interface and configured to perform a vector video processing operation; a memory interface coupled to the scalar execution unit and the vector execution unit and configured to establish flow-based communication between the scalar execution unit and the vector execution unit and a frame buffer memory, wherein The frame buffer memory includes at least a plurality of blocks, and wherein the memory interface implements a first stream including one of the first sequential accesses of the block, and implementing one for the vector execution unit or the scalar The second stream of the second sequential access of one of the blocks of the execution unit. 23. The system of claim 2, wherein the first stream and the second stream comprise at least one prefetched title. 2. The system of claim 2, wherein the first flow system starts from a first position in the frame woven memory, and the second flow system buffers memory from the frame One of the second positions in the body starts. 25. The system of claim 21, wherein the memory interface is configured to manage a plurality of streams from a plurality of different starting locations and to a plurality of different termination locations. 26. The system of claim 25, wherein at least one of the starting positions or at least one of the ending positions is in a system 41 1327434 In memory. 2 7. The system of claim 21 or 22, wherein the DMA engine is configured to perform a plurality of memory readings in the memory interface to support the first stream and to implement the plurality of A memory write to support the first stream and 1 28. The system of claim 21 or 22, wherein the stream experiences a higher amount of latency than the second stream (the first stream combination in Latenc) A larger number of buffers than the second stream. 2 9. The system of claim 2, wherein the body interface is configured to prefetch the first stream or the second stream a number of blocks to compensate for the first stream or the second > 1 (Latency). A system for video processing operations, the system comprising: a host interface for use in the video The processor and an implementation communication; a scalar execution unit coupled to the host interface and performing a scalar video processing operation; a vector execution unit coupled to the host interface and performing a line vector video processing operation; comprising: In the second stream; in the second stream. A first y), and the host CPU which is arranged for storing in the memory when an adjustable potential to perform the ί configured to perform 421327434 a command FIFO for causing the vector execution unit to operate on a demand driven basis by accessing the command FIFO; a memory interface for buffering memory in the video processor and a frame Implement communication between the bodies; a DMA engine for establishing a DMA transfer between the plurality of different memory locations for loading DMA transfer between the plurality of different memory locations, and loading a data storage memory with data and instructions for the vector execution unit And an instruction cache. 3. A system as claimed in claim 30, wherein the system is a Latency tolerance system for performing video processing operations. 3. The system of claim 3, further comprising: a motherboard; a host CPU coupled to the motherboard; a video processor coupled to the motherboard and coupled to The CPU » The system of claim 30, 31 or 32, wherein the vector execution unit is configured to access the command FIFO to operate asynchronously with respect to the scalar execution unit, Drive based on operation. 34. The system of claim 30, 31 or 32, wherein the demand-driven infrastructure is configured to hide a different memory location from the same 43 1327434 Transfer to the data of the command FIFO of the vector execution unit. 35. The system of claim 30, 31 or 32, wherein the scalar execution unit is configured to perform an algorithm flow control process, wherein the vector operation unit is configured to perform a majority of video processing. a dive and its work 36. The system of claim 35, wherein the scalar unit is configured to pre-calculate a number of work for the vector execution unit to hide a data transfer latency. The system of claim 30, wherein the vector unit is configured to read a memory read via the DMA engine to prefetch commands for subsequent execution of a vector subroutine. . Execution process, 3. The system of claim 3, wherein the memory is scheduled to be prefetched for the vector subroutine before the unit call is performed to the routine by the scalar execution unit. The command to execute. The system of claim 32, wherein the vector unit is configured to read a memory read by the DMA engine for prefetching for subsequent execution of a vector subroutine. Command, and its memory reading is scheduled to be prefetched for execution of the vector subroutine before the vector subroutine is called to 44 1327434 by performing the unit call execution process by the scalar quantity a system for performing a video processing operation, comprising: a motherboard; a host CPU coupled to the motherboard; The video processor of claim 11 is coupled to the motherboard and coupled to the CPU. 41. The system of claim 40, wherein the scalar execution unit is executed at a first clock frequency and the vector execution unit is executed at a second clock frequency. The system of claim 40, wherein the scalar interface unit is configured to perform an application flow control algorithm, and the vector execution unit is configured to perform pixel processing operations of the application. 43. The system of claim 4, wherein the scalar execution unit is configured to call to the vector execution unit using a command FIFO transfer function, and wherein the vector execution unit accesses the command FIFO by Operate on a demand-driven basis. 44. The system of claim 42, wherein the asynchronous operation of the video processor is configured to support one of the applications of the vector subroutine 45 1327434 1327434 Patent No. 094140179 Patent Application Replacement Page ( October, 1996) 300 301 - J.l4 · Replacement page \ Quantitative data thread Parse_methods〇; setup_vector_engine〇; whi!e(!end_of_alg&!cind_fifo_full) { compute_param_.for_tHe{i) }_ send_params_to_vector〇; //mem RD fetch^.data_to_vector〇;3-// initiate RPC call on vector exe_vec_func(&amp ;vector_funcB); // mem write write_data_from-vector〇;j' 302 Vector data thread vector_funcA { vector_funcB { 1327434 Patent application No. 094140179 Chinese picture replacement page (96 years 1 month) 96.10. ϋ Year, month and day)) 0 1 4 5 2 3 6 7 4 5 0 1 6 7 2 3 610 Figure 6