1327346 九、發明說明： 【發明所屬之技術領域】 一種電路板之電性連接結構之製法，尤指一種在電路 板上形成兩種不同導電結構之製法，並可形成細線路間距 5 之電性連接結構。 【先前技術】1327346 IX. Description of the invention: [Technical field of the invention] A method for manufacturing an electrical connection structure of a circuit board, in particular, a method for forming two different conductive structures on a circuit board, and forming an electrical property with a fine line pitch of 5 Connection structure. [Prior Art]
10 15 20 隨著電子產業的蓬勃發展，電子產品之外型趨向輕薄 短小，在功能上則逐漸邁入高性能、高功能、高速度化的 研發方向。而覆晶式（Flip chip)半導體封裝技術為一種先進 之半導體封裝技術，在現行覆晶技術中，係於半導體積體 電路（Integrated Clrcuit ; IC)晶片的表面上配置有電極焊 墊，並於該電極焊墊上形成有焊錫凸塊，且在一有機電路 封裝基板上形成有相對應之電性連接塾與焊錫凸塊，俾提 供該晶觸面朝下的方式設置於該封裝基板上。 &由於越來越多的產品設計趨向於小型化、高速度、多 功旎’因&，覆晶技術的應用範圍將不斷擴大，成爲一種 標準的晶片封裝技術。同時為提升該些電子裝置之電性品 ::即需於其中設置有例如電阻、電容或電感等被動元件， 而该二被動元件同樣採用表面黏著技術10 15 20 With the rapid development of the electronics industry, the appearance of electronic products tends to be thin and light, and the functions are gradually entering the development direction of high performance, high functionality and high speed. Flip chip semiconductor packaging technology is an advanced semiconductor packaging technology. In the current flip chip technology, an electrode pad is disposed on the surface of a semiconductor integrated circuit (IC) chip. Solder bumps are formed on the electrode pads, and corresponding electrical connections and solder bumps are formed on an organic circuit package substrate, and the crystal contact surface is provided on the package substrate. & As more and more product designs tend to be smaller, faster, and more efficient, the application of flip chip technology will continue to expand, becoming a standard chip packaging technology. At the same time, in order to improve the electrical properties of the electronic devices, it is necessary to provide passive components such as resistors, capacitors or inductors, and the passive components also employ surface adhesion technology.
=板:使預焊錫凸塊與表面黏著型金屬連接元件並(I 彡成之焊錫㈣高度及尺寸並不相 有不_型之半導體元件之相配合電性導接。 而目別業界普遍使用化學沈積及模板印刷技術 6 1327346 (Ste—gTechnology)於基板上來形成焊锡材料。如 第1A圖至第1E圖所示，主要係於—具有複數電性連接塾 (pad)101的電路板丨〇覆上一有機絕緣保護層〗丨，如綠漆等防 焊層材料（solder mask)所構成，該絕緣保護層】i經时化繁 程而形成複數個開孔丨丨丨以顯露出該電性連接墊ι〇ι(如第 1A圖所示）；藉由_'_、無電⑽或化學 性連接塾⑻上形成-金屬黏著層12(如第1β圖所示）;、= 一具有網格13a之模板13於該電路板之部分電性連接塾⑻ 表面之金屬黏著層12以模板印刷方式形成—谭錫材料 M(如第糊所示）；最後再經由回焊（⑽叫製程以形成預 焊錫凸塊M，（如第聞所示），俾以在電性連接墊⑻上带 成兩種不同材質之預焊錫凸塊或焊錫材料。 / 15 20 但以模板印刷的方式形成凸塊或焊接锡球，形成 f越南’於後段的製程中所形成的高度不易控制，導致迴 ，後之凸塊或焊接錫球的高衫平均，而影響其電性連 2 =刷電路板’以及於該電路板之電性連接塾上印刷 形成凸塊或焊接錫球容易導致迴谭製程中過多 =材料㈣造成橋接現象及短路問題，而無法提供 之電性連接塾。同時大量使用焊錫材料亦面 者亟::進=述之問題，實已成目前電路板製造業 【發明内容】 7 板之==習it缺點，本發明提供-種半導體封裝基 路板係至少包括首先提供—電路板，而此電 -電性連接2 介電層表面形成至少-第 板表面形成1;:個弟：電性連接墊。接著，於此電路 第-開口盘第二=層’I中防焊層係形成至少一 墊，第一鬥、’口，弟一開口係顯露出第-電性連接 弟一開口係顯露出介電層與第二 於電路板及防焊層表面形成_導電層。 …、後 10 於第導電層表面形成一第一阻層，第-阻層可對應 开連接墊形成一第三開σ。然後，於第三開口内 y 夕—凸塊金屬層。再移除第一阻層。 "/成圖案化之第二阻層，此第二阻層對應於第 塾與第二電性連接塾分別形成至少-第四開口 及複數個第五開口。 15 一 ’’、、後⑨第四開口之凸塊金屬層表面及第五開口内之第 二=連接塾表面分別形成一金屬薄詹。最後，移除該第 :阻層及被該第二阻層所覆蓋之導電層，而形成具有一凸 塊區二及—表面黏著技術區之封裝基板。 20 7<由上述之方法，可減少習知使用網版印刷的技術， 無法將焊II材財效充類蓋於電性連料之間，致使電 性功能無法發揮°另亦可解決形成焊錫材料於半導體封裝 基板之電性連接塾表面在防焊層開口過小時無法使用網 版㈣的技術形成焊錫材料於開口中之電性連接塾表面之 問題。另’此方法在凸塊區形成之凸塊金屬層可調整凸塊 8 1327346 高度，代替習知使用大量的焊料，可減少材料及製造之成 本。 【實施方式】 5 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人式可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用’在不悖離本發明之精神下進行各 10 種修飾與變更。 請參閱圖2A至2H，係為本發明一較佳實施例半導體封 裝基板之剖面圖。 如圖2A所示，提供一電路板21，該電路板21係至少包 括有一介電層211，該介電層表面形成至少一第一電性連接 15 墊212a及複數個第二電性連接墊212b。其中，介電層211使 用之材料可選自 ABF(Ajinomoto Build-up Fiim )、 BCB(Benzocyclo-buthene) > LCP(Liquid Crystal Polymer) ' Pl(Poly-imide)、PPE(Poly(phenylene ether))、PTFE(Poly (tetra-fluoroethylene))、FR4、FR5、BT(Bismaleimide Tri-20 azine)、芳香尼龍（Aramide)等感光或非感光有機樹脂，或亦 • 可混合環氧樹脂與玻璃纖維等材質所組成之群組。在本實 施例中係使用ABF。而第一電性連接塾與第二電性連接塾 使用之材料可為銅、錫、鎳、鉻或鈦，在本實施例中係使 用銅。 9 1327346 • 再於4電路板21表面形成—®案化之防焊層22,而防焊 層之材料可為-感光及聚縮錫性之樹脂，例如綠漆或里 漆’ f中，該防焊層22係以曝光及顯影之圖案化方式形成、 ^少H 口221與第二開σ 222，第—開口221係顯露出 5弟-電性連接塾212a，第二開口如係顯露出介電層叫與 第二電性連接墊212b。 、 如圖2B所示，於電路板21及防焊層22表面以化學沈積 及物理沈積之其中一種方式形成一導電層23,而該化學及 ►物理沉積方式可例如為無電解電鑛或_等。其中，該導 10電層23主要係作為後述進行電鍍製程之電流傳導路徑，其 使用之材料可為銅、錫、錄、鉻或鈦，在本實施例係使用 銅。 如圖2C所示，於該導電層23表面形成一第一阻層24， 第一阻層24使用之材料可為乾膜或液態光阻，較佳地本實 15施例係使用液態光阻，其對應於該第一電性連接墊212a可 經由曝光及顯影之圖案化方式形成一第三開口 241。 如圖2D所示，於該第三開口 241内經由電鍍方式形成至 少一凸塊金屬層25,而該凸塊金屬層25使用之材料可為 銅、錫、鉛、銀、鎳、金、鉑或其合金，在本實施例中係 20 使用銅。接著，如圖2E所示，移除該第一阻層24。 如圖2F所示，形成一圖案化之第二阻層26，其可使用 之材料為乾膜或液態光阻，較佳地本實施例係使用液態光 阻，該第二阻層26對應於該第一電性連接墊212a與該等第 二電性連接墊212b分別經由曝光以及顯影之圖案化方式形 1327346 成至V 第四開口 261及複數個第五開口 262a，262b。 :1如圖2G所示，於該第四開口261之凸塊金屬層乃表面及 該等第五開口 262a，262b内之第二電性連接墊212b表面分別 I由電鍍方式形成一金屬薄層27，且此金屬薄層27使用之 5材料較佳可為銅、錫、銀、金 '錄/金、錄/纪/金或其類似 物等材料。 最後，如圖2H所示，移除該第二阻層16及被該第二阻 • 斤復蓋之、電層23，而形成具有一凸塊區28a具有以及 •—表面黏著技術區28b之封裝基板。 10 在此值得注意的是，請參考圖3，係為本實施例中， 形成於表面黏著技術區之電性連接墊之上視圖。在本發明 之λ施例中’表面黏著技術區28b之第二電性連接墊 212b(如圖2H所不），其形成於介電層211表面的形狀係可為 矩形之形狀，而與其一側之線路連接。 15 、’’’T、上所述，本發明可避免習知使用網版印刷的技術， ,、.、法將谭錫材料有效充填覆蓋於電性連接塾之間，致使電 11 1 +生功能無法發揮。另亦可解決形成焊錫材料於半導體封裝 基板之電陡連接塾表面在防焊層開白過小時，無法使用網 版Ρ刷的技術形成焊錫材料於開口中之電性連接塾表面之 20門題另此方法在凸塊區形成之凸塊金屬層可調整凸塊 .高度，代替習知使用大量的焊料，可減少材料及製造之成 本而在表面技術黏著區使用阻層（例如乾膜或液態光 阻尤4曰液癌光阻）來進行電錄金屬製程以代替習知之網板 印刷，電性連接塾之密度而增加電性品f。 1327346 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準而非僅限 於上述貫施例。 【圖式簡單說明】 圖1A及1E係習知半導體封裝基板之表面電性連接墊佈 5又結構剖面圖。 圖2A至2H係本發明一較佳實施例之半導體封裝基板 10 之剖面圖。 土 圖3係本發明之半導體封裝基板中，形成於表面黏著技 術區之電性連接墊之上視圖。= plate: the pre-solder bump and the surface-adhesive metal connecting component (I) solder (four) height and size do not have the same type of semiconductor components with the electrical connection. Chemical deposition and stencil printing technology 6 1327346 (Ste-gTechnology) is used to form a solder material on a substrate. As shown in Figures 1A to 1E, it is mainly used for a circuit board having a plurality of electrical pads 101. Covered with an organic insulating protective layer, such as a green paint and other solder mask material, the insulating protective layer] i formed over time to form a plurality of openings to reveal the electricity a connection pad ι〇ι (as shown in Fig. 1A); forming a metal adhesion layer 12 by _'_, no electricity (10) or a chemical connection 塾(8) (as shown in Fig. 1); The template 13 of the grid 13a is partially formed on the surface of the circuit board. The metal adhesion layer 12 on the surface of the board (8) is formed by stencil printing - tan tin material M (as shown in the paste); finally, by reflow soldering ((10) is called the process Forming a pre-solder bump M, (as shown in the figure), in the electrical connection pad (8) Pre-solder bumps or solder materials in two different materials. / 15 20 However, the formation of bumps or solder balls by stencil printing forms a height that is not easily controlled in the process of the rear section of Vietnam. , after the bump or soldering the ball of the high shirt average, and affecting its electrical connection 2 = brush circuit board 'and the electrical connection on the board to form bumps or solder balls is easy to lead to the process Too much = material (4) causes bridging and short-circuit problems, but can not provide electrical connection 塾. At the same time, the use of a large number of solder materials is also a problem: the problem of the introduction, has become the current circuit board manufacturing industry [invention content] The invention provides a semiconductor package substrate board comprising at least a first circuit board, and the surface of the dielectric layer 2 is formed at least - the surface of the first board is formed 1; Younger brother: electrical connection pad. Next, the solder mask layer of the second-layer 'I of the first-opening plate of the circuit forms at least one pad, and the first bucket, the mouth, and the opening of the brother reveal the first electrical property. Connecting the younger brother’s opening system reveals the dielectric Forming a first conductive layer on the surface of the conductive layer with the second conductive layer formed on the surface of the circuit board and the solder resist layer, and the first resist layer may form a third opening σ corresponding to the opening pad. In the third opening, the y-bump metal layer is removed, and the first resist layer is removed. "/ patterned second resistive layer, the second resistive layer corresponding to the second and second electrical connections respectively Forming at least a fourth opening and a plurality of fifth openings. The surface of the bump metal layer of the fourth opening of the fourth opening and the second surface of the fifth opening of the fifth opening form a thin metal. And removing the first: the resist layer and the conductive layer covered by the second resist layer to form a package substrate having a bump region 2 and a surface adhesion technology region. 20 7< By the above method, the conventional technique of using screen printing can be reduced, and the welding efficiency of the welding material II cannot be filled between the electrical materials, so that the electrical function cannot be exerted. The problem that the material on the surface of the electrical connection of the semiconductor package substrate is too small when the solder resist layer is too small to form the solder material in the opening is formed by the technique of the screen (4). In addition, the bump metal layer formed in the bump region can adjust the height of the bump 8 1327346, instead of using a large amount of solder, which can reduce the material and manufacturing cost. [Embodiment] 5 The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present specification. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. 2A to 2H are cross-sectional views showing a semiconductor package substrate in accordance with a preferred embodiment of the present invention. As shown in FIG. 2A, a circuit board 21 is provided. The circuit board 21 includes at least one dielectric layer 211. The surface of the dielectric layer forms at least a first electrical connection 15 pad 212a and a plurality of second electrical connection pads. 212b. The material used for the dielectric layer 211 may be selected from the group consisting of ABF (Ajinomoto Build-up Fiim), BCB (Benzocyclo-buthene) > LCP (Liquid Crystal Polymer) 'Pl (Poly-imide), PPE (Poly (phenylene ether) ), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Tri-20 azine), aromatic nylon (Aramide) and other photosensitive or non-photosensitive organic resins, or also can be mixed with epoxy resin and glass fiber, etc. A group of materials. In this embodiment, ABF is used. The material used for the first electrical connection and the second electrical connection may be copper, tin, nickel, chromium or titanium, in the present embodiment copper is used. 9 1327346 • A solder resist layer 22 is formed on the surface of the 4 circuit board 21, and the material of the solder resist layer may be a photosensitive/poly tin-resin resin such as green paint or lacquer 'f. The solder resist layer 22 is formed by patterning by exposure and development, and has a small H port 221 and a second opening σ 222. The first opening 221 reveals a 5th-electrical connection port 212a, and the second opening is exposed. The dielectric layer is called a second electrical connection pad 212b. As shown in FIG. 2B, a conductive layer 23 is formed on one of the surface of the circuit board 21 and the solder resist layer 22 by chemical deposition and physical deposition, and the chemical and physical deposition methods may be, for example, electroless ore. Wait. The conductive layer 23 is mainly used as a current conducting path for performing an electroplating process as described later, and the material used therein may be copper, tin, copper, chromium or titanium. In the present embodiment, copper is used. As shown in FIG. 2C, a first resist layer 24 is formed on the surface of the conductive layer 23. The material used for the first resist layer 24 may be a dry film or a liquid photoresist. Preferably, the liquid resist is used in the embodiment. Corresponding to the first electrical connection pad 212a, a third opening 241 can be formed by patterning by exposure and development. As shown in FIG. 2D, at least one bump metal layer 25 is formed in the third opening 241 by electroplating, and the bump metal layer 25 may be made of copper, tin, lead, silver, nickel, gold or platinum. Or an alloy thereof, in the present embodiment, 20 is copper. Next, as shown in FIG. 2E, the first resist layer 24 is removed. As shown in FIG. 2F, a patterned second resist layer 26 is formed, which can be made of a dry film or a liquid photoresist. Preferably, in this embodiment, a liquid photoresist is used, and the second resist layer 26 corresponds to The first electrical connection pads 212a and the second electrical connection pads 212b are formed into a V fourth opening 261 and a plurality of fifth openings 262a, 262b by patterning 1327346 respectively through exposure and development. As shown in FIG. 2G, the surface of the bump metal layer of the fourth opening 261 and the surface of the second electrical connection pad 212b in the fifth openings 262a, 262b are respectively formed by electroplating to form a thin metal layer. 27, and the material of the metal thin layer 27 is preferably made of copper, tin, silver, gold, gold, gold, gold, gold or the like. Finally, as shown in FIG. 2H, the second resist layer 16 and the electrical layer 23 covered by the second resistor are removed to form a bump region 28a and a surface adhesion technology region 28b. Package substrate. 10 It is worth noting here that please refer to FIG. 3 , which is a top view of the electrical connection pad formed in the surface adhesion technology zone in this embodiment. In the λ embodiment of the present invention, the second electrical connection pad 212b of the surface adhesion technology region 28b (as shown in FIG. 2H), the shape formed on the surface of the dielectric layer 211 may be a rectangular shape, and one of them Side line connections. 15、''T, as described above, the present invention can avoid the conventional technique of using screen printing, and the method can effectively fill the tin-tin material between the electrical connection ports, so that the electricity is 11 1 + The function cannot be played. In addition, it can also solve the problem that the soldering material is formed on the surface of the semiconductor package substrate, and the surface of the soldering layer is too small to be used, and the technique of using the screen brush can not form the surface of the electrical connection of the solder material in the opening. In addition, the bump metal layer formed in the bump region can adjust the bump height, instead of using a large amount of solder, which can reduce the cost of materials and manufacturing, and use a resist layer (such as dry film or liquid) in the surface technology adhesive region. Photoresist, especially liquid cancer, is used to replace the conventional screen printing, and the density of the electrical connection is increased to increase the electrical property f. 1327346 The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1E are cross-sectional views showing the structure of a surface electrical connection pad 5 of a conventional semiconductor package substrate. 2A through 2H are cross-sectional views of a semiconductor package substrate 10 in accordance with a preferred embodiment of the present invention. Figure 3 is a top view of an electrical connection pad formed in a surface mount technology region in a semiconductor package substrate of the present invention.
11 12 13a 【主要元件符號說明】 1Q，21電路板 絕緣保護層 金屬黏著層 網格 預焊錫凸塊 212a 第一電性連接墊 22 防焊層 222 第二開口 24 第一阻層 25 凸塊金屬層 101 電性連接墊 in 開孔 13 模板 14 焊錫材料 211 介電層 212b第二電性連接墊 221 第一開口 23 導電層 241 第三開口 26 第二阻層 12 1327346 261 第四開口 262a，262b 第五開口 27 金屬薄層 283. 凸塊區 28b 表面黏著技術區11 12 13a [Description of main component symbols] 1Q, 21 circuit board insulation protective layer metal adhesion layer grid pre-solder bump 212a first electrical connection pad 22 solder resist layer 222 second opening 24 first resist layer 25 bump metal Layer 101 Electrical connection pad in Opening 13 Template 14 Solder material 211 Dielectric layer 212b Second electrical connection pad 221 First opening 23 Conductive layer 241 Third opening 26 Second resist layer 12 1327346 261 Fourth opening 262a, 262b Fifth opening 27 metal thin layer 283. bump area 28b surface adhesion technology area
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