TWI325538B - Storage enclosure control system and chip thereof - Google Patents

Description

1325538 MIC2006-231 21969twf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a storage box control system, and more particularly to a storage box control system for displaying a hard disk state and its storage The cabinet controls the wafer. [Prior Art]

Serial Connection SCCI (serial attached SCCI) is the next generation of SCSI

(Small Computer System Interface) interface, referred to as SAS, aims to improve the performance, scalability and reliability of the storage system, while providing compatibility with large-capacity SATA hard drives and dual-port, high-performance SAS hard drives, mainly locked = Server and workstation market. With the demand for large storage capacity, multiple hard disks must be set on the server to meet the needs of users. Therefore, ^ It ^ ^ ^ (storage enclosure processor, ® n SEP)-th requires more I/ The O pin is responsible for displaying the status of the hard disk.

In the conventional technology, the number of hard disks that can be supported is usually increased by using the "〇 expansion chip, VSC055. VSC056 (Vitesse Semic〇nductor C〇rp〇ration „ =). Therefore, SEp can be displayed via ι/〇 The chip to display the operating status of more hard disks == is expensive, and can not be based on user needs = energy box Zhao: two: Zhao = chip 'can be used to store the operating state of the disk., the memory processor can display more More Hard The present invention provides an interface for a storage box control chip, which can be used to reduce the storage box control system by using a complex programmable logic element. Design cost. Chengqi provides a storage box control system, which utilizes the operation status of complex multiple hard disks. The knives and months are not (4) ^ to achieve the above and other purposes, this correction - miscellaneous storage box control = box The control system includes a processor (eg, a storage box)

The Si storage box controls the wafer, wherein the _ heart_|, the operating state of the disc, the plurality of hard disks are placed on the backboard. The storage π is used between the processor and the backplane to control the backplane: t where the processing buffer (4) is used to detect the operating state of the hard disk. In the invention, the tree-box control wafer can be controlled by a complex programmable logic two-banked wafer for the storage box======================================================== Judging that the external device controls the storage box body to control a third pin': two receiving is a storage box processor; and one of them:: a label to select the plurality of hard disk signals, the storage box (four) s ^ (four) four pins '帛Adjust the lamp number to adjust multiple lampsΪ=Target signal and lamp number control signal. This month, another, the above storage box control crystal 6 MIC2006-231 21969twf.doc/006 Receive-Preset signal' The storage box controls the crystal signal, and sequentially drives the motor of the hard disk; the plurality of enabling pins enable the motor of the plurality of hard disks; and the sixth pin outputs the data of the hard 2=f: piece state a plurality of seventh pins for predicating: = another shape-shaped secret disc is ---; and a plurality of eighth pins for indicating the display state of the hard disk . Control the interface of the wafer with a set of storage boxes, so

At ^ 壬 壬 logic elements to expand the I / O memory of the health box processor The processor can display more hard disk operating status, while reducing storage (4) control pure design costs. The above and other objects, advantages, and advantages of the invention will become more apparent from the detailed description of the invention. The system of the storage box control system implemented in the first month comprises a processor u〇, a storage box body control device 2, and a f back plate 130 'where the processor n〇 can be a storage box The processor responsible for storing the cabinet is controlled, and the back panel 130 is used for a hard disk. The storage box control chip 120 is secreted between the processors 110 130 to control the lights 131 to 139 on the backplane 130 to display the operating state of the hard disk on the backplane 13G or = eight ^,, and the lights 131 to 139 on the backplane 13 () i4i~149 LE "consisting of one or more light emitting diodes (1) 凼 Emitting Diode. The hard disk controller 14 〇 is coupled to Between the processor lio and the backplane 1325538 MIC2006-231 21969twf.doc/006 hard disk 'processor 110 can be controlled by the hard disk controller, such as reading and writing data, or directly through the hard disk controller, please Support SAS interface, so the backplane = installed a SAS hard drive, while the hard drive control _ 14 〇 can control the sas hard drive. The judgment of the operating state of the tree, the processor ιι〇 can ==f know, then Then, the display state of the lamps 131 to 139 is adjusted via the storage box, for example, a combination of flashing, bright, and no sorrow, etc. The user can judge the current hard by the "No" of the lights 131 to 2 The operation of the disc =: Whether the hard disc is set on the backboard 13. After the upper, the heart of the second pass is passed to the storage box control crystal 120, the storage box suppresses the flaky heart. In the present example, each hard disk corresponds to two lights, and the table does not set the state and operation state of the hard disk, for example, by ==r. In another embodiment of the present invention, the same state and the operating state may be used, which are the related media of the second=face===== of the invention, wherein the processors may be connected to each other. _For communication, and 3g and health 8 1325538 MIC2006-231 21969twf.doc/006 'The number of pins used between phase control chip 12G is based on the number of hard disks and the number of displayed lights The signal #u transmitted between the β process benefit 110 and the storage box control chip 120 includes the confirmation signal STRB, the read/write signal Na, the target signal tar, the signal control signal MODE, the preset signal PRE, and the status. The data SDa. The processor 110 outputs the read/write signal r/w, the target signal TAR, the signal control signal LC, the preset signal PRE to the storage box control chip call 12G' and the acknowledge signal STR_ by the processor UG Both the storage box control wafer 120 and the storage box control wafer 120 are shared by time, and the status data is stored. The body control chip 120 is output to the processor H. In the present embodiment, the 'pin Ρ is responsible for transmitting the confirmation signal STRB, and the confirmation signal STRB is for confirming whether the hard disk is disposed on the backplane 13 。. 110 output read signal STRB to the storage box control chip ^ processor in a negative edge trigger (falling edge trigger), the storage box control wafer, at this time, the confirmation signal STRB enable _ period is about 14 〇 Between ns and 350 ns. When the storage box control chip 120 outputs the confirmation signal STRB to the processor 110, the storage box control wafer 120 triggers the processor 110 in a manner to control the length of the negative edge period. At this time, the enable period of the confirmation signal STRB is approximately Between 700ns and 3500ns. The pin h is responsible for receiving the read/write signal R/W, and the storage box control crystal 1 120 determines, by the logic state of the read/write signal Ryw, that the processor 11 () is currently performing a read operation on the storage box control wafer 120 or It is a write action (for example, high logic level means read, low logic level means write). Pins P3 to P7 are used to receive the target signal TAR to select one of the target hard disks of the hard disk 9 1325538 MIC2006-231 21969twf.doc/006, and the processor 110 transmits the target signal via the target signal. The target hard disk to be processed is ^32 db, and the example: since the logical state of the receiving ~P7 combination has the 5th power of P, it can support up to 32 hard disks.

'Storage box control crystal> 12G can be based on the target signal TA

In order to select the hard disk to be set - and perform the corresponding action light signal _ horse _ start). . Of course, in the other embodiment of the present invention, the storage box control wafer 12G can increase or decrease the number of pins of the target signal TAR according to the usage to match the number of hard disks to be connected.

. The pins h and P9 are used to receive the lamp number control signal m〇de, and the lamp number in the display state of the lamp number is not in the (four) hard disk state. Since there are four logical state combinations of the pins p8 and p9, the four-sided state can be indicated separately, for example, light, no light, and flash _. In conjunction with the target signal TAR and (4) money MQDE, age touch (four) wafer ^ can know the current display status of the Nana-light, the different lights correspond to different target hard drives. If you need to indicate more display status, you can set more pins to receive the signal control signal ^M〇DE. In this embodiment, each hard disk corresponds to two lights, one of which is based on the operating state of the light (4) money M〇DE ageing old disk, and the other light number indicates whether the hard disk is set to On the backboard 13 (), the light can be directly set according to the signal of the bribe of the backboard 13 (4). The pin P1G is used to connect (4) the signal PRE, and the storage box control chip 120 sequentially drives the motor of the hard disk according to the preset signal PRE. In the embodiment of the present invention, the storage box control chip (4) uses the pins pn~pu to output the hard disk preset signal HPRE to sequentially enable the motor of the hard disk. For example, if you connect a 24^ hard disk, each pin will be responsible for 6 motors. Of course, you can also adjust the number of hard disks that each pin is responsible for or the pin that is responsible for enabling the hard disk. The number of pins, and the interval between the P"~P14 enable can vary depending on the system. Therefore, as long as the processor 11 enables the preset signal PRE, the storage box control chip 120 sequentially enables the hard disk on the backplane 13 to prevent the hard disk motor from being activated at the same time, thereby causing the system power load to be excessive. In addition, the Pi5 is a test pin, and the processor 110 can obtain the test status data p〇-12 of the storage box control chip through the pin pi5 to confirm whether the storage box control chip 12 is operating normally. Pin PN+1~? The signal is used to detect the setting state of the hard disk, N is a positive integer, and the pins Pn+i~P2n are one-to-one with the hard disk. The backplane 130 outputs the detection signal SAS_IN to the pins pN+1~P2Nj according to the setting of the hard disk, and the storage box control chip 120 receives the signal according to the pin pN+1~p2N, and displays it by the light number. The setting status of each hard disk, for example, the light number is not set correctly, the light number is not bright, indicating that the light is not set correctly or has not been set, and the storage control chip 120 can control the light through the pins P3N+i~p4N. 5 tiger's display state, its output control signal is collectively referred to as the set signal SAS-ON, as shown in Figure 2. The number of pins ρΝ+ι~ρ2Ν and pin 丨p state is determined according to the number of hard disks, which is one-to-one in this embodiment. In addition, the 'pin P2N+1~ can be used to control other lights, for example, the lights 131 to 139 indicating the operating state of the hard disk. In the present embodiment, the signals for adjusting the display states of the lights 131 to 139 are collectively referred to as the operation signal 11 1325538 MIC2006-231 21969twf.doc/006 ❹ ( 四 四 四 四 四 四 四 四 四 四 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 12 = 12 12 12 12 12 . In this embodiment, the storage box control chip 120 is illustrated by taking one of the pins as an example, but the present invention does not limit the number of pins on the wafer, and the number of pins used to implement each of the Weishen® is set. Can be appropriate

Adjustments, those of ordinary skill in the art, should be readily inferred by the disclosure of the invention, and are not described herein. In the other embodiment of the present invention, the memory control crystal of the present invention can be realized by a complex programmable logic device (CPLD) according to the description of Fig. 2 described above. 3 is a pin diagram of a complex programmable logic element in accordance with another embodiment of the present invention. In this embodiment, the CPLD of the Xilinx XC128 series is taken as an example to illustrate how the present invention implements the interface of the storage box control chip with the CPLD. Figure 3 (a) ~ (c) respectively indicate the interface function that the pins of the CPLD are responsible for. Please refer to FIG. 3(a) to (c) at the same time. Pins 1/〇94~98, 1〇〇~113, 115~U5 are used to receive the detection signals SAS1_IN~SAS24_IN' from the backplane. The detection signals SAS1_IN~SAS24_IN are respectively set on 24 hard disks. The status 'is to reflect whether 24 hard disks are correctly set on the backplane. The CPLD outputs a setting signal SAS1_ON~SAS24_ON according to the detection signals SAS1_IN~SAS24 IN to display the setting status of the hard disk on the light (for example, light indicates correct setting, and no light indicates no breaking setting), The setting signal SAS1-ON~SAS24_ON is output by the pins 1/02~7, 9~21, 22~24, 129~130, and each 12 1325538 MIC2006-231 21969twf.doc/006 pin is responsible for adjusting one. The lights, each of which corresponds to the setting state of a hard disk. In addition, pin 1/070 is used to receive the acknowledgment signal STRB, and pin 1/071 is used to receive the read and write signals. Pins 1/〇74, 76 are used to receive the lamp number control signals M0DE1, 2, so the corresponding lamp number can have four display state changes. The pins 1/077 to 81 are used to receive the target signals TAR0~4' with a logical combination of the target signals TARO~4, for example, their values, up to 32 hard disks can be identified, and in this embodiment only 24 of them are used. To identify the hard disk of 24, the hard disk selected is called the hard disk. If you need to identify more hard disks, you can increase the number of bits of the target signal and the number of pins received as required by the design. The preset signal pRE is received by the pin 1/087. When the preset signal PRE is enabled, the CPLD rotates the hard disk preset signals HPRE1 to HPRE4 via pins 1/081 to 83, 85, 86, each of which A hard disk preset signal is negatively capable of 6 hard disks, and the hard disk motor is sequentially enabled in time interval.

The operation signals BAY1JFAULT to BAY24 FAULT for displaying the operating status of the hard disk are connected by pins 1/025, 26, 28, 30, 35, 39, 4〇, 41, 43, 45, 49 to 54, 56 to 61, 68. 69 is responsible for the output. According to the target signal TAR〇~TAR4 and the signal adjustment signal Μ〇^, 2, the CPLD is in accordance with the 24-valve number, and each-Jinlin should be in one item, and the hard disk is used to indicate the operating state of the target hard disk. The pin/〇9ι is the test pin, and the read storage box controls the job status data P0J2 of the chip. The other pins are the power pin, the ground pin or the program write pin, etc. The technical function of the present invention is not limited by the pin sequence of the embodiment of FIG. 3, since the function of the (4) pin can be determined according to the design requirements according to 13 1325538 MIC2006-231 21969 twf.doc/006. As shown in FIG. 4 and FIG. 5, the circuit for assisting in detecting the state of the hard disk and the setting state on the backplane is shown in FIG. 4 and FIG. 5. FIG. 4 is a circuit diagram of the hard disk detection according to an embodiment of the present invention, which mainly uses the output of the hard disk. The setting signal HDOUT is compared with a preset voltage (the voltage division of the resistors R3 and R4), and the flag #SAS_IN is outputted. Therefore, the output of the comparator 41〇 changes if the hard disk 9 is set correctly or not. The storage box control chip can adjust the display of the light according to the detection signal SAS-IN. Of course, each hard disk requires a configuration-group hard disk_circuit, and its implementation details are not described herein. FIG. 5 is a hard disk motor enabling circuit according to another embodiment of the present invention. In the fifth embodiment, the 'light emitting diode 51' will emit light when the hard disk preset signal hpre is enabled, because when the hard flip HPRE is enabled, the motor enable signal SPIN is enabled, correspondingly The hard disk motor (4) starts running.

When the PNP transistor B51 is turned off by the motor enable signal spiN, the current required for the light is formed by the light-emitting diode and the resistors R8 and R9 forming a new conduction path. The circuit of Leeguan 5 can be directly produced by the backplane = the number of lights that can be identified, and it is directly judged that the motor of the hard disk has started to operate. Using ΐ 明 因 订 订 — — — 面 面 面 面 面 面 面 面 面 面 面 面 面 13 13 13 13 13 13 13 13 13 13 13 13 13 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 面 13 13 13 13 13 13 13 13 13 13 .doc/006 Although the present invention has been exemplified above, it is not intended to limit the invention to any of the ordinary skill of the art, without departing from the spirit and scope of the present invention. Therefore, the subject matter of the invention is subject to the definition of the application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the implementation of the present invention - the implementation of the age control (four) system. 2 is a pin diagram of a storage case control wafer in accordance with another embodiment of the present invention. 3 is a pin diagram of a complex programmable logic element in accordance with another embodiment of the present invention. 4 is a diagram showing a hard disk detecting circuit according to an embodiment of the present invention. FIG. 5 is a hard disk motor enabling circuit according to another embodiment of the present invention. [Main component symbol description] 100: Storage box control system 11: Processor 130: Backplane 120: Storage case control chip 130 to 139, 141 to 149: Light number 140: Hard disk controller 51: Light emitting two Polar body 410: Comparator STRB: Acknowledgement signal 15 1325538 MIC2006-231 21969twf.doc/006 R/W: Read/write signal, TAR, TARO~4: Target signal MODE, MODE1, 2: Signal control signal PRE: Preset Signal HPRE, HPRE1~HPRE4: Hard disk preset signal P0_12: Test status data BAY_FAULT: Operation signal BAY1_FAULT~BAY24_FAULT: Operation signal SAS ON, SAS1 IN~SAS24 IN: Set signal — SAS_IN, SAS1_IN~SAS24JN: Detection signal HDOUT : Set signal SPIN: motor enable signal

Pi~P4N, I/O2-I/O140: Pin B51: PNP transistor R1~R9: Resistor M51: NMOS transistor CbC2: Capacitor VCC: Operating voltage GND: Ground terminal 16

Claims (1)

1325538 MIC2006-231 21969twf.doc/006 Patent Application Park 1. A storage box control chip, comprising: a first pin for receiving a confirmation signal with the wheel, in a set state of a hard disk; The second pin 'is used for receiving-reading and writing signals to determine the read/write command for the storage box control chip; I==the third pin for receiving the target signal to select the disc, a target hard disk; and ''a plurality of fourth pins for receiving a signal control signal, the control crystallized according to the target money and the verification commission to rectify a plurality of lights Displaying the state, the above-mentioned first corresponds to the target hard disk; the first light number of the current /, one of the first light numbers corresponds to the display state of the hard disk 'the storage box control piece U of the first-light number The operation of the hard disk is as follows: 2. The storage box control chip according to the first aspect of the patent application, the fifth pin is configured to receive a preset signal, and the storage box controls the s chip according to the preset. The signal, the motors of the hard disks are sequentially enabled. 3. The storage box control chip described in claim 2, further comprising: a virtual enable pin "per touch" (four) corresponding to the hard disk, the listen According to the signal, the pin sequentially causes the motors of the hard disks. 17 1325538 MIC2006-231 21969twf.doc/006 The data package includes the storage box control chip described in item 1 of the patent scope, and the sixth pin for outputting the state of the storage box control chip. For example, the storage box difficult to manufacture the wafer according to the first item, wherein the storage box control chip further comprises: = a seventh lion, the use of the hard disk is set to the seventh pin and the The hard disks are one-to-one; and ~ are multi-pins, according to the signals received by the seventh pins, the display state of the control-to-j number, the second light number and the state of the hard disks are == = : using the second light number · the second storage _ system wafer, the processing body " film processing 11 and the backplane, the read and write 3: 'hard disk operating state, and output The confirmation signal, the back=, the target (4) and the signal control signal, the hard disk sets the storage first position on the backboard, and the processor adjusts the backplane by controlling the wafer The first number of lights to indicate the operating state of the target hard disk. Including, as described in item 1 of the patent scope of Zhongming, (4) box control wafer 'state data test pin' rib transfer (four) storage button control test pattern 18 1325538 MIC2006-231 21969twf.doc/〇〇6 8. The storage case control chip described in claim w, wherein the hard disks support a SAS interface. 9. The storage enclosure control wafer of claim 3, wherein the storage enclosure control wafer is a complex programmable logic component. = The storage box control wafer as described in claim 1 (4), wherein the display states of the first-numbers include _, bright or no light. a storage box control system, comprising: a processor for determining the operation of a plurality of hard disks on a backplane; and a storage tray (four) W, secretive to the processing 11 and the The backplane is used to control a plurality of first lights on the backboard; the second panel is: the buffer is controlled by the storage box to adjust the backlights to display the operating bears of the hard disks. . Output, signal (STRB), slanted two, two pins, used to receive a read and write signal to determine an external pair, the storage box controls the read and write commands of the chip; the external device is equipped with a pin 'to touch _ target domain, to select the singer: its - target hard disk; and k select the hardware ^ ton foot to receive - (four) control age number, the health gamma body control chip according to the target signal and the The storage phase-light number of which H industry can, the xenon lamp _5 唬 adjust the state of the first, the first light 19 1925538 MIC2006-231 21969tw£doc/〇〇6 corresponds to the target A hard disk, wherein the first light numbers correspond to the hard disks, and the storage box control chip indicates the operating states of the hard disks by the display states of the first lights. 13. The storage box control system of claim 12, wherein the storage box control crystal moon further comprises a fifth pin for receiving a preset signal, the storage box control The chip sequentially enables the motors of the hard disks according to the preset signal. The storage box control system of claim 13, wherein the storage box control chip further comprises: · an enable pin 'each-these enable pins respectively correspond to the The hard part of the hard disk, these enable the lion preset signal, in order to order the hard drive motor. 7 system, the material storage control system described in Item 12, first of which the storage box control chip further includes: data. The sixth pin, the ribs lose the bribe and save the box control crystal > 5 - the state control system is the seventh disc rr:: the setting state of the disc, the ^ J, Μ and the number of the first root $ these The signal received by the seventh pin, the control-to-the-state, the (four) two-slot and the hard disk are 20 1325538 1325538 MIC2006-231 2l969twf.doc/〇〇6 state to indicate that the second lamp is utilized The display material of the number. Measure 4 connected nx output · save the state of the butterfly w, ir / board special package 第 第 第 第 健 健 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制Is it correct to set the storage box control system as described in Item 11? Continued ==/The storage box control system described in item 11 of the patent scope = where the thief is confusingly--(four) two = == According to the r number control signal and the target, the display state of the first lights should be adjusted. The storage box control system as described in item 11 of the H patent scope is controlled according to the disk box - 21 1325538 MIC2006-231 21969twf.doc/006 23. If the scope of the patent scope is a, it should be hard Disk domain SAS interface. = Sub-phase control system, sales receiving box control system ^ handling stolen storage box processor. The storage box control system control chip described in the item [u] is a complex programmable logic element. m twenty two