TWI325595B - Dll circuit feeding back zq calibration result, and semiconductor device incorporating the same - Google Patents

Description

1325595 IX. Description of the invention: [Technical field to which the invention belongs] ^ Issued in a semiconductor device, especially the calibration result of zq, used to adjust = Wei Lu (four) DLL (Lai Wei Wei) Wei, a semiconductor with such a dll circuit Device. /, [Priority of the application] The priority of the prior claim is 5-308072, the disclosure of which is incorporated into the prior art. Recently, electronic systems have been accelerated in operation, among which semiconductor devices have been named Data transfer rate. Furthermore, the data transfer rate of idle speed has been sought. Therefore, the U-channel pulse synchronization system is synchronized inside the semiconductor device using the clock signal tiger (hereinafter also referred to as "clock"). For example, there is a synchronous dynamic random access memory (hereinafter referred to as "sdram t" memory device. Furthermore, with the front edge of the clock and the ddr of the back_step (double the hair, and the 3 tears ^) The circuit has been synchronized with the clock. Each of these advanced SDRAMs uses dll if η to synchronize the timing between the internal clock and the external clock. Figure 1A is a rabbit figure. The buffer in the DLL circuit is in its value S to suppress the amplitude of the output of the buffer to a decimal. Therefore, since the DQ does not have a termination element, the Q replica output (RCLK) will exhibit a full amplitude, as shown in the figure. π shows the inclination of these outputs and the amount of delay (tP_temperature, Lai, and process): and the delay time Ati and ~2 of these outputs are different due to the amplitude difference l it. The delay line of the DLL circuit The operation is to make the DQ copy and steal. The called pulse CK is synchronized. Therefore, as shown in Fig. 2, the difference between the observation (S) 595 is observed as the skew between the output of the DQ buffer and the external clock. Driving the SDRAM towel 'not measured by temperature, voltage, and 曰: pressure (Vth) The function of delaying the amount of delay and feeding it back.: 1 absorbing the control of those changes. That is, - there is a delay in the delay and the delay of the DQ replication system (Skws), and thus The DLL circuit can not achieve high-speed operation, and the splicing becomes a DLL circuit of the 16th, etc., and there is a prior art document 1 (Japanese unexamined patent application ^ drought circuit, there is a prior art document 2 (Japanese unexamined 004 -032070 3 (9 2004-145709). In addition, about 兮 ( (4) _ A: Month 'A) This unexamined special case first filed the technology 4 (曰 Previous Technical Document 1 revealed a DLL system, and == = The phase difference ' is controlled by the external control of the signal = the reflected wave is added 』 == The hold time depends on the settling time of the mother money chip (, (4) and the electric crystal S circuit, there is no measurement Temperature, voltage, and M0S = the change of the Vth of the Japanese body and the feedback function. Because: the Vth and other changes of the MOS transistor lead to the Wei Wei eccentricity on the domain of the plaque _ I know the fresh electric axis, and I have not improved the solution for these deviations and therefore still leave this problem.

In the DLL circuit, there is no measurement temperature, electromigration, and M sf change and it is reversed. Shame, there is a delay of the DQ buffer system caused by changes in temperature, electricity, Vth, etc.; the change in the delay amount of the high Si system becomes a problem of skew, and therefore there is no [invention]

It is therefore an object of the present invention to provide a DLL circuit that reduces skew by virtue of circuitry. V(4), σ, and σ DLL are intended to provide a semiconductor device including the DLL circuit. Other objects of the invention will become apparent as the description proceeds. Zo M has 70 parts of the resistance of the external resistance element connected to the special soldering iron. The county is subject to temperature, miscellaneous and process. Therefore, the result of the calibration is the reaction temperature, voltage, and system. : The copying system of the DLL circuit can be adjusted = 广 〇 由 由 由 由 由 将 将 将 Z Z Z Z Z Z Z Z Z Z Z Z Z 。 。 。 This architecture can provide a semiconductor device having a reduced DLL circuit with such a DLL circuit. In the case of Dianqi, 八不, and 2, basically, the present invention employs the technique described below. If you don't know more about it, you can see that the application technology of the variant is also included in this application. According to the embodiment of the invention, the DLL is provided with a DLL (Delayed Circuit) circuit having an output buffer path of the output buffer and a copy output circuit = a path including a delay amount. The variable circuit adjusts the copy path by the control signal of the output impedance of the output buffer = ================================================================================== The variable circuit includes a m〇s transistor as a variable capacitance f body connected to the signal line of the replica path, and the Ls base is connected to the control signal or the transistor of the control signal, and can be configured such that the second The drain is connected to the control signal and is variably connected to the reverse signal of the control signal. The core source and the pole, a conversion factor' converts the control signal into a second control signal, and the second control signal is used to adjust the delay of the delay variable circuit. The person can use the lookup table to convert the control signal into the delay I of the third variable control circuit. Control of the 虎 ' Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏 Γ吏In this way, a signal is provided. The circuit includes: a delay line input with a clock signal; an output buffer input with a clock signal from the 疋^路); a copy-of-purchase driver input with a pulse-driven drive number; The clock signal is input to the variable variable circuit; the output buffer is input by the input signal from the 2, drive, and the pulse signal; and the clock signal of the circuit is input to the circuit The clock signal of the delay line is added to the output buffer 珞, thereby detecting the phase difference between the input clock signals, the phase detection power >, the delay of the delay line 8 1325595, from, the phase The judgment result of the fine circuit is adjusted, and the bile delay amount can be a semiconductor description DLL circuit having a calibration function by using a control signal for adjusting the output impedance of the output buffer, each of which is based on being connected to a ZQ calibration. "The replication of the wide DLL circuit is based on the ZQ calibration of the sister fruit 5 = money. Therefore, it is possible to reduce the skew of the output timing. Preface = Reducing the DQ output caused by changes in temperature, and process, etc. [Embodiment] ϊί外明, - The embodiment illustrates a DLL circuit. Input station and propagate to ^ green by the "DLL circuit dedicated start line via - delay the appropriate delay of the f line 1 clock, body data input itl DQ buffer k ^ = buffer 3 and 4 sent to memory = = out The clock processor 6 and the buffer ί7' have been delayed by the delay delay. The clock is also driven through a replica clock into the DQ buffer 5, the Ί路8, and a buffer 9 To promote 6 to DQ to copy 10° ^^Q H10 ° We will self-replicate the drive to monitor DQ copy 10 (4) i slow ==:= 9 1325595 for phase comparison, then feedback the comparison judgment to the step Tank 1 is still (four) 5 times =, the difference (grab △ _ _ may be small, and should be further === ^ voltage, and the change in the process does not change. However, 5, the termination component does not reduce the current The purpose is set to ^, so the amplitudes of the output data are different from each other. Furthermore, the DQ buffer system path of the 3 long-distance automatic/Λ to rDQ buffer 5 is placed as a parameter for correcting this change. By zQ calibration ^ (4) - brain - to make the right, Z Z calibration circuit 12 by monitoring the output impedance connected to the school 5. Since zq Calibration circuit = ^ The body of the system is connected to the calibration end; a counter; and a comparison. Adjust the impedance of the replica output circuit according to the lion - 10 1325595 transistor ' g. When the impedance of the replica output circuit and the impedance of the external resistor component become equal to each other, that is, when the potential of the ZQ calibration terminal and the reference potential become phase with each other, the miscellaneous device will stop operating to determine the ZQ calibration result DRZQNT as the counter output. By inputting the ZQ calibration result DRZQNT outputted from the counter, the output can be completed for 5 weeks, and the impedance of the path is read to be equal to the resistance value of the external resistance element. By means, the resistance value of the external resistor element of the ZQ calibration is set equal to the impedance of the transmission line of the system, and the impedance of the dedicated transmission line and the impedance of the output circuit match each other. It is assumed that the output circuit is composed of four transistors TQNT 4 has a four-bit architecture and the ZQ calibration result leg j is used to combine the driving ability of the four electric Japanese bodies into 8:4:2: The ratio of 1 to individual bits. In this example, by setting ^QkUDRZQNT according to the binary system, it can be used as a control signal for directly controlling the transistor. The ZQ registration circuit is not particularly limited to the foregoing structure, as long as it can make the disk DRZQNT<3:〇&gt To control the impedance. Y /, called the right result Zhao chip by = 2; electricity: so it is not subject to the semi-conducting i Q father criterion for the temperature, voltage, Ϊ # fk of the semiconductor device greedy 'and therefore used to compensate These changes are based on the results of the DRZQN^f^ component, which represents the calibration junction and the MOS thunder β (four) eve you '"u ^ take the pass value, while in the high temperature, high voltage, and MOS electric body Under the condition of low Vth, the ZQ calibration result is a low value of ^=> 1325595. That is, when the driving ability of the transistor of the output circuit is small, more transistors are selectively turned on to match the impedance. Conversely, when the driving ability of the transistor of the output circuit is large, then less transistors are selectively turned on to match the impedance. Referring also to Fig. 3B, the delay amount variable circuit 8 will be explained.

The delay amount variable circuit 8 includes: a D-FF group 13 including four d-FFs and input with a ZQ calibration result DRZQNT<3:0>; an inverter group 14, which includes four Inverting the corresponding component of the ZQ calibration result DRZQNT<3:0>^ZQ calibration result DRZQNT, respectively; and the capacitive delay element groups 15 and 16, are connected to a signal line and each of the four capacitive types Delay element. Each of the capacitive delay elements is in the form of an electric crystal having a gate electrode connected to the signal line. The capacitive delay element of the capacitive delay element group 15 disposed on the upper side of FIG. 3 is a Ρ-channel MOS capacitive element, and the capacitive delay element of the capacitive delay element group 16 disposed on the lower side is η _ channel m〇s capacitive components. Here, the capacitance value of the transistor is set to a ratio of 8:4:2:1 from the right of the binary system. By setting the capacitance value corresponding to the binary system, we can control according to the binary system ZQ calibration result DRZQNT<3:0;^^^. ZQ calibration result DRZQNT<3: 〇W is connected to the substrate, source, and drain of the p-channel M〇s capacitive element' and the ZQ calibration result drzqnt<3.〇> reverse ZQ calibration result DRZQNB<3 :0> is connected to the n-channel M〇s capacitive component ^ substrate, source, and drain. The ZQ calibration result DRZQNT<3:0> and the reverse ZQ calibration result DRZQNB<3:0> are input to thereby control the potential applied to the capacitive extension. For example, when the ZQ calibration result DRZQNT is <〇100>, the second capacitive delay element from the right side on the upper side of Fig. 3B is connected to the supply potential, and the lower side is set from the right side. The second capacitive delay element is connected to the junction, thus changing its capacitance value. The residual capacitive delay element on the upper side is at ground potential and the remaining capacitive delay element on the lower side is connected. Since the transistor is in the reverse direction, the capacitive delay element input according to component 2: DRZQNT with a high level will lower its capacitance value. On the other hand, = 12 1325595 has a low level component ZQ calibration result. The capacitive delay element input by DRZQNT is used as the storage area' so that its capacitance value becomes large. In this way, the capacitance value changes depending on the high or low level of the corresponding component ZQ calibration result. When the driving capability of the transistor of the output circuit is lowered due to low temperature, low voltage, and process variation, the ZZ calibration result has a large value. Therefore, the capacitance of the valley type delay element exhibits a small value. However, when driving with a transistor having a small driving capability due to a process variation, the amount of delay will increase by the amount of delay equivalent to the path of the Dq buffer system. Therefore, the difference in delay amount (ΔΤ1_ΔΤ2) between the Dq buffer system path and the DQ copy system path remains unchanged. In the mode, the capacitance value is changed by switching the potential of the substrate, the source, and the gate of each transistor (capacitive delay element) between the supply potential and the ground potential. The dream value is such that the difference in the amount of delay between the signals is controlled. "It is difficult to match the small and solid state. As described above, the ZQ calibration result DRZQNT<3:〇> is used as the delay amount to change the signal so that the temperature is The difference in delay amount (λτι· Τ2) within the range of voltage variation is fixed. ~ The D-FFs respectively accept the ZZ calibration result drzqnt of the corresponding component of the drzqnt<3:〇> synchronized with the DLL lock signal. The delay occurred in the delay variable circuit is shown as 'k'. By inputting the final term and the continuous change when checking the rainbow lock, the circuit is performed in order to apply the ZQ after the DLL lock is completed. Calibration result. Check lock yell = 'The DLL in the DLL circuit is adjusted according to the timing chart. Ye Shuo will refer to Figure 4 pulse 2 in response to the clock pulse output from the output of the clock driver LCL^pT; ^面, copy 1325595 10 will output data after ΔΤ2. Δτι and ^Τ2 change due to temperature, voltage, and process changes. The fastest delay of ATI is known, and the slowest delay is ATliAW). Similarly, the fastest known delay is /\ T2 (MW) The slowest delay amount of ΛΤ2 as △ TSiAW).

In general, the amount of change of ΛΤ1 (ΔTKAW) - ATICMW)) 盥ΛΤ2 change amount (AT2(AW)_ ΔT2(MW)) is different from each other. Therefore, a deviation occurs between the data output timing of the DQ buffer 5 and the data output timing of the DQ copy 1 due to changes in temperature, voltage, and process. Since the delay line in the DLL circuit monitors the output of the DQ replica and synchronizes it with the external clock, the added offset is used as the skew between the external clock and the DQ output. Therefore, inserting the delay variable circuit 8 into the clock of the clock LCLKREPT regardless of changes in temperature, voltage, and process will make the timing difference between the DQ buffer output and the DQ replica output a fixed value. When the relative delay is due to temperature, voltage, and variation in the process, the delay of the (4) way 8 can be controlled and reduced, and when the phase is defeated: the delay of 2LCLKREPT is reduced, the delay variable circuit 8 is The amount of delay is controlled to increase. In the case of a high pressure 取得, the high number is 4, and the temperature (rQ=the imbalance between the vths is considered to be::; = 1325595. In this case, the reverse control signal can be used as the n_mif stabilization, The result of the improved output timing is added to the DLL circuit, and the DLL output clock pulse (LCLKOET) is sent to the DQ buffer, and the delay is adjusted, and the data output timing is externally generated. Clock synchronization. This delay line) is used to make a phase comparison. The comparison: 3⁄4 of the way to the ϊΐίπ road' delay amount variable circuit is inserted in m. Electric circuit "Q copy system: = receive: buffer system can improve the timing adjustment accuracy == If this way,

15 S 1325595

The semiconductor device can be operated at high speed. Although the present invention has been described in connection with its single-embodiment, it is to be understood by those skilled in the art that the present invention can be implemented in various other square wires. In the above, the "6" is based on the case where the ZQ calibration result DRZQNT<3:〇> is directly used as the control signal. However, the ZQ calibration result drzqnt <3:g> is the impedance (four) signal of the output circuit, so it is possible that it is not achieved with the electrical signal in a perfect hl manner. Therefore, for more accurate control, we use Z-scale to convert ZZ scale drzqnt<3:g>, ^ to the capacitance control signal. Furthermore, 'we can arrange to use the lookup table to convert the ZQ school's DRZQNT<3:0>, and then use it as a capacitance control signal. [FIG. 1A] FIG. 1A is a block diagram of a conventional DLL circuit. DQ Buffer Input DQ Copy Wheel Out Figure 1B shows the waveform diagram contained in the DLL circuit of Figure ία. Figure ic shows a waveform diagram of (RCLK) included in the DLL circuit of Figure 1A. 2 is a timing diagram of the DLL circuit of FIG. 1A. Figure 3A is a block diagram of a DLL circuit in accordance with an embodiment of the present invention. Fig. 3B is a schematic diagram of a variable amount circuit included in the circuit of Fig. 3A. Fig. 4 is a timing chart of the DLL circuit of Fig. 3A. Fig. 5 is a graph showing the results of the skew comparison for explaining the effects of the present invention. [Description of main component symbols] 1 to delay line 2 to DLL output clock driver 3 to buffer 4 to buffer 1325595 5 to DQ buffer 6 to copy clock driver 7 to buffer 8 to delay amount variable circuit 9 ~ Buffer 10 to DQ Copy 11 to Phase Detection Circuit 12 to ZQ Calibration Circuit 13 to DFF Group 14 to Inverter Group 15 to Capacitive Delay Element Group 16 to Capacitive Delay Element Group

Claims (1)

1325595 Amendment 1 10, the scope of application for patents, L A DLL (Delay Locked Loop) circuit, including: Brother/No. Patent Application Chinese Patent Application Revision (without line) ---- January 29, 1999 Revision. Output buffer path, the output buffer path includes a round-trip slow copy path with a copy-round circuit; a timely 'two-delay variable circuit, which is used to adjust the output of the output buffer Adjusting the delay amount of the copy path by the impedance control signal, wherein the delay amount variable circuit includes an M〇s transistor as a device, and the gate of the MOS transistor is connected to one of the signal paths of the copy path And === secret, and the secret system is connected to the control side, or the paper circuit of the control claim 2. 2.t, the delay variable circuit is connected to the control signal of the DLL lock signal . From the inside, the circuit is connected to the ^ DLL circuit of the patent application scope, wherein when the variable capacitor is used, the substrate, the source, and the secret of the PM〇S transistor are 3 if , # The variable capacitance component is running _, meaning (10) electricity ίί by fr and secret money _ control number of the reverse recording. 4. The DLL circuit of item i of claim §, wherein the control is replaced by a second control money, #, and the delay amount is variable. For example, the -(4) field is adjusted. # 5. As in the DLL circuit of the patent application section, the control signal of the driving side transistor of the output buffer is determined in the basin. r is used to control the circuit's controllable input signal is used to control the read-side transistor of the w-reading state. 7. If the patent application scope is the second item, the second rush f!5_ The control of the drive side transistor of the control state is performed by the DLL (delay lock loop) circuit, I. Hush: path __ device; 18 is 1325595 a delay variable circuit And adjusting the delay amount of the copy path by using a control signal for adjusting the impedance, and converting the control signal into a third control by buffering the Z-search table, Q delay Delay of variable-variable circuit Ϊ 9. A DLL (delay-locked loop) circuit comprising: a delay line 'input with a clock signal; pulse drive (four)' wire from the delayed clock input. ; ten, from the DLL wheel (four) pulsator at the time of the ^ number to the Hi pulse driver 'clock with the clock signal from the delay line. In; variable circuit, from the clock of the replica clock driver Signal input; and round-out copy buffer 'input and output from the clock signal from the delay variable circuit , with the clock from the output copy buffer H; 5 亀 观 ,, look at the control signal of the output impedance of the clock. ^ 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 敕 日 日 日, 士置' where the semiconductor device contains the DLL circuit according to the third patent. The job includes, according to (4) a semiconductor device having a calibration function according to (4), the semiconductor device comprising the DLL circuit according to item 5 of the patent application No. 19 Ui 1325595. 15. A semiconductor device having a calibration function, wherein the semiconductor device comprises a DLL circuit according to item 6 of the scope of the patent application. 16. A semiconductor device having a calibration function, wherein the semiconductor device comprises a DLL circuit according to item 7 of the scope of the patent application. • 17. A semiconductor device having a calibration function, wherein the semiconductor device comprises a DLL circuit according to item 8 of the patent application. 18. A semiconductor device having a calibration function, wherein the semiconductor device comprises a DLL circuit according to claim 9 of the scope of the patent application. XI. Schema: 20