TWI324299B - Processor system and method for reducing power consumption of a processor - Google Patents

Description

9a m . - » . · Nine, invention description: [Technical field to which the invention belongs]. The present invention relates to processing n, particularly by controlling the switching of the round-out signals to reduce power consumption. [Prior Art] In this era of electronicization, miniaturization of highly versatile and highly integrated inexpensive electronic devices has extremely high market demand. To cater to this trend, the issue of reducing power consumption in electronic devices is becoming more important. Since a computer, or central processing unit (CPU), consumes a significant proportion of the power, a variety of methods have been used to reduce the power consumed by the processor. Conventional processor designs can simultaneously initiate multiple outputs beyond what is actually needed. In many cases, it is acceptable to turn off unused turns. One such situation occurs when the write action of a processor to a memory or any external peripheral device is narrower than the width of the bus. For example, writing only eight bits out of thirty-two bits means that twenty-four bits are not used. If the twenty-four-bit circuit is turned off, no power is consumed. The second case occurs when the address is transferred to the memory or any external peripheral device. Once the above memory or external peripheral device knows the address, it does not need to change the address value until the next address appears. Moreover, some peripheral devices will automatically increment in the case of unloading, and switching the above unnecessary output will waste power, so the above output can be turned off to save power. SUMMARY OF THE INVENTION In the context of the above-described invention, in order to meet the industry's need for power saving, the present invention provides a processor that can be used to defeat the above-mentioned conventional processors. An embodiment of the present invention provides a processor system that saves power consumption of the virtual system by simplifying the number of handovers. This system package ^-process II core and at least - switch simple single center is located in the processor = processor core is used to execute instructions and produce raw output = ° the switch simple unit is used to connect the processor at least = = number. Each of the switches simply saves the single-domain receive-enable signal and the original round-trip signal, and the signal includes a signal to close the gate to the first logic circuit unit to enable the original output signal to be the default value. Or retaining the number to pass the original μ (four) generation - the final (four) signal to take another embodiment of the tree: ::::: under-number to save processor - consumption. This device: The internal core system executes the instructions and generates the original where = core and at least - switches the simplified unit. Located at the processor to start the correction replacement page output signal. The core further includes a decoding unit to generate a consistent energy signal. The switching simple unit is for connecting at least one original output signal of the processor. Each of the switching simplification units receives a coincidence signal and the original output signal, and includes at least one logic circuit unit to cause the original output signal to be a default value or to remain a previous value when the enable signal is off and when When the enable signal is turned on, the original output signal passes through the switching simple unit, thereby generating a final output signal instead of the original output signal. Another embodiment of the present invention provides a method of saving power consumption of a processor system by simplifying the number of switching cycles. The method includes receiving an original output signal and a consistent energy signal, determining whether the enable signal is turned on, making the original output signal a final output signal when the enable signal is turned on, and when the enable signal is off , let the original output signal be a default value or leave it as a previous value. [Embodiment] The direction of the invention discussed herein is a processor. In order to thoroughly understand the present invention, detailed steps and compositions thereof will be set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. . Referring to Figure A, it is a block diagram of a simplified computer system. A computer system can be simplified to include only at least three main components: at least one processor 110, at least one memory unit 120, and at least one input-output subsystem 130. The processor 110 described above is also commonly referred to as a central processing unit. The memory unit 120 is used to store program instructions and data. The input and output subsystems 130 are interfaced with different input and output devices 140. These input and output devices 140 connected to the computer system are also referred to as peripheral devices. The two main purposes are to communicate with the outside world and store data. Input and output devices 140 such as a keyboard, display screen, printer, and data machine are used to provide a user interface; and input and output devices 140 such as a magnetic disk are secondary data storage devices. The first A diagram also shows a connection network called a system bus, which is used to provide a communication channel between the above three components. This system bus contains three main components: a destination bus 150, a data bus 160, and a control bus 170. The width of the address bus 150 determines the size of the physical memory that the processor 110 can address. The width of the data bus 160 determines the size of the data exchanged between the processor 110 and the memory unit 120 or the input/output subsystem 130. Control sink j 9 know 11 ^ 〆 7 day repair r.. change mourning Flow row 170 contains a set of control signals. Typical control signals include control signals such as memory read, memory write, output read, output write, interrupt, interrupt acknowledgement, bus request, and bus grant. The above control signals are used to indicate the type of action performed on the bus bar of this system. Please refer to FIG. B, which is a block diagram of signal transmission in a processor core 181 of a processor 180 in the prior art. This processor 180 typically has three output signals: address, data, and control signals. A processor core 181 is used to execute instructions and communicate the results to other components of a computer system. In a conventional processor design, the above three output signals will be as shown in the first B diagram, whereby the processor core 181 is directly transferred to the output bus. In the prior art, the decoding unit 182 does not generate any control signals to control the switching of the outputs, i.e., even when some of the outputs are inactive or can be turned off, all of the outputs must be turned on. Please refer to the first C diagram, which is a block diagram of a decoding unit 190 in the prior art. A decoding unit 190 receives data and instructions from an instruction fetch unit of a pipeline architecture processor to decode instructions transmitted by the instruction fetch unit of the previous stage of the pipeline. The decoding unit 190 is configured to generate a sufficient control signal to supply the execution unit of the next stage of the pipeline for the execution unit to perform the decoded instruction 1324299

Execution of the job. The instruction decode block 192 in the decoding unit 190 is instructed to decode. The decoded instructions and data are transferred from this decoding unit 190 to the execution unit of the pipeline one stage for execution of the decoded instructions. Please refer to FIG. 2A, which is a block diagram of a decoding unit 250 according to one embodiment of the present invention. The present invention discloses an additional enable control signal 257 to provide control when the data of the current instruction needs to be updated. This enable control signal 257 will be activated when the data has to be updated; this enable control signal 257 will be turned off when there is no need to update the data. There are three types of enable signals: address enable signal, data enable signal and control enable signal to control the address bus, data bus and control signal bus. A receiving function block 251 of a decoding unit 250 is for receiving instructions and data from an instruction fetch unit of a previous stage of the pipe architecture. The received instructions will be decoded in decoding function block 252. Then, the transfer function block 253 transfers the data generated by the decoding unit 250 and the decoded instruction to the execution unit of the next stage of the pipeline architecture for execution, and the above-mentioned enable control signal 257 is directly transmitted to the output circuit of the processor. 0 Refer to the second B diagram, which is a processor with multiple switching reduction units to connect an output address sink 10 1324299 row, an output data bus and a control signal bus A block diagram of the one. As shown in the first A diagram, a processor has three output bus bars: a bit bus bar 150, a data bus bar 160, and a control signal bus bar 170. The present invention adds a switching simple unit to each bit of each of the above bus bars to reduce the switching operation of the output circuit. One of the output address ADDR generated from a processor core 220 will be fed into a plurality of switching simple cells 210-1 to 210-N with respect to the output address bus width, and thus the decoding unit 230 of the processor The generated address enable signal ADDR_EN is also fed to the plurality of switching simple units 210-1 to 210-N described above. The decoding unit 230 converts an instruction into a read or write job that must control the address, data, and control signals. The number of required simple switching units depends on the width of the output address bus. For example, a 32-bit output address bus should have 32 switching simple units 210-1 to 210-N (N=32). ). Next, the function of the simple switch switching is performed in each of the switching simple units 210-1 to 210-N, and the results of all the switching simple units 210-1 to 210-N are combined into a final output QUIET_ADDR, and This final output is transferred to the memory unit 120 or the output sub-system unit 130 according to the destination of the output address ADDR described above. In the same way, the simple output data DATA switch switch 11 1324299 satiiz. The action can also be achieved by transmitting the output data DATA through a plurality of switching simple units 211-1 to 211-N corresponding to the width of the data bus. . The data enable signal DATA_EN will control whether each bit of the output data DATA through the plurality of switching simple units 211 needs to be modified to achieve a simple switching switch. The final output data QUIET_DATA collected from all the switching simple units 211 will be transferred to the memory unit 120 or the output sub-system unit 130 shown in the first A diagram. Some control signals CONTROL can also utilize the same technique to reduce the switching action of the final control output QUEIT_CONTROL signal. The control enable signal CONTROL_EN from the processor decoding unit 230 and the plurality of switching simple units 212-1 to 212-N are used for the switching operation of the control signal. The number of switching simple cells required to correspond to the control signal bus is also related to the width of the control signal bus. When it is necessary to access octets (one tuple) at a time, the number of switching simple units that need to be constructed can also vary. For each tuple, a single switching simple unit can be implemented to open and close the eight bits together. Taking a busbar with a width of 32 bits as an example, four switching units that allow the octet to be turned on and off should be implemented to control each byte independently. According to this, the number of switching simple units on the one busbar is also relatively high on the 7th 丄 ; ;; 1 ____ ------------ should be in this bus The width, the number of bytes in this bus, or the number of random bits required. Please refer to the third figure, which is a block diagram of a plurality of switching simple units in a microprocessor for a round of data bus. Taking a 32-bit data output bus DATA as an example, 32 switching simple units 311 to 31M should be implemented as shown in the second B. However, the above 32 switching simple units 311 to 31M can be divided into four groups. The first group 311 corresponds to each of the first byte, and the second group 312 corresponds to the second byte. The third group 313 corresponds to the bits of the third byte and the fourth group 31M (314) corresponds to the bits of the fourth byte. The data enable signal DATA_EN generated by the decoding unit 330 to control the 32 switching simple units 311 to 31M may also be a single signal shown in the second B, or may be divided into

Four sub-signals, BYTE_1_EN, BYTE 2 EN, BYTE 3 EN - and BYTE_M_EN (BYTE_4) to control the four bytes of the output data DATA, respectively. Dividing a single data enable signal DΑΤΑ_ΕΝ into a single byte data control signal β ΥΤΕ_Μ_ΕΝ has the advantage of only having to turn on the necessary changes to the byte and leaving the other bytes unaffected. Assume that only the first byte of a busbar needs to be accessed, and only the switches of the 简_1_ ΕΝ仏 相关 简 简 简 , , , , , , BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY BY 1324299 兕 胸 胸 _ _ 切换 简 简 简 简 简 简 切换 切换In this case, cutting the single data enable signal DATA_EN into multiple sub-signals to control the opening and closing of the other triad can save some power. For data buses with other widths, the number of byte data control signals can be adjusted accordingly so that a byte data control signal ΒΥΤΕ_Μ_ΕΝ is used to control a byte. Accordingly, each byte can be independently turned on and off to minimize the number of output switch switches, thereby using less power in a computer system. Although a data output bus is shown in the third figure, the same technique can be used in the address output bus and a control signal bus to separate the enable signals, thereby turning on the bits that must be changed. Keep the remaining bits unchanged. Please refer to the fourth figure, which is a block diagram of a plurality of switching simple units in a microprocessor for an output data bus. In this figure, each of the switching simple units 411 to 41 corresponds to each byte of the data bus DATA. Obviously, the number is the same as the total number of bytes in this data bus. The enable signal from the decoding unit 430 is also divided into sub-signals according to the number of bytes of the data bus, that is, ΒΥΤΕ_1_ΕΝ to ΒΥΤΕ_Μ-ΕΝ. In the implementation example of the 32-bit data bus, there are four switching simple units 411, 412, 413 and 414 and four enabling data secondary signals BYTE 1 ΕΝ, BYTE 2 ΕΝ, 14 1324299 ΒΥΤΕ_3_ΕΝ and ΒΥΤΕ_4_ΕΝ. Taking the data bus shown in the fourth figure as an example, the same concept can be applied to the address bus ADDR and the control signal bus CONTROL. The fourth figure is superior to the third figure in that the fourth picture only requires one-eighth switching of the simplified unit in the third figure, which can significantly reduce many logic circuits. In another embodiment, shown in FIG. 5, the switching simplification units 510 through 512 can be located outside of the processor 530. The output of the processor 530 typically includes an output address ADDR, an output data DATA, and an output control signal CONTROL. Each bit of the above address/data/control signal is transmitted to the switching simple units 510 to 512 located outside the processor 530 to simplify the switching of the output circuit. The decoding unit 540 of the processor 530 also provides an enable signal. This concept of adding the switching simple units 510 to 512 outside the processor 530 can also be applied to the case where the switching simple cells are placed inside the processor in the second, third and fourth pictures. Five embodiments for switching the simplified unit structure will be disclosed in the sixth, seventh, eighth, ninth and tenth views, respectively. The first four embodiments disclosed in the sixth to ninth embodiments disclose the first method of setting the invalid output value to a default value, and the embodiment shown in the tenth embodiment reveals that the invalid output value is retained as the previous value. Two methods. Please refer to the sixth figure, which is a block diagram of switching the simplified unit 600 according to a first embodiment of the present invention. This switching simplification unit 600 includes a single one and a gate 610. When the original output signal OUTPUT and the coincidence signal ENABLE of the 15-processor are simultaneously input to the AND gate 610, the enable signal ENABLE from the processor decoding unit can control how the original output signal ^OUTPUT will be converted into a final output. Signal QUIET is an OUTPUT. When the enable signal ENABLE is on, the AND gate 610 will cause the original output signal OUTPUT to pass through the gate 610 unchanged. Conversely, when the enable signal ENABLE is off, the above raw output signal OUTPUT will be set to a default value of 0 to reduce the number of output switchings. It should be noted that the original round output signal OUTPUT may be a single address, a data, or a control signal; likewise, the final output signal QUIET_OUTPUT may also be a final address, a final data, or a Final control signal. Please note that the operation shown in the block diagram of the sixth figure is only one of many embodiments consistent with the scope and spirit of the present invention. It is also possible to use a combination of other logic units or logic units to achieve the same function and purpose by using one and the gate 61 〇 only to reduce the number of output switching times. For example, a series of gates can be used to replace a single gate. When the enable signal is off, a series of gates can also set the output value to a default value. Another method is to simultaneously reverse the two outputs of a reverse or gate (NOR), and its function is equivalent to a gate. Those skilled in the art can easily derive other types of logic circuit units to achieve the same function as the above-mentioned 1324299 when the enable signal is turned off and the output value is a default value. Reducing the number of output switchings reduces the total power consumption of a processor' and extends the battery life of an electronic device. The seventh diagram shows that one or the gate 710 can also be used to achieve the function of setting the output value to a default value when the enable signal is off. When the coincidence signal ENABLE is on, an original output signal OUTPUT can pass through the OR gate 710 to become a final output signal QUIET_OUTPUT. A truth table can be easily displayed. When the enable signal ENABLE is off, the final output signal QUIET_OUTPUT can be set to a default value of 1, instead of using the default value of one and the gate. Since the final output signal QUIET_OUTPUT when the enable signal ENABLE is off is ignored, it is irrelevant to set it to 〇 or 1. The eighth figure shows that one of the multiplexers 810 can also be used as another embodiment of the present invention. One of the first inputs of the multiplexer 810 is for receiving an original output signal OUTPUT, and a second input is coupled to a stable value, such as 0 or 1. A selection signal ENABLE is used to control the switching of the output. When the selection signal ENABLE is on, the above-mentioned original output signal OUTPUT will pass through the multiplexer 810 and become a final output signal QUIET_OUTPUT. Conversely, a closed selection signal ENABLE will prevent the original output signal OUTPUT from passing through the multiplexer 810 and cause the second input value to become the final input 17 1324299

Signal QUIET_〇UTPUT. Please refer to the ninth figure, which is a schematic diagram of a switching simple unit according to another embodiment of the present invention. When a select signal ENABLE is on, a transparent latch 910 allows an original output signal OUTPUT to pass through as a final output signal QUIET_OUTPUT. Conversely, a closed selection signal ENABLE will prevent the above-mentioned original output signal OUTPUT from passing, so the final output signal QUIET-OUTPUT will be set to a default value. The tenth diagram shows a fifth embodiment of switching the simplified unit structure. The switching simplification unit 100 includes a multiplexer 102 having a first input value for receiving an output from the multiplexer 102 and a feedback signal generated by a flip flop 101 and a second input value. Receive an original output signal OUTPUT. Similarly, the above-mentioned original output signal OUTPUT can be a bit address, a data, or a control signal. A selection signal enable from the processor decode unit is fed into the multiplexer 102 to control the output switching. The final output value of this switching simplification unit 100 is referred to as a final output signal QUIET_〇UTPUT, which may represent a final address, a final data, or a final control signal. When this selection signal ENABLE is off, this switching unit 1 performs the action of retaining this original output signal OUTPUT. However, when the selection signal ENABLE is on, the original output signal OUTPUT will be 18 1324299 9a ιϊ· λ by switching the simple unit ΙΟΟ to form the final output signal QUIET_OUTPUT described above. Then, the combination of the other logic circuit | meta or logic unit replaces the above-mentioned flip-flop 1 〇 1 and multiplexer 1 〇 2 to achieve the function of retaining the original output signal OUTPUT when the selection signal ENABLE is off, which is in accordance with the present invention. Scope and spirit. Referring to FIG. 11 , which is the first method for setting the output value to a default value according to the first to fourth embodiments of the present invention to reduce the output of a continuous output stream A1 to A7. A schematic diagram of the number of handovers. Each of the output values A1 to A7 may represent a bit, a byte, or any other number of bits as shown in the second B, second, and fourth figures. The coincidence signal (ENABLE) and an original output signal (OUTPUT) are fed into the gate 61 of the sixth figure. When the enable signal is on, the AND gate 610 allows the above-mentioned original output signal to pass and becomes the final output signal QUIET_OUTPUT. Signals such as A, A2, A4, and A5 can pass unchanged to become the final output signal. On the other hand, when the enable signal is off, the final turn-out signal such as A3, A6 and A7 signals is set to the default value of zero. The default value of the output can be set to 〇 or 1 in advance. At the original output signals A1 to A7, six switches are generated in a continuous output stream. The advantages produced by the present invention can be seen in a continuous output when at least two enable signals are off. For example, since the enable signals of the A6 and A7 signals are all off, the final output signal of 19 is 0 at this time, and the switching operation between the A6 and A7 signals is omitted. According to the switching simple unit disclosed in the first to fourth embodiments of the present invention, the total number of switching times is changed from six times to five times. If the first output signal shown in Figure 代表 represents one bit, since the Α6 and Α7 signals can be set to 0, then the switching simple unit shown in Figure 6 to Figure 9 will have a one-bit switching reduction. The advantages. However, if each of the original output signals represents a byte, switching between the Α6 and Α7 signals can effectively save one byte switching. Obviously, the longer the enable signal is turned off, the easier it is to switch more times and to save more power. Referring to Fig. 12, it is a schematic diagram of the second method of retaining the invalid output value as a previous value to reduce the number of output switching times according to the fifth embodiment of the present invention. The same Α1 to Α7 and enable signals are used to compare the first method disclosed in the first to fourth embodiments with the second method disclosed in the fifth embodiment. Referring to the fifth embodiment shown in FIG. 10, the original output signal (OUTPUT) and the enable signal (ENABLE) are used to switch the input value of the unit 100, and the switching function is simplified. The internal flip-flop 101 and the multiplexer 102 are executed. Furthermore, the final output value of this switching simplification unit 100 is referred to as a final output signal QUIET_OUTPUT. For those original output signals whose enable signal is 20 1324299 ί pole 7 曰 correction replacement page j open state, such as A1, A2, A4 and A5 signals shown in Fig. 12, which can be implemented as the first four The example generally simplifies the unit 100 by this switching. When the enable signal is off, the flip-flop 101 and multiplexer 102 in the switching unit 100 will retain the previous value of the input. Taking the A3 signal as an example, A3 will retain its previous value, which is the A2 value in this embodiment. Obviously, retaining the previous value will eliminate the switch between the A2 and A3 signals. Comparing the A3 signals of the eleventh and twelfth figures, the eleventh mode uses the first mode of setting the output to the default value to switch the output value from a valid value to a gating value (the A2 value is turned to 0). And then switch to the next valid value (that is, from 0 to A4); however, the second method of retaining the previous value used in the twelfth figure only switches when a new valid value occurs (directly by the A2 value) Change to A4 value). Similarly, A6 will retain the previous value of A5, and A7 will be the same. If the final output signals of the eleventh and twelfth graphs A5 to A7 are compared, the eleventh diagram has a switching action (A5 to A6), and the twelfth graph does not have any switching action. The second method shown in Fig. 12 successfully eliminates the switching action between A5 and A6, thereby saving the power consumption of the processor. Comparing the final output signals of the eleventh and twelfth figures, the eleventh figure has a total of five switching actions, and the twelfth picture only needs three times. When considering the scale of the output bus or the load level of the bus, it can be seen that the power saved is quite considerable 21 1324299 9a a 27... '. Although the fifth embodiment requires two logic circuit units, that is, one flip-flop 101 and one multiplexer 102, the number of switching reductions is obviously larger than that of the first embodiment and the gate 610 or the second. The gate 710, the multiplexer 810, and the latch 910 are much more similar to the third embodiment. The advantages obtained by increasing the number of enable signals can be easily seen from the comparison between the 13th and 14th. Please refer to the thirteenth figure, which is a schematic diagram of using the consistent signal ® in one of the four byte width busbars to simplify the number of output switching. Looking back at the second diagram, each bus has a consistent energy signal, and the number of switching simple cells corresponds to the number of bytes in the bus width to reduce the number of output switchings. For the sake of illustration, the thirteenth figure considers a bus with a width of four bytes. The original output signal of this four-byte width bus is expressed in units of octets, such as AnBnCnDn, and η can be any integer. A single enable signal controls the output of these four bytes in a fully open and fully closed mode. For example, when the enable signal is on, all four bytes A1B1C1D1 will be output as A1B1C1D, and vice versa, 'When this enable signal is off and the method of retaining the previous value, such as A4B4C4D4, the previous A3B3C3D3 value Will be retained as the final output value. Please refer to the fourteenth figure, which is to use four enable signals in one bus of the width of four bytes to simplify the number of output switching 22 1324299, Ί

A schematic diagram. The processor structure supporting the waveform shown in Fig. 14 is the processor shown in Fig. 4. The number of switching simple cells and enable signals corresponds to the number of bytes of the bus width to reduce the number of output switching. A bus with four byte widths will have four switching simple cells and four independent enable signals, each controlling the output signal of eight bits. Since most of the bus access operations are 8-bit, 16-bit, and 32-bit, the above enable signals can be turned on 1, 2, or 4 bits, respectively. When four enable signals are turned on, such as A1B1C1D1, all four bytes will be output unchanged. When A2B2C2D2 only turns on a single enable signal 0001, the first three bytes of Bay 1J remain as the previous value and the last byte will change to the new value, and the final output signal will be A1B1C1D2. Changing the two-tuple can be observed when A3B3C3D3 and A5B5C5D5 are observed. The number of output switchings is further reduced by further dissolving the enable signal of the control bus. Comparing the number of switchings of the two figures, the thirteenth picture with a single consistent energy signal is completely switched three times; the fourteenth picture with multiple enabling signals is partially switched three times (A2B2C2D2 is switched by a quarter, A3B3C3D3 and A5B5C5D5 are switched halfway each). Therefore, the number of switchings saved is reduced from 3x32 or 96 bits to (0.25+0.5+0.5)χ32 or 40 bits, and the province's ratio is 58.5%. Please refer to the fifteenth figure, which is to switch the simplified unit operation 23

A schematic diagram of one of the ways. After the process starts, step 151 is performed, wherein one of the output signals and the consistent energy signal of the user is received by each switching unit. In a next step 152, it is determined whether the enable signal corresponding to the currently output address/lean/control output bit/byte signal is on. If the enable signal is indeed on, then step 153 is performed to cause the above-mentioned round-trip signal to become the final turn-out signal by switching the simplified unit. Conversely, if the enable signal is off, the flow proceeds to two steps to perform the simpler number of output switching times provided by the present invention. The first method is as shown in the sixth to ninth diagrams. When the enable signal is off, the output value is set to - the default value. The second method, as shown in the tenth figure, retains the output value as the previous value when the enable signal is off. Both of the above methods can effectively reduce the number of output switching. Next, in a second step 155, it is determined whether the current address/data/control output bit/bit=group signal is the end of the output address/#material/control signal. If not, then each of the remaining address/data/(4)-transmission TG/byte signals will go through the process of steps 152 to 155 until the output address/data/control signal ends. Furthermore, if the end of the output address/data/control signal has been reached, as shown in step 156, the switching simple unit will continue to wait for the next output wire/_/ control number to arrive. When the secondary-output address/data/control (4) arrives, the entire loop will return to heart 151. Again, once again, a complete address/data/control 24 1324299 H27· '· Year Month Day Correction f Each page of the i-signal/bytes signal will go through the flow of steps 151 to 155, Jane saves the number of switchings and thus reduces power consumption and improves system consumption. The foregoing embodiment uses a gate and/or gate/multiplexer/latch to achieve an output value set to a default value or a flip-flop and a multiplexer to retain the output value as a previous value. Jane saves the number of output switches. It is noted that other circuits that are within the scope and spirit of the present invention can be implemented. For example, a combination of other logic circuit units or logic circuit units such as a series of gates can also set the output value to a default value. Similarly, the above-described flip-flops and/or multiplexers may be replaced by other equivalent logic circuit units or combinations of logic circuit units. In the present invention, the embodiments shown in the sixth to tenth embodiments and the contents of the present specification are merely exemplary of specific advantages, which can be achieved by the use of the switching simple unit in the embodiments of the present invention. Obviously, many modifications and differences may be made to the invention in light of the above description. It is therefore to be understood that within the scope of the appended claims, the invention may be The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Within the scope. 25 1324299

BRIEF DESCRIPTION OF THE DRAWINGS The first A diagram is a block diagram of a simplified computer system; the first B diagram is a block diagram of signal transmission in a core of a processor in the prior art; A block diagram of a decoding unit in the prior art; • A second diagram is a block diagram of a decoding unit according to the present invention; and a second diagram B has a plurality of switching simple units to connect an output bit A block diagram of a processor of an address bus, an output data bus and a control signal bus; the third picture is a plurality of switching simple units of a microprocessor for an output data bus φ The block diagram is a block diagram of a plurality of switching simple units in a microprocessor for an output data bus; the fifth picture is a plurality of switching simple units for external connection of a processor A block diagram of an output address bus, an output data bus and a control signal bus; the sixth figure is a switch according to a first embodiment of the present invention 26 is a block diagram of a unit in accordance with a second embodiment of the present invention; and FIG. 1 is a block diagram of switching a simplified unit according to a third embodiment of the present invention; FIG. 9 is a block diagram showing a switching unit in accordance with a fourth embodiment of the present invention; and a tenth block diagram showing a simplified unit in accordance with a fifth embodiment of the present invention; 11 is a schematic diagram showing the number of switching times of the first method in which the output value is set to a predetermined value according to the first to fourth embodiments of the present invention; A second method for retaining the output value of the previous value disclosed in the fifth embodiment to reduce the number of output switching times; 'the thirteenth figure is to utilize the chimney in one of the four byte widths. § No. 1 is a schematic diagram of the number of times of output switching; the fourteenth figure is a schematic diagram of using four enable signals in one of the four byte widths to simplify the number of output switching times; 27 1324299

The fifteenth figure is a schematic diagram of the flow of switching the operation of the simplified unit. [Main component symbol description] 100 switching simple unit 101 flip-flop 102 multiplexer 110 processor 120 memory unit 130 output-in subsystem 140 output-in device 150 address bus 151 to 156 implementation of an embodiment of the present invention Step 160 Data Bus 170 Control Bus 180 Processor 181 Processing Core 182 Decoding Unit 190 Decoding Unit 191 Receiving 192 Decoding 193 Transmitting 28 1324299 48.牟ί·|Τ日修.! k 210 Switching Simplified Unit 211 Switching Simple province unit 212 switching simple unit 220 processor core 230 decoding unit 250 decoding unit 251 reception 252 decoding 253 transmission 254 transmission enable signal 257 enable control signal 311-31M switching simple unit 330 decoding unit 411-41M switching simple province Unit 430 decoding unit 510~512 switch simple unit 540 decoding unit 530 processor 600 switching simple unit 610 and gate 700 switching simple unit 29 1324299 fgsm: '27, j years. Βί) 710 or gate 800 switching simple Provincial unit 810 multiplexer 900 switching simple province unit 910 latch

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Claims (1)

1324299 τκ %〇 uyQii^y4o -, the scope of patent application: 1. A processor system comprising: a processor core, present in the processor to execute instructions and generate raw output signals; and ' At least one switch unit is connected to connect at least the output signal of the processor, and each of the switching units receives the enable signal and the output. 'Every-the city's simplified unit contains at least—a logic circuit unit to cause the output signal to be a default value or to remain as a previous value when the enable signal is _ and to enable the original when the enable signal is on The output signal is switched to the simple unit, and the resulting output signal is replaced by the final output signal. 30 (^ withdrawal day ... ... year, month, day, repair, page change, revision 2. According to the patent system of the scope of the patent application, and the above-mentioned switching system is Each ^ tuple (four) money channel and the enabling signal are independently mixed (four) each (four) byte output channel, so that when the age is older, the original output signal is outputted by each tuple The signal is - default or reserved as - previous value, and when the enable signal is on, each bit of the original output signal is rotated through the switching unit. 3. According to the scope of the patent application The processing of the item (4), wherein each of the above-mentioned switching units includes the following possible changes: controlling each bit; controlling each byte; and 31 1324299 sa 1L>;7 controlling any number of bits. The enabling signal according to the scope of the patent application is divided into a plurality of byte signal channels. 5. According to the processor system of claim 1, the original output signal includes the following possible changes. Address a data; and a control signal. 6. The processor system of claim 1, wherein the enabling signal comprises the following possible changes: an address enable signal; a data enable signal; and an enable signal for the control signal. The processor system of the above, wherein the superior 4 controls each processor independently. According to the processor system of claim 1, the above-mentioned switching simple unit also includes the following possible changes: When the enable signal is off, the original round is wide. It is an internal value and the original is when the enable signal is on. The lead signal is passed through the switching unit; the signal is sent to the gate to cause the original wheel to be a default value when the enable signal is off and the original wheel 32 1324299 when the enable signal is turned on. By switching the simplified unit; a multiplexer to make the original output signal a default value when the enable signal is off and let the original output signal pass the switching simple unit when the enable signal is turned on; And a latch to cause the original output signal to be a default value when the enable signal is off and to cause the original output signal to pass through the switching simple unit when the enable signal is turned on. 8. The processor system according to claim 1, wherein the switching unit comprises: a flip-flop; and a multiplexer comprising a first input signal from the multiplexer And outputting, by the flip-flop, a feedback signal, a second input signal to receive the original output signal, and a selection signal to receive the enable signal, whereby the original output is when the enable signal is off The ® signal is retained as a previous value and when the enable signal is turned on, the original output signal is passed through the switching simple unit. 9. The processor system of claim 1, wherein the switching simple unit is located inside or outside the processor. 10. A processor system comprising: a processor core resident within the processor to execute instructions and generate an original output signal, the processor core further comprising a decoding unit to generate a consistent energy signal at 33 U24299; and at least one switch The simple unit is connected to the output signal of the processor, and each of the cut_original output ^β is received a few times earlier - the enable signal and the original 'mother' - the unit contains at least - logic circuit::: When the enable signal is off, the original round-off signal is two = or reserved as - the previous value and when the enable money is activated The initial output signal is passed through the switching unit, and the final output signal is substituted for the original output signal. The processor system according to claim 10, wherein the decoding unit pair has been reduced. Age riding decoding (four) students can be numbered and decoded instructions. ° 12. According to the scope of the patent application, the processor system, The enabling signal generated by the decoding unit described above is used to determine whether the original output signal needs to be updated. 13. The processor system of claim 1, wherein each of the switching simple units comprises controlling the following possible changes of a bus: controlling each bit; controlling each byte; and controlling Any number of bits. According to the processor system of claim 10, wherein the above-mentioned enabling signal is divided into a plurality of sub-signals to independently control each of the tuple signal channels. 15. The processor system according to claim 10, wherein the switching unit includes the following possible changes: a gate is used to make the original output signal a default value when the enable signal is off and when When the enable signal is turned on, the original output signal passes through the switching simple unit; or the gate is used to make the original output signal a default value when the enable signal is off and when the enable signal is turned on The original output signal passes through the switching simple unit; a multiplexer causes the original output signal to be a default value when the enable signal is off, and causes the original output signal to pass the switch when the enable signal is turned on a simple unit; and a latch to cause the original output signal to be a default value when the enable signal is off and to cause the original output signal to pass through the switch when the enable signal is turned on. 16. The processor system of claim 10, wherein the switching unit comprises: a flip-flop; and a multiplexer including a first input signal from the multiplexer Outputting and receiving a feedback signal via the flip-flop, a second input 35 sa ii- ^ .. entering the L number to receive the original output signal, and - selecting a signal to receive the monthly Ms number When the energy signal is off, the original output L number is guaranteed to be the previous value, and when the enabled money is turned on, the original output k number is passed through the switching simple unit. 17. A method of saving processor power consumption, comprising: receiving an original output signal and a consistent energy signal; determining whether the enable signal is turned on; and although the enable signal is on, causing the original turn signal to be a final The output signal; and when the enable signal is off, the original output signal is set to a default value or tied to a previous value. 18. The method of saving processor power consumption according to claim 17 of the scope of the patent application, wherein the raw output signal comprises the following possible changes: in units of one bit; in units of one-tuple; and in any number of bits Yuan is the unit. 19_ The method for saving processor power consumption according to claim 17 of the patent application scope, further comprising: dividing the enable signal into a plurality of secondary signals to independently control each of the byte signal channels. 36 1324299 Case No. 095112948 November 27, 1998 Revision page processor QUIET_ ADDR~ Final output signal QUIET_ DATA Final output signal QUIET_ CONTROL Final output signal 1324299 9 good m QUIET-ADDR~ Final output signal QUIET_ DATA~ Final output signal QUIET_ CONTROL Final output signal Fifth figure 1324299 « - VII. Designated representative figure: (1) The representative representative picture of this case is: (fifteenth). (2) A brief description of the components of the present drawings: 151 to 156. The implementation steps of an embodiment of the present invention. 8. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: