TWI323929B - A stacked non-volatile memory device and methods for fabricating the same - Google Patents

Description

1323929 IX. Invention Description: [Related application materials] This case is the priority date of the US provisional application filed on December 9, 2005. The application number of the application is 60/748,807 and the invention name is "Process". Of Multi Layer NAND NROM". FIELD OF THE INVENTION The embodiments of the present invention relate to a non-volatile memory component and a method for fabricating the same, and more particularly to a stacked non-volatile memory component and method of fabricating the same. [Prior Art] Non-volatile memory components are used in more and more products. For example, flash memory components are used in MP3 players, digital cameras, storage elements in computer files, and the like. As applications increase, so does the demand for memory toward smaller sizes and larger memory capacities. This need requires the manufacture of high-density memory. Therefore, the direction of research and development is toward increasing the density of conventional non-volatile memory elements. One of the ways to increase the density of non-volatile memory elements is to use stacked memory elements, i.e., elements in which multiple layers of memory cells are stacked on each other. Unfortunately, so far no research and development energy has been invested in such stacked memory elements. For example, the design of stacked nitride read-only memory is not much. This phenomenon is due in part to the fact that stacked memory elements are not necessarily compatible with current processes and may result in inefficient and costly fabrication of stacked memory elements. There are other ways to increase the density of conventional non-volatile memory elements, however these methods are not necessarily applicable to all applications. Therefore, 5 1323929 still has a need to increase the density of conventional non-volatile memory elements. A particular non-volatile memory element is a nitride read-only memory element. 1 is a schematic diagram of a conventional nitride read-only memory structure 150. As shown, the nitride read only memory 150 is constructed on a substrate ι52. The substrate may be a P-type substrate or an N-type substrate, but for various design reasons, a P-type germanium substrate is generally preferred. The source/drain regions 154, 156 can then be implanted in the substrate 152. The capture structure 158 is then formed over the substrate 152 between the source/drain regions 154, 156. Control gate 160 is then formed in capture structure 158

The source/drain regions 154, 156 are germanium regions doped with dopants of the opposite type to the substrate 152. For example, when a p-type germanium substrate is used, N-type source/no-polar regions 154, 156 are implanted. Charge trapping,,,. The structure 158 includes a nitride capture layer and an insulating oxide layer between the capture layer and the channel 166 of the substrate 152. In other embodiments, the capture structure 158 can include a nitride capture layer sandwiched between two insulating (dielectric) layers, such as an oxide layer or a hafnium oxide layer. These configurations are commonly referred to as oxide-nitride-oxidation capture structures. The charge can be in the capture structure 158, in close proximity to the source/drain region = independent, 162, 164. Each of the charges 162, 164 can be maintained in one of two, and one state, that is, a stylized state or an erased state, and the two states ΐ = the presence or absence of a subroutine. This configuration allows the storage of double-bits, and * requires the use of complex multi-order cell technology « 15 ° ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ gentleman into the blush without affecting other storage areas . A: Recalling the stylization of cells by applying a voltage to bring the main entrance into the nitride layer of the capture structure 158 close to the end of the cell. The 6 shows that the hole is injected into the nitride layer by applying a voltage, so that h1 cancels the electrons stored in the nitride layer when it is first programmed. The nitride read-only memory element was constructed by fabricating the memory cell 歹2 as shown in Fig. 1. The array system connects cells with word lines and bit lines. The chemical read-only memory elements (e.g., the elements shown in Fig. 1) can be stored in a single cell in multiple bits, so the nitride read-only memory element = I is increased by using a stacked structure. Unfortunately, 'nitride-only reading is implemented because the heap is less abundant, and even if it is implemented, its process is not efficient and the manufacturing cost is increased. SUMMARY OF THE INVENTION The method disclosed in the prior art discloses that the method disclosed in the method for manufacturing a stacked non-volatile memory element uses an efficient process technology, and the embodiment of the invention can be reduced. The size of the present invention can be utilized in the manufacture of a 'stacked nitride read-only memory. The stacked vapor-only read-only memory element can be used in another object of the present invention. The method potential memory element 'configurable for reverse (NAND) operation. Preferably, the structure and method of the present invention are described in detail below. The early programming of the present invention is not intended to define the present invention. The invention is claimed by

Defined. The embodiments, features, objects, and advantages of the present invention are obtained by the following description of the patent scope and the accompanying drawings. "I [Embodiment] It can be understood that any size described below, Measurement, range, potential 1323929 includes a thin film polycrystalline layer deposited over insulating layer 202. It will be appreciated that in other embodiments, the semiconductor layer 204 can comprise an N-type semiconductor material. A capping layer 206 can then be formed over the semiconductor layer. For example, in a particular embodiment, the capping layer 206 can comprise a tantalum nitride material.

As shown in FIG. 4, conventional lithography techniques can be used to pattern and etch layers 204 and 206. Figure 5 is a top view of the layers in the components manufactured so far. Figure 4 is a cross-sectional view taken along line AA of Figure 5. Thus, as shown in Figure 5, layers 206 and 204 are patterned and etched into region 205, which passes through insulating layer 2〇2 from top to bottom. As explained below, region 205 will form the bit line of the first bit line layer 11 of Figure 2 .

Referring to Figure 6, a dielectric layer 2〇9 can then be formed over the insulating layer 2〇2 as shown in the figure. For example, the dielectric layer 2〇9 may be a germanium dioxide layer and may be formed by a still-dense plasma chemical vapor deposition (HDp_CVD). Referring to Fig. 7, the portion of the dielectric layer is removed to expose the remaining portion of the cap layer 206 and the remainder of the semiconductor layer 2〇4. For example, a conventional wet etching process (such as etch etching) can be used to remove portions of the dielectric layer 209. In order to remove the correct number of dielectric layers 209, a method of having a high ratio of selection for the dielectric layer 2G9 and the cap layer can be used. The process is on top of the overlay and between the remainder of the semiconductor layer collapse. 7 The top view of the layers made so far. Figure 7 is a cross-sectional view of the f AA line. Therefore, the electrical regions are located between the regions 205. As shown in the figure, the 210 system covers a part of the cover layer 2〇6. Please refer to Figure 9, the remaining layer of the cover layer. Remove the area of the dielectric layer 2〇9 in this = Use a hot sulphuric acid to remove the remaining part of the cover layer. When the remaining portion of 9 1323929 206 is overlaid, the dielectric region 21 of the dielectric layer 209 is automatically removed because the dielectric region 210 is not connected to the dielectric region 212, as shown in Figures 6-9. The process illustrated is described in US Patent No. 6,380, 068 ^ Method for Planarizing a Flash Memory Device, which was assigned to the claimant on April 30, 2002, and is hereby incorporated by reference. The process illustrated in Figure 69 can be efficiently planarized for the remaining surface shown in Figure 9. Thus, the process described herein is compatible with newer, more efficient process technologies.

This feature will make the manufacture of stacked non-volatile memory components more efficient and economical. The first figure is a top view of the layers formed so far. Figure 9 is a cross-sectional view taken along line AA of Figure 10. Therefore, the insulating layer 2 〇 2 is covered by the oxide regions 212 and the bit lines 2 〇 5 which are alternately arranged, wherein the ridge lines 205 are formed by the remaining portions of the semiconductor material 2 〇 4 . As shown in the figure \1-13, the word line 22〇 can then be formed over the bit line 2〇5. As shown in Fig. 12, a capture structure 222 can be formed first over the remaining portion of the semiconductor layer 204 and over the insulating region 212. The word line conductor 224 can then be formed over the capture structure 222, and a second capture structure 218y is then formed over the word line conductor 224 to form the word line 220. A layer of bismuth (not shown) may then be formed over the second capture structure 218. Some of the layer structures can be patterned using conventional lithography techniques and etched ‘:f into word lines 22〇 as shown in FIG. The configuration of the engraving process is set such that the high-density plasma oxide region 212 is used as an etched two-fr high-density plasma oxide layer (not shown) which can then be formed on the thunder-bending sub-line Above 220 'includes a nitride layer (not shown). This high density y is then partially etched' and a portion of the high density oxide layer can be removed by the remainder of the hair styling layer (not shown) in a manner as shown in the phase '9. To this end, the high density oxide region 1323929 field 242 will be left between the word lines 220 as described in Figures 14-15. In the embodiment illustrated in Figures 11-12, the capture structures 218, 222 are oxide nitride oxide structures (ΟΝΟ). Therefore, the capturing structures 218 and 222 are formed by successively forming an oxide layer, a nitride layer, and an oxide layer. For example, the oxide layer can include hafnium oxide and the nitride layer can include a tantalum nitride layer. It will be appreciated that the tantalum nitride layer acts on the capture layer' to capture charge during stylized operations. The trapped charge changes the threshold voltage of the memory cell, and the threshold voltage determines the stylized state of the cell. Sections 23-23 show examples of various capture structures that can be used in element 1〇〇. For example, referring to Fig. 12, various structures in the 23rd-23th drawing can be used as the capturing structure 222. The first exemplary embodiment shown in Fig. 23 includes a 矽_oxide_nitride_oxide-dream (so>kds) structure. The structure includes an oxide layer 272, a nitride layer 274, and an oxide layer 276 which are successively formed on the polycrystalline layer 214. The I oxide region 272 functions as a channel dielectric layer, and the nitride layer The 274 system acts as a capture layer to capture charge. When the SONOS structure of Fig. 23A is used, the charge is injected (electron in the capture layer 274, and stored in the capture layer 274 of a particular cell. The erasing of a cell, the hole is directly worn by the capture Any of the electrons previously stored in the capture layer 274 are offset by layer 274. The tunneling of the holes in the capture layer 274 is achieved by the Fuller-Nordham tunneling effect. The oxide layer 272 can be a thin layer. The oxide layer 'e.g., may have a thickness of less than 3 nm. For example, cells formed using the SONOS capture structure of Figure 23 can be used in a NANd recording application. ~ _Using the SONOS capture structure shown in Figure 23A The constructed NAND = piece ' may show a poor charge retention effect because leakage current is generated in the charge retention process ^' hole directly tunneling into the capture layer 274. Figure 23B shows a nitride read-only memory capture Structure. Similarly, 11 1323929

The nitride read-only memory capture structure includes a germanium structure that successively forms an oxide layer 278, a nitride layer 280, and a second oxide layer 282 over the evening region 214. However, the thickness of oxide layer 278 herein is between about 5-7 nm. The stylization of cells formed by the nitride read-only memory structure as shown in Fig. 23 is achieved by injecting electrons into the layer 280. The thinness formed by the nitride read-only memory structure as shown in Fig. 23 can then be erased by the hot hole erasing technique. The nitride read-only memory structure shown in Fig. 23β can be used in N〇R (reverse) applications; however, the components constructed using the nitride read-only memory structure of Fig. 23B show the hot hole erasing procedure. Some damage caused.

Fig. 23c is not a sound force; (a BE5aN〇s structure. The BE-SONOS structure shown in Fig. 23C is formed by continuously forming an N〇 structure 294, then forming a nitride layer 290 and a dielectric layer The germanium structure 292 is formed by sequentially forming an oxide layer 284, a nitride layer 286, and an oxide layer 288 on the poly germanium layer 214. As in the SONOS structure of Fig. 23, The BE_s〇N〇s structure of Fig. 23c uses the Fuller-Nordham hole penetration effect to erase memory cells; however, the BE_S camphor structure does not have the effect of 穿ίίιΐ by the (four) current' or The damage caused by the hot hole is erased. In addition, the BE-SONOS structure of HL can be used in the reverse or reverse application. 夕ΠΛΤΓΛ ^ 23; Figure 糸 ^ is not in the BE_S〇N〇S structure in Figure 23C? And ^ 294 = ▼ diagram. 帛 231 diagram shows the data when the data is saved = if the erased band diagram. As shown in Figure 231, the energy in i = cookware / is not enough Overcome, including _ household ^ blocking, you %, \ barrier. Because the hole wearing effect of the hole is 294 : L, almost no leakage current. As shown in Figure 23J, when Chun Gu is speaking, the _ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ The energy barrier represented by 288 is almost 12 1323929, which is caused by the energy band offset generated by the presence of the high field. The 23D-23H diagram shows other elements that can be used in the capture layer of the component ι〇〇. Illustrative structure. For example, '23D depicts a SONS structure that can be included in the capture structure of element 100. The structure shown in FIG. 23D includes a thin oxide layer formed over polysilicon layer 214. 302. A nitride layer 304 is then formed over the thin oxide layer 302. A gate conductive layer 224 can then be formed over the nitride layer 304. The thin oxide layer 302 acts as a tunneling dielectric layer and charge Can be stored in the nitride layer 304. Figure 23E illustrates the upper BE_SONOS structure that can be used for the capture structure in the device 1 。. Thus the structure shown in Figure 23E includes an oxide layer 306, It is formed on the polysilicon layer 214. A nitride layer 3〇8 is then formed on Above the layer 306, an NMOS structure 315 comprising an oxide layer 310, a nitride layer 312, and an oxide layer 314 is then formed over the nitride layer 308. In the embodiment illustrated in Figure 23, The oxide layer 306 acts as a tunneling dielectric layer, and charges can be trapped in the nitride layer 308. Figure 23F depicts a bottom SON〇s〇s structure that can be applied to the capture layer of element 100. The structure shown in FIG. 23F includes an oxide layer 316 formed over a polysilicon layer 214, and a nitride layer 318 formed over the oxide layer 316. A thin oxide layer 32 is subsequently formed on the nitride layer 318. A thin polycrystalline layer 322 is then formed. Another thin oxide layer 324 is then formed over the polycrystalline layer 322. Thus, layers 320, 322, 324 form a 〇s〇 structure 321 adjacent gate conductor 224. In the embodiment illustrated in Figure 23F, the oxide layer can act as a tunneling dielectric layer' and charge can be stored in the nitride layer 318. Figure 23 (5 shows a bottom SOSONOS structure. It can be seen that a thin OSO structure 325 is formed on the polycrystalline layer 214. The 〇s〇 structure 325 includes a thin oxide layer 326, a thin polysilicon. Layer 328, and thin oxide layer 330. Nitride layer 332 is then formed over 〇s〇 structure 3, 13 1323929 and oxide layer 334 can then be formed over nitride layer 332. In Figure 23G In the embodiment, the OSO structure 325 can function as a tunneling dielectric layer, and the electricity can be stored in the nitride layer 332. Figure 23H shows an example of an S〇n〇NS structure, which can be used for components. In the 1 捕捉 capture structure, it can be seen that an oxide layer 336 is formed over the polysilicon layer 214, and a nitride layer 338 is formed over the oxide layer 336. An ON structure 341 is then formed on Above the nitride layer, the ON structure 341 includes a nitride layer formed on the nitride layer 338, and a nitride layer formed on the thin oxide layer 340. * The embodiment shown in FIG. The oxide layer 330 can act as a dielectric layer and the charge can be trapped in the nitride layer 338. In an example, the capture structure may include nitride or arsenic oxynitride, an electrical value material such as oxidizing, oxygen partial, nitriding, etc. 八蚌一I Tian may use any dielectric structure or dielectric material as long as It can meet the requirements of special applications. The text / / J multi-body / 24 can be formed by a Ν + or Ρ + conductor material, such as ί ΓΪ鶏 poly _ _ / / (4) materials, or - metal, 丄In the semiconductor: ί, 2 2 pack 0 „ by the bungee f bungee region f16 can form 205. Therefore, the area of the bit line layer 204 covered by the blood quilt line 220 is the area ^, 216, the area *216 can be implanted and heat driven into the semiconductor I am aligning with the process. - In the U ^ can be solved, this process is a self-contained system for the implementation of the source, the source and the immersive area" Half-domain, semiconductor layer 2〇4 package N” conductor material implementation = solution 疋' P+ region should be formed after using the pole/drain region 2, ^216, the semiconductor layer 204 will include the source "region) and The P-type region is below the heart, and under the spring 220. As explained below, the 1323929 P-type region 214 forms a channel region for a particular memory cell. Figure 12 is a cross-sectional view of the structure of the second diagram taken along line AA'. As shown, the P-type region 214 is still below the word line 220 and is separated by a dielectric region 212. Figure 13 is a cross-sectional view taken along line BB. As shown in Figure 13, an N+ doped region 216 is formed between each word line 220 and is separated by a dielectric region 212. As shown in Figures 14 and 15, a high density plasma oxide region 242 can be formed between each word line 220. As shown in FIGS. 16-18, a second bit line layer (eg, bit line layer 130) can then be formed over word line 220. Thus, bit line 228 can be formed over word line 220 as shown in FIG. The bit lines can be formed using the same process as forming the bit lines 205, such as shown in Figures 6-9. Bit line 228 is thus separated by dielectric region 236. Figure 17 is a cross-sectional view taken along BB'. As shown, the first bit line layer 110 is separated from the second bit line layer 130 by a high density plasma oxide layer 242 in a region between the respective word lines 220. Figure 18 is a cross-sectional view taken along AA'. As shown, bit line 228 is formed over word line 220 and word lines are formed over bit line 205. As shown in Figures 19-21, word line 230 can then be formed over bit line 228 to form a second word line layer (e.g., word line layer 140). Like word line 220, word line 230 can include a word line conductor 246 that is sandwiched between capture structures 240 and 244. This drawing is shown in Fig. 21, which is a cross-sectional view taken along line AA of the layers of Fig. 19. Figure 20 is a cross-sectional view taken along BB'. Therefore, in the embodiment of Fig. 21, the capturing structures 240, 244 are formed in such a manner as to form an oxide layer, a nitride layer, or an oxide layer. For example, the oxide layer can include cerium oxide and the nitride layer can include cerium nitride. It will be appreciated that the 'nitride layer acts as a capture layer to capture charge when the component is programmed. The trapped charge changes the threshold voltage of the 15 1323929 cell, and the threshold voltage determines the state of the cell. The capture structure 24A, 244 in the embodiment may include any of the structures in the 23α_23η. In the embodiment, the 'capture structure may include nitrogen cuts of oxidized oxide, ΐ dielectric value material' such as oxidizing, oxidizing, nitriding, and the like. /ν二,. Any dielectric structure or dielectric material can be used as long as it meets the requirements of a particular application. Ge / / J He layer / 46 can be formed by a talk or rape conductor material, such as more

:; bucket, 曰矽 曰矽 / 矽 / / polycrystalline germanium material, or a metal, such as aluminum, copper, or tungsten. After the "on" sub-line 230, the source and j: and the polar regions 234 may form an area in which the line 228 is not covered by the word line 23A. Thus, the source drain region 234 can be implanted and thermally driven into the bit line 228. It can be understood that the process is a self-aligned process. In the embodiment shown in Fig. 19, the 'source and drain regions are N+ type regions formed of arsenic or phosphorus because the bit line 228 includes a P-type semiconductor material. It will be appreciated that the P+ region should be formed in an embodiment using an N-type semiconductor material.

After forming the source and drain regions 234, the bit line 228 will include a source/drain region 234 (doped into a region) and a P-type region 232, wherein the P-type region is still below the word line 230. As explained below, the p-type region 232 will form a channel region for a particular memory cell. As shown in Fig. 22, the process shown in Figs. 3-21 produces a stacked memory array which includes a plurality of memory cells. By way of example, in Figure 22, three such cells 250, 252, 254 〇 regions 234 are formed to form the source and drain regions of each cell, and current lines flow through the cells in the direction indicated by the arrows. These cells can be configured for reverse (NAND) operation. The memory cells 250, 252, 254 are located in the upper layer of the array; however, this array includes a layer of cells that are stacked one on another in a plurality of layers, which can be understood from the cross-sectional view of Fig. 21, which is incorporated herein by reference. As shown in Fig. 21, the capture structure 240 forms the gate structure of the cells 250, 252, 254; the region 232 below the capture structure 240 forms the channel region of the cells 250, 252, 254; the source/drain regions on either side of the word line 230 234 forms the source and drain regions of cells 250, 252, 254 (see Figure 22). In addition, capture structure 218 can serve as a gate structure for memory cell layers (e.g., cells 256, 258, 260) under cells 250, 252, 254. Region 232 above capture structure 218 forms the channel region of cells 256, 258, 260; while source/potential region 234 on either side of word line 230 forms the source and drain regions of cells 256, 258, 260. As shown, conductor 224 forms a word line ' to supply a voltage to the gate structure of cells 256, 258, 260. The third layer of memory cells (e.g., cells 262, 264, 266) are located below cells 256, 258, 260, as shown in Figure 21. The capture structure 222 forms the gate structure of the cells. Conductor layer 224 forms a word line' to provide a voltage to the gate structure of a plurality of cells. The region 214 below the word line 220 forms the channel region of these cells and the region 216 located at the word line 220 forms the source and drain regions of these cells. Figure 24 is a diagram showing an exemplary stacked non-volatile memory component configured in accordance with an embodiment of the present invention. Figures 25-35 illustrate the various process steps for fabricating the memory element of Figure 24 in accordance with an embodiment of the present invention. The embodiment described in Figure 24-35 provides a relatively simple design in which the word lines are not shared by multiple memory cells. As shown in Fig. 24, the process illustrated in Figures 24-35 generates a stacked memory structure including an insulating or dielectric layer 2402 and including stacked word lines and bits over the insulating layer 2402. The line layers are separated by a dielectric layer (or inter-cell dielectric layer) 2404. The word line and bit line layer includes a bit line 2410 and a word line layer 2406, which are separated by a capture structure 2408. As described below, a layer of one-level lines can be deposited first, and then patterned and etched to form bit lines 17 1323929 2410. A capture structure layer can then be deposited and then deposited over the word line structure layer. The word line and capture structure layer can then be patterned/twisted to form a word line over the bit line 2410. A capture structure 24〇8 located above the bit ^10 and below the word line 2406 can function as a capture layer to store charge in a memory cell. 25-35 illustrate an exemplary process for fabricating the components of Figure 24. As shown in Fig. 25, a polysilicon layer 25〇4 can be deposited on an insulating layer 25〇2.

ί上二绝2 5 〇 2 may include an oxide material, such as cerium oxide material ^ more than 夕 layer 2, after which the thickness may be between about fine to Angsts. For example, the thickness of the δ, 矽 矽 layer 2504 may preferably be about 4 〇〇. In the second embodiment, the I's layer 2504 can then be patterned and etched using conventional lithography to create bit line regions 25〇6. For example, the insulating layer 2502 can function as an etch stop layer of the etching step to generate the domain 2506. The overall thickness of the structure shown in Fig. 26 can be 1 angstrom, and preferably about 400 angstroms. Heart, spoon 2〇0 to

. An alternative process for etching the polysilicon layer 25〇4 is illustrated in Figures 27A-27C to generate bit line regions 2506. Referring to Figure 27A, a cover layer 2528 can be formed over the polysilicon layer 2504. For example, the cap layer 252A8 may include a tantalum nitride layer. Polysilicon layer 2504 and cap layer 2528 are then patterned and etched using conventional lithography techniques, as shown in Figure 27. Similarly, insulating layer 2502 can function as an etch stop layer for the etch process. In May, after the layers 2504, 2528 are touched to generate the bit line regions 2506 and 2530, the regions 2530 can be removed using conventional processes.

Referring to FIG. 28, a capture structure layer 2508 can be formed over the insulating layer 2502 and the bit line region 2506. As noted above, capture structure layer 2508 can include any of a number of capture structures, such as s〇N〇S, BE-SONOS, upper BE-SONOS, SONONS, SONOSLS, SLSLNLS, and the like. In other embodiments, the capture structure layer 2508 may comprise a nitride stone 18 1323929 ί, ίίίJ material, or a high dielectric material, such as oxidation, oxidation, please refer to Figure 29, - word line structure layer Measured h example = 125 () may then be formed on the capture junction capture structure layer 2508 above the polycrystalline sand material day 251 〇 may include deposition on the bit line 2506 to form a word line as shown in Figure 31 'This 2508. This process generates and has a domain and penetrates the capture structure layer. The capture structure layer should be located in the zone with a region of 212. The 3D view line of the figure 2; the ‘two-line character line 2506 is in the sub-area of -P I more than 0 bottom. For example, if the source recording area 25H is used, it can be buried in the portion covered by the N-type coffee. ^者, 2鸠 is not a word line. The crystal material is 2, and the right sub-line 2506 is an N-type multi-bit line 25& , P-type source/drain regions are implanted, and the cross-sections of the layers in the figure along the ΑΑ' line are thermally driven. Because / '^曰w lost each layer in the 4 figure along BB, the line made the channel area line 2510 under the covered line 2510 Mm. The original pole and the bungee area 2514 are formed in the character formation process. I'm sure that the source/secret area 2514 is formed on top of the 35th ''---- (or inter-dielectric layer) 2518 line 19 1323929. The other-bit line and the word line layer are formed on the via layer (or the unit between the units using the same process as described above. In this method, any number of word line layers) can be formed. Above the insulating layer 2 5 02, and the interlayer is separated by a dielectric layer (or a dielectric layer 2518. Gate). Please refer to Figure 34 for the memory cell 252〇_2526 to be connected. The memory cells 2520, 2522 are shown in Fig. 2. The source and drain regions of the cells are represented by the associated word line 2. Recorded in the pole / bungee area Cheng 2 514. Channel area is from bit 1 = source

A region 2516 below the word line 251 is formed. These cells = element 'which may be affected by excessive edge effects, but also a larger element width to increase cell current. This is because, as described above, the method of the present invention can be used to characterize features and components. As shown in Figure 36, the erased state of =. In a read operation, a high voltage is applied to the one bit line (BLi), and the stack is recorded (MAD) to the first floating, and the source line is maintained at the position of the 〇 ^ 一Then, a reading voltage (VpAss) is applied to the fine f ° smear ^ (A) can be read by the +7 volt sub-line as shown by the curve of Figure 36. As shown in Figure 37, the card is linked to a chain of fields, retreats and fine works. The periphery of the memory cells that are not programmed by the cells is programmed by applying a + 1 ^ volt method. In Figure 37, the cells (A) are stroked. To the word line of the cell (8), the BL2 system is raised to approximately +8, and the source line is allowed to float. The line is raised to about +9 volts' and the cells associated with cells (C) and (D) are disturbed, while the cells (with =, (9): occur in a moderately tempering manner. The potential is suppressed by the process. In the 20 Θ 23929 stylization operation performed under the above circumstances, almost no stylized interference occurs. Although the present invention has been described with reference to the preferred embodiments, it will be understood by us. The present invention is not limited by the detailed description thereof, and alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. It is to be understood that all of the alternatives and modifications may be made without departing from the spirit and scope of the invention. It is intended to fall within the scope of the invention as defined by the scope of the appended claims and their equivalents. Any patent application and printed text referred to in the preceding paragraph are BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description] Fig. 1 shows a conventional nitride read-only memory structure. Cold Figure 2 shows a stacked nitride structure in one embodiment of the present invention. 3-21 illustrates an example of a process for fabricating a stacked nitride read-only memory as shown in FIG. 2, in accordance with an embodiment of the present invention. Figure 22 is a diagram showing a 3_2i diagram. In the Lu NAND array manufactured by the process, a current path of the selected memory cell is selected. The 23A-H diagram shows an exemplary structure which can be used to form the capture structure of the element of the second figure. The 23I-J diagram shows the 23C Figure 24 is a diagram showing the structure of the structure. Figure 24 is a diagram showing another exemplary stack #volatile memory structure according to the present invention. Figures 25-35 are diagrams for manufacturing according to the present invention. An exemplary process step of the steps of the elements of Figure 24. Figures 36-37 illustrate exemplary operational features of a germanium TFT NAND device in accordance with the method illustrated in the above diagram. 21 1323929 [Signature Description of Main Components] 100 Stacking Nitride read-only memory 102 103,107 insulation capture Layers 103a, b, 107a, b capture layer 104 bit line 104a, b 105 105a, b 106 106a, b 110 120 130 140 150 152 154, 156 158 160 162, 164 166 202 204 205 206 209 210, 212 bit line word line conductor word Element line conductor insulation area insulation area first bit line layer first word element line layer second bit line layer second word element line layer nitride read-only memory $ 夕 substrate source/drain capture structure control gate Charge Channel Insulation Semiconductor Layer Bit Line Region Overlay Dielectric Layer Dielectric Region 22 1323929 214 Polysilicon Layer 216 Source/Torminal Region 218 Second Capture Structure 220 Word Line 222 Capture Structure 224 Character Line Conductor 228 Bits Line 230 character line 232 P-type area

234 source/drain region 236 dielectric region 240,244 capture structure 242 high density oxide region 246 word line conductor memory cell 250,252,254,256,258,260,262,264,266 272,276 oxide layer 274 nitride layer 278,282 oxide layer 280 nitride layer

284,288 oxide layer 286 nitride layer 290 nitride layer 292 dielectric layer 294 germanium structure 302,306,310,314 oxide layer 304,308,312 nitride layer 315 germanium structure 316,320,324 oxide layer 318 nitride layer 23 1323929

322 polysilicon layer 321, 325 OSO structure 326, 330, 334 oxide layer 328 polysilicon layer 332 nitride layer 336, 340 oxide layer 338, 342 vapor layer 341 ON structure 2402 insulating layer 2404 inter-cell dielectric layer 2406 word line layer 2408 capture structure 2410 bit line 2502 Insulation layer 2504 polysilicon layer 2506 bit line region 2508 capture structure layer 2528 cover layer 2530 region 2510 word line 2512 region 2514 source /; and polar region 2516 channel region 2518 dielectric layer 2520-2526 memory cells 24

Claims (1)

1323929 The Republic of China invention patent application No. 095141947 No 刽 之 之 谙 谙 谙 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The component includes a plurality of bit line layers and a plurality of word line layers sequentially formed on each other, the method comprising: forming a first bit line layer, wherein the forming of the first bit line layer comprises: Forming a semiconductor layer on an insulator; patterning the semiconductor layer to form a plurality of bit lines; forming a first word line layer over the first bit line layer, wherein the first word line layer The forming system includes: sequentially forming a first capturing structure, a conductor layer, and a second capturing structure; and after the sequentially forming step, patterning the first and second capturing structures and the conductor layer to A plurality of word lines are formed to define a memory cell including a channel region among the bit lines of the plurality of bit lines arranged in a NAND type array. 2. The method of claim 1, wherein the patterning and etching step of the semiconductor layer comprises: forming a capping layer over the semiconductor layer; etching the capping layer and the semiconductor layer to form a bit a bit line region including the cap layer and a remaining portion of the semiconductor layer; forming a dielectric layer over the etched cap layer and the semiconductor layer; leaving a portion of the dielectric layer to form a dielectric region between the bit line regions and a remaining portion of the cap layer; and removing a remaining portion of the cap layer to remove the portion of the dielectric layer over the cap layer. 3. The method of claim 2, wherein the cover layer 25 comprises a nitride exhibit. The method of claim 1, wherein the dielectric layer is deposited as described in the item, wherein the dioxo prior is deposited by chemical vapor deposition. The method of claim 1, wherein each of the first forms an n-explosive nitride-oxygen and the method of claim 1, wherein each of the first substances (the formation of 〇Nm if comprises forming an oxidation Nitride read-only memory structure of the material-nitride-oxide CONO. The method of claim 1, wherein the towel is - the first ^so:s) = f. The method of forming the method of claim 1, wherein each of the formation of the first-if structure comprises forming an upper layer of cerium-oxide-nitride emulsification. Material-sand-oxide-矽 (SONOSOS) structure. The method of claim 1, wherein each of the formation of the second capture structure comprises forming a bottom layer of yttrium-oxide-mouse-oxide-oxide-矽-(SONOSOS) structure. U. The method of claim 1, wherein each of the formations of the first and second capture structures comprises forming a tantalum oxide oxide nitride - SONONS )structure. The method of claim 1, wherein the forming of the second "second capture structure" comprises forming a layer of ruthenium oxynitride. [beta] is as described in claim i, wherein each The formation of the / and second capture structures includes depositing a high dielectric value material. 15. The method of claim 14, wherein the devaluation material is oxidized (Post 2), Nitrogen (A1N) Or the region covered by the oxidizing electric field is not subjected to the method described in claim 16, wherein the semiconductor 2 semiconductor material, and wherein the formation of the source pole region is included in Ρ The method of claim 17, wherein the method of claim 1 , wherein the conductor layer 19 comprises a polycrystalline material as claimed in the patent application. 27 0 01323929 ? The method described in the scope of claim 4 includes a polycrystalline 5 compound / polycrystalline (four) material. /, U body layer system 2, the method described in the first item, wherein the conductor layer is The method of claim 21, wherein the metal system 23. The second bit line layer described in the second paragraph of the patent application is above the first word line layer, and L is formed to form a 24. The second character line layer of claim 23 The method of the second bit line layer further includes forming - 25. The method of claim 16 wherein the bit lines of the plurality of bit lines are in the _th direction The line is separated from each other in the bit line of the plurality of bit lines in the second direction of the bit line of the plurality of bit lines. 26. As disclosed in the 25th item of the patent application, a source is shared. / 汲 区域 。 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U The adjacent bit line in the bit line is at a distance separating one bit line; the ^-the direction is separated from each other by the character line of the plurality of character lines, the character position, and the complex 28 1323929 The adjacent word lines in the plurality of word lines are separated from each other by a word line along a second direction; the memory cells have a region The area has a first side along the first direction and a second side along the second direction, the first side having a length corresponding to the bit line width and the bit line separation distance And the second side has a length corresponding to the sum of the width of the word line and the distance separating the word lines. 28. A method of fabricating a memory device, the method comprising: forming a first plurality of semiconductor bits Forming a first multilayer capture structure over the first plurality of semiconductor bit lines and forming a word line material over the first multilayer capture structure and forming a second multilayer capture structure Overlying the word line material; patterning the first multi-layer capture structure, the word line material and the second multi-layer capture structure to expose a portion of the first plurality of semiconductor bit lines, thereby forming the word element a plurality of word lines of the line material; forming a first plurality of doped regions within the exposed portion of the first plurality of semiconductor bit lines, the first plurality of doped regions having the first plurality of semiconductor regions Different meta lines An electrical form, wherein the memory cells in the first plurality of memory cells comprise a first plurality of pixel capture lines in the plurality of word lines and from the first plurality of semiconductor bit lines Forming a portion between a channel region separated by a set of doped regions of the first plurality of doped regions in a corresponding one of the semiconductor bit lines; forming a second plurality of semiconductor bit lines to the second plurality of layers Overlying the capture structure; and forming a second plurality of doped regions within the second plurality of semiconductor bit lines, the second plurality of doped regions having a different conductivity type than the second plurality of semiconductor bit lines a memory cell in the second plurality of memory cells, wherein the second multi-layer capture structure is in a plurality of word line lines and a corresponding one of the plurality of semiconductor word lines a portion of a channel region separated by a set of doped regions of the second plurality of doped regions in a corresponding one of the semiconductor bit lines. 30