TWI323380B - Stacked storage capacitor structure for a ltps tft-lcd - Google Patents

Description

1323380 IX. Description of the Invention: [Technical Field] The present invention relates to a low temperature polycrystalline film transistor liquid crystal display, and more particularly to a stacked storage capacitor structure and a method of forming the same. [Prior Art]

Fig. 1A is a top view showing a halogen element of a conventional low temperature polycrystalline germanium thin film transistor liquid crystal display in which a storage capacitor is formed. Fig. 1B is a cross-sectional view taken along line A-A' of the halogen shown in Fig. 1A. Fig. 1C is an equivalent circuit diagram showing the halogen shown in Fig. 1A. As shown in FIG. 1A, a halogen 10 has a storage capacitor 12, a thin film transistor 14, and a halogen electrode 140 formed thereon. A signal line 16 and a gate line 18 are interleaved in the vicinity of the thin film transistor 14 and disposed around the halogen element 10. The pixel electrode 140 and the storage capacitor 12 are electrically contacted with the thin film transistor 14 via a via 146. As shown in FIG. 1B, the prior art provides a substrate 104, a buffer layer 108, a polysilicon layer 112 as a first conductive layer, a gate insulating layer 116, a second conductive layer 120, and a first interlayer dielectric. Layer 124, and a second interlayer dielectric layer 128. The polysilicon layer 112, the second conductive layer 120, and the gate insulating layer 116 interposed between the polysilicon layer 112 and the second conductive layer 120 together constitute the storage capacitor 0773-A31798TWF; P2005028; forever769 5 1323380

(Cst) 12. Next, a metal layer 132 is formed by conventional techniques. Thereafter, a protective layer 136 having a via 146 is formed on the metal layer 132 and the second interlayer dielectric layer 128 by a conventional process. A transparent halogen electrode 140 is conformally formed on the protective layer 136 and the via 146. The above transparent halogen electrode 140 includes indium tin oxide or indium zinc oxide. Moreover, a backlight module 14 8 is placed on the other side of the substrate 104 to complete the thin film transistor array substrate 100 for low temperature polycrystalline thin film transistor liquid crystal display. The arrow 144 represents the light from the backlight module 148. Fig. 1C is an equivalent circuit diagram showing the pixels shown in Fig. 1A. In order to meet the increasing demand for high resolution, the pixel size must be reduced. As a result, the area occupied by the storage capacitor for the low-temperature polycrystalline silicon transistor liquid crystal display must also be reduced to maintain the proper aperture ratio. At the same time, problems such as flicker, image sticking, and cross-talk are likely to occur. Therefore, there is a need in the industry for a new storage capacitor structure that can increase the storage capacity without sacrificing the aperture ratio of the halogen, or to increase the aperture ratio of the low-temperature polysilicon thin film transistor liquid crystal display while maintaining a certain degree. Store capacity. SUMMARY OF THE INVENTION The present invention discloses a stacked storage capacitor structure for a low temperature polycrystalline germanium thin film transistor liquid crystal display. A first preferred embodiment of the present invention includes a substrate, a first storage capacitor, and a second storage battery 0773-A31798TWF; P2005028; forever 769. The first storage capacitor includes a -first conductive layer, - a second Question 2 and 2, standing in the above-mentioned first conductive layer and said second conductive layer, a conductive layer, wherein said second conductive layer is placed on said first upper layer and wherein said first storage capacitor is placed The substrate: channel=day storage capacitor structure further includes a third conductive layer, and the second layer includes a first portion and an extended second portion. The sub-electrical valley state includes a second portion of the second conductive layer, the third conductive layer ... f extending, and - between the second conductive layer and the second portion of the extending portion of the third conductive layer The second portion of the second insulating layer, wherein the second portion of the second conductive layer is extended, is disposed on the first conductive layer and wherein the second storage capacitor is disposed on the storage battery and forms an electrical contact. The first preferred embodiment further includes a protective layer and a halogen electrode, wherein a dielectric layer is formed in the protective layer, and the halogen element 2 is placed on the protective layer. Further, the halogen element is electrically contacted with the first portion of the third conductive layer through the via window. In addition, the first preferred embodiment further includes a second insulating layer disposed between the second insulating layer and the extended second portion of the third conductive layer, wherein the third insulating layer and the second insulating layer The layer has a concave portion. Further, a second preferred embodiment further includes a third insulating layer. The third insulating layer is disposed between the second conductive layer and the second extended portion of the third conductive layer, wherein the second insulating layer has a concave portion and a third portion of the second conductive layer The portion is partially covered by the above-mentioned concave portion 0773-A31798TWF; P2005028; f〇rever769 7 1323380 is directly covered by the above third insulating layer.

According to the first and second embodiments of the present invention, the extended portion of the third conductive layer is used to construct the second storage capacitor, and the second storage capacitor is placed on the first storage capacitor without additional Occupy the area of the element. Therefore, it is possible to increase the storage capacity without affecting the aperture ratio. In particular, the first portion of the third conductive layer is formed simultaneously with the second portion of the extension, so that the process can be simplified and the cost can be reduced. The above and other objects, features and advantages of the present invention will become more <RTIgt; 2A is a top view of a halogen element of a low temperature polycrystalline germanium thin film transistor liquid crystal display according to a first preferred embodiment of the present invention, in which a stacked storage capacitor structure is formed. Fig. 2E is a cross-sectional view taken along line B-B' of the halogen shown in Fig. 2A; and Fig. 2B to 2E' is a cross-sectional view showing the process of the stacked storage capacitor structure. Figure 2F shows the equivalent circuit diagram of the halogen shown in Figure 2A. As shown in Fig. 2A, a pixel 20 has a stacked storage capacitor structure, a thin film transistor 24, and a halogen electrode 240 formed thereon. The stacked storage capacitor structure includes a first storage capacitor (Cst) 22 and a second storage capacitor (Cst) 29. A signal line 26 0773-A31798TWF; P2005028; forever 769 8 1323380 and a gate line 28 are interleaved in the vicinity of the above-mentioned thin film transistor 24, and are disposed around the above-mentioned halogen element 20. The second storage capacitor (Cst,) 29 is placed on the first storage capacitor (Cst) 22 described above. The pixel electrode 240 and the stacked storage capacitor structure are in electrical contact with the thin film transistor 24 via a via 246.

As shown in FIG. 2B, the present embodiment provides a substrate 204, a buffer layer 208, a polysilicon layer 212 as a first conductive layer, a gate insulating layer 216, a second conductive layer 220, and a first interlayer dielectric. Layer 224, and a second interlayer dielectric layer 228. The polysilicon layer 212, the second conductive layer 220, and the gate insulating layer 216 interposed between the polysilicon layer 212 and the second conductive layer 220 together constitute the first storage capacitor (Cst) 22. As shown in Fig. 2C, openings 230 and 232 are sequentially formed by photolithography etching. That is, a photoresist pattern (not shown) is formed on the second interlayer dielectric layer 228. A portion of the second interlayer dielectric layer 228 between the regions I is completely etched, and a portion of the first interlayer dielectric layer 224 between the regions I is partially etched, thereby forming a second interlayer dielectric layer 228a and a first interlayer dielectric layer 224a. Wherein, the etching step is performed by using the photoresist pattern as an etching mask, and performing a dry or engraved name. The thickness of the second interlayer dielectric layer 228a and the first interlayer dielectric layer 224a is between 800 and 3000 angstroms, preferably 3000 angstroms. However, the preferred thickness 231 of the first interlayer dielectric layer 224a between the regions I is 1000 angstroms. The first interlayer dielectric layer includes niobium nitride or hafnium oxide. 0773-A31798TWF; P2005028; forever769 9 1323380

As shown in Fig. 2D, a third conductive layer is deposited by conventional chemical vapor deposition (CVD), electroless plating (ECP), or physical vapor deposition (PVD). The third conductive layer includes a first portion 232a and an extended second portion 232b, wherein the extended second portion 232b extends and covers a portion of the second interlayer dielectric layer 228a. The first portion 232a and the extended second portion 232b are defined by regions II and III, respectively. The opening 232 is filled with a metal material such as aluminum or copper. The third conductive layer, the second conductive layer 220, and the first interlayer dielectric layer 224a sandwiched between the third conductive layer and the second conductive layer 220 constitute the second storage capacitor (Cst) 29. As shown in Fig. 2E, a protective layer 236 having a via 246 is formed on the third conductive layer and the second interlayer dielectric layer 228a by a conventional process. A transparent pixel electrode 240 is conformally formed on the protective layer 236 and the via 246. The above transparent halogen electrode 240 includes indium tin oxide or indium zinc oxide. Moreover, a backlight module 248 is placed on the other side of the substrate 204 to complete the thin film transistor array substrate 200 for a low temperature polycrystalline silicon oxide transistor liquid crystal display. The arrow 244 represents the light from the backlight module 248. As shown in FIG. 2F, the stacked storage capacitor structure including the first storage capacitor (Cst) 22 and the second storage capacitor (Cst) 29 obtained by the above method has more than the second storage capacitor (Cst). ,) 29 capacity, thus having a larger capacity than conventional storage capacitors. As shown in FIG. 2G, the above-mentioned thin film transistor array substrate 200 and a color filter substrate 252 are pasted and filled with liquid crystal layer 250 to obtain ·-low 0773-A31798TWF; P2005028; forever769 10 1323380. The thin film transistor liquid crystal display panel 2000. Second embodiment

Fig. 3A is a top view showing a halogen element of a low temperature polycrystalline germanium thin film transistor liquid crystal display according to a second preferred embodiment of the present invention, in which a stacked storage capacitor structure is formed. Fig. 3G is a cross-sectional view taken along line C-C' of the halogen shown in Fig. 3A; and Figs. 3B to 3G are cross-sectional views showing the structure of the stacked storage capacitor. As shown in Fig. 3A, a cell 30 has a stacked storage capacitor structure, a thin film transistor 34, and a halogen electrode 340 formed thereon. The stacked storage capacitor structure includes a first storage capacitor (Cst) 32 and a second storage capacitor (Cst) 39. A signal line 36 and a gate line 38 are interleaved in the vicinity of the above-mentioned thin film transistor 34, and are disposed around the above-mentioned halogen 30. The second storage capacitor (Cst,) 39 is placed on the first storage capacitor (Cst) 32 described above. The above-described halogen electrode 340 and the stacked storage capacitor structure are in electrical contact with the thin film transistor 34 via a via 346. As shown in FIG. 3B, the present embodiment provides a substrate 304, a buffer layer 308, a polysilicon layer 312 as a first conductive layer, a gate insulating layer 316, a second conductive layer 320, and a first interlayer. Electrical layer 324. The polysilicon layer 312, the second conductive layer 320, and the gate insulating layer 316 interposed between the polysilicon layer 312 and the second conductive layer 320 together constitute the first storage capacitor (Cst) 32. As shown in Fig. 3C, opening 326 is formed using a photolithographic etching technique. 0773-A31798TWF; P2005028; forever769 11 1323380 That is, a photoresist pattern (not shown) is formed on the first interlayer dielectric layer 324. Next, the first interlayer dielectric layer 324 is etched, thereby forming a first interlayer dielectric layer 324a. Wherein, in the etching step, the photoresist pattern is used as a button mask, and the dry etching or the engraving is performed. In particular, a portion of the first interlayer dielectric layer 324 located within the region 被 is completely removed such that a portion of the surface 327 of the second conductive layer 320 is exposed.

As shown in FIG. 3D, a second interlayer dielectric layer 328 is conformally deposited on the exposed first surface of the first interlayer dielectric layer 324a and the second conductive layer 320. The method of forming the second interlayer dielectric layer 328 described above includes chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The second interlayer dielectric layer 328 includes tantalum nitride or tantalum oxide having a thickness between 400 and 1200 angstroms, preferably between 600 and 700 angstroms. As shown in FIG. 3E, the second interlayer dielectric layer 328, the first interlayer dielectric layer 324a, and the gate insulating layer 316 are etched through dry etching or wet etching until the polysilicon is exposed. A portion of the surface of layer 312 and an opening 330 is formed; on the other hand, a second interlayer dielectric layer 328a, said first interlayer dielectric layer 324a, and a gate insulating layer 316a are left. As shown in Fig. 3F, a third conductive layer 332 is deposited by conventional chemical vapor deposition (CVD), electroless plating (ECP), or physical vapor deposition (PVD). The third conductive layer includes a first portion 332a and an extended second portion 332b, wherein the extended second portion 332b extends 0773-A31798TWF; P2005028; f〇rever769 12 1323380 extends and covers the second interlayer dielectric One of the layers 328a. The first portion 332a and the extended second portion 332b are defined by regions II and III, respectively. The opening 330 is filled with a metal material such as aluminum or copper. The third conductive layer, the second conductive layer, and the second interlayer dielectric layer 328a sandwiched between the third conductive layer and the second conductive layer constitute the second storage capacitor (Cst) 39.

As shown in Fig. 3G, a protective layer 336 having a via 346 is formed on the third conductive layer and the second interlayer dielectric layer 328a by a conventional process. A transparent halogen electrode 340 is conformally formed on the protective layer 336 and the via 346. The above transparent halogen electrode 340 includes indium tin oxide or indium zinc oxide. Moreover, a backlight module 348 is placed on the other side of the substrate 304 to complete the thin film transistor array substrate 300 for the low temperature polycrystalline silicon oxide transistor liquid crystal display. The arrow 344 represents the light from the backlight module 348. As shown in FIG. 2F, the stacked storage capacitor structure including the first storage capacitor (Cst) 32 and the second storage capacitor (Cst) 39 obtained by the above method is more than the second storage capacitor (Cst). ,) 39 capacity, thus having a larger capacity than conventional storage capacitors. As shown in FIG. 3H, the thin film transistor array substrate 300 and the color filter substrate 352 are pasted and filled with the liquid crystal layer 350 to obtain a low temperature polycrystalline dream film transistor liquid crystal display panel 300. Fig. 4 is a schematic view showing a low temperature polycrystalline thin film transistor liquid crystal display incorporating the low temperature polycrystalline germanium film transistor liquid crystal display panel 2000 shown in Fig. 2G. The low temperature polycrystalline germanium film shown in the above FIG. 2G is 0773-A31798TWF; P2005028; forever769 13 1323380. The crystal liquid crystal display panel 2000 is coupled to a controller 3 to form a low temperature polycrystalline germanium thin film transistor liquid crystal display 4. The controller 3 includes a source and gate driving circuit (not shown) for controlling the low temperature polysilicon thin film transistor liquid crystal display panel 2000 according to the input. In this embodiment, the low temperature polycrystalline germanium thin film transistor liquid crystal display panel 2000 shown in Fig. 4 above may be replaced with a low temperature polycrystalline germanium thin film transistor liquid crystal display panel 3000.

Fig. 5 is a schematic view showing an electronic device coupled to the low temperature polysilicon thin film transistor liquid crystal display 4 shown in Fig. 4. An input device 5 is coupled to the controller 3 of the low temperature polysilicon thin film transistor liquid crystal display 4 shown in Fig. 4 to form an electronic device 6. The input device 5 described above may include a processor, and the processor may input digital data (data) to the controller 3 to generate and maintain an image. The electronic device 6 can be a portable device, such as a PDA, a notebook computer, a tablet computer, and a mobile phone. In addition, the electronic device 6 can also be a non-portable device, such as a desktop computer. . According to the first and second embodiments of the present invention, the extended portion of the third conductive layer is used to construct the second storage capacitor, and the second storage capacitor is placed on the first storage capacitor without additional Occupy the area of the element. Therefore, it is possible to increase the storage capacity without affecting the aperture ratio. In particular, the first portion of the third conductive layer is formed simultaneously with the second portion of the extension, so that the process can be simplified and the cost can be reduced. Although the present invention has been disclosed above in several preferred embodiments, it is also 0773-A31798TWF; P2005028; forever769 14

Claims (1)

f Date: 96.12.21 I ^ No. 94142780 Patent Application Scope Amendment 10, Patent Application Park: U..._ 1. A laminate stored in Ray-A-A transistor crystal liquid crystal display, packaged for low-temperature polysilicon film a substrate; an electrical layer, a buffer, and a capacitor: the capacitor 'including a first conductive layer, a second conductive second edge #, and the second conductive layer between the first conductive layer and the second conductive layer a conductive layer is disposed on the first conductive layer, and /, a center i storage capacitor is placed on the substrate; a third three conductive sound, 4 points; θ includes a first portion and an extended second portion - the second storage a capacitor comprising: the extended first layer of the electrical layer, the second layer of the third conductive layer, and a second insulating layer between the second conductive layer and the first portion of the first conductive portion a second layer of the extension of the V-electrode layer, wherein 嗲筮 抑 抑 々 々 々 々 电 电 电 电 电 电 电 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 电 电 电 电 电The second insulating layer and the third conductive layer edge layer have a concave center, wherein the third An insulating layer and a second insulating layer, wherein a protective layer is formed with a via; and an electrode is disposed on the protective layer; and the sound electrode is passed through the via and the third conductive layer The portion of the third insulating layer is in direct contact with the fourth portion of the second insulating layer 0773-A31798TWF2 (2〇〇7l〇22) 19 1323380 The thickness of the fourth portion of the second insulating layer is thicker than other portions of the same layer; wherein the thickness of the fourth portion of the second insulating layer is between 800 and 1200 angstroms. The stacked storage capacitor structure of claim 1, wherein the substrate comprises a substrate and a buffer layer thereon. 3. The stacked storage capacitor structure of claim 2, wherein the The first portion of the three conductive layers is in electrical contact with the first conductive layer through the third insulating layer, the second insulating layer, and the first insulating layer. 4. As described in claim 3 Stacked storage capacitor structure, the second insulating layer 5. A stacked storage capacitor structure for a low temperature polycrystalline germanium thin film transistor liquid crystal display, comprising: a substrate; a first storage capacitor comprising a first conductive layer and a second conductive layer And a 'first insulating layer between the first conductive layer and the second conductive layer, wherein the second conductive layer is disposed on the first conductive layer, and wherein the first storage capacitor is disposed a third conductive layer comprising a first portion and an extended second portion; a second storage capacitor comprising a second conductive layer, the extended second portion of the third conductive layer, and a second a second insulating layer between the second conductive layer and the extended second portion of the third conductive layer, 0773-A31798TWF2 (20071022) 20 extending, the second portion of the f is placed on the second conductive and forming an electrical The contact r storage capacitor is disposed in the first storage capacitor, and is disposed between the second portion of the extension of the second and second portions of the extension and the second conductive layer::: = have - inside The third insulating layer is directly covered, wherein:; = the concave portion is between 400 and 1000 angstroms; 'the thickness of the second insulating layer is a protective layer, wherein the cap-all I is formed with a &quot; a window; and a ruthenium electrode disposed on the protective layer; and wherein the quinone electrode is electrically connected through the first portion of the via. The layer "the third conductive structure layer ^ such as U (four) around the fifth item f substrate and the upper = 7 · as claimed in the sixth item, wherein the third conductive layer of the order μ, and the layer storage electricity benefits a second insulating layer, and a first portion; the portion is electrically connected through the third insulating layer; &quot; shouting layer and the stacked storage capacitor junction of the first conductive layer structure, 7 The insulating layer comprises yttrium oxide. 9. A low-temperature polycrystalline germanium thin film transistor liquid crystal display panel comprising: the stacked storage capacitor junction color filter 'light sheet substrate' as described in claim 1 with respect to the transistor array base 0773 -A31798TWF2(20071022) 21 The light substrate is disposed on the thin film transistor array substrate and the color germanium, germanium, and polycrystalline germanium thin film transistor liquid crystal display, comprising: the low temperature polycrystalline second thin film electricity according to the liquid crystal display The crystal display panel is used to control the panel to maintain the image according to the rounding of the low temperature polycrystalline silicon thin film transistor liquid crystal display. 11. An electronic device comprising: 'If the patent application scope is $10 The low temperature A polycrystalline liquid crystal display; and a 曰/special film electric wheel into the farmer' is connected to the low temperature polycrystal 0773-A31798TWF2 (20071022) 22