TWI318504B - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- TWI318504B TWI318504B TW094137483A TW94137483A TWI318504B TW I318504 B TWI318504 B TW I318504B TW 094137483 A TW094137483 A TW 094137483A TW 94137483 A TW94137483 A TW 94137483A TW I318504 B TWI318504 B TW I318504B
- Authority
- TW
- Taiwan
- Prior art keywords
- delay circuit
- delay
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
- H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Networks Using Active Elements (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005203054A JP4129010B2 (ja) | 2005-07-12 | 2005-07-12 | 遅延回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200703914A TW200703914A (en) | 2007-01-16 |
| TWI318504B true TWI318504B (en) | 2009-12-11 |
Family
ID=35295425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW094137483A TWI318504B (en) | 2005-07-12 | 2005-10-26 | Delay circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7750710B2 (zh) |
| EP (1) | EP1744456B1 (zh) |
| JP (1) | JP4129010B2 (zh) |
| KR (1) | KR100655814B1 (zh) |
| TW (1) | TWI318504B (zh) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7514966B2 (en) * | 2005-06-02 | 2009-04-07 | Via Technologies, Inc. | Fast, low offset ground sensing comparator |
| JP5440831B2 (ja) * | 2007-11-29 | 2014-03-12 | Ｎｌｔテクノロジー株式会社 | 電圧制御発振器並びにそれを備えた表示装置及びシステム |
| JP2009290857A (ja) * | 2008-01-11 | 2009-12-10 | Toshiba Corp | 半導体装置 |
| JP4879240B2 (ja) * | 2008-09-16 | 2012-02-22 | 株式会社リコー | 発振回路、ｄｃ−ｄｃコンバータ及び半導体装置 |
| US8866556B2 (en) * | 2009-02-27 | 2014-10-21 | Analog Bits, Inc. | Phase shift phase locked loop |
| US10466763B2 (en) * | 2013-12-02 | 2019-11-05 | Nvidia Corporation | Dynamic voltage-frequency scaling to limit power transients |
| US10756881B2 (en) | 2016-08-01 | 2020-08-25 | Nxp B.V. | Method and system for operating a communications device that communicates via inductive coupling |
| US10567092B2 (en) | 2017-09-01 | 2020-02-18 | Nxp B.V. | System to calibrate phase using system information |
| US11405042B2 (en) * | 2019-12-31 | 2022-08-02 | Texas Instruments Incorporated | Transceiver carrier frequency tuning |
| CN116073799A (zh) * | 2021-11-04 | 2023-05-05 | 上海复旦微电子集团股份有限公司 | 时钟产生电路 |
| CN114696787B (zh) * | 2022-03-29 | 2023-06-16 | 拓尔微电子股份有限公司 | 一种具有电源同步功能的延迟电路 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0394512A (ja) | 1989-09-07 | 1991-04-19 | Fujitsu Ltd | 半導体遅延回路 |
| US5606276A (en) * | 1994-10-05 | 1997-02-25 | Altera Corporation | Method and apparatus for creating a large delay in a pulse in a layout efficient manner |
| US5982213A (en) * | 1997-11-14 | 1999-11-09 | Texas Instruments Incorporated | Digital phase lock loop |
| US6493305B1 (en) * | 1998-03-26 | 2002-12-10 | Sanyo Electric Co., Ltd. | Pulse width control circuit |
| JP3547983B2 (ja) | 1998-03-26 | 2004-07-28 | 三洋電機株式会社 | パルス幅制御回路及びディスク記録制御回路 |
| JP3745123B2 (ja) * | 1998-08-24 | 2006-02-15 | 三菱電機株式会社 | デューティ比補正回路及びクロック生成回路 |
| JP2000163999A (ja) | 1998-11-20 | 2000-06-16 | Fujitsu Ltd | セルフタイミングコントロール回路 |
| DE10082011T1 (de) * | 1999-07-07 | 2001-08-02 | Advantest Corp | Variable Verzögerungsschaltung |
| JP3921321B2 (ja) | 2000-01-27 | 2007-05-30 | 株式会社ルネサステクノロジ | 記録メディア読み出しシステム |
| JP3676213B2 (ja) * | 2000-09-05 | 2005-07-27 | シャープ株式会社 | 遅延回路及びそれを用いたリング発振器 |
| JP3605033B2 (ja) | 2000-11-21 | 2004-12-22 | Ｎｅｃエレクトロニクス株式会社 | 固定長遅延生成回路 |
| US6587811B2 (en) * | 2000-11-28 | 2003-07-01 | Scientific Technologies Incorporated | System and method for delay line testing |
| JP4871462B2 (ja) * | 2001-09-19 | 2012-02-08 | エルピーダメモリ株式会社 | 補間回路とｄｌｌ回路及び半導体集積回路 |
| JP2005269147A (ja) * | 2004-03-18 | 2005-09-29 | Sanyo Electric Co Ltd | 遅延回路 |
-
2005
- 2005-07-12 JP JP2005203054A patent/JP4129010B2/ja not_active Expired - Fee Related
- 2005-10-26 TW TW094137483A patent/TWI318504B/zh not_active IP Right Cessation
- 2005-10-28 EP EP05023650.4A patent/EP1744456B1/en not_active Expired - Lifetime
- 2005-11-03 US US11/265,104 patent/US7750710B2/en not_active Expired - Lifetime
- 2005-11-21 KR KR1020050111289A patent/KR100655814B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US7750710B2 (en) | 2010-07-06 |
| TW200703914A (en) | 2007-01-16 |
| EP1744456A2 (en) | 2007-01-17 |
| JP2007027849A (ja) | 2007-02-01 |
| US20070013427A1 (en) | 2007-01-18 |
| JP4129010B2 (ja) | 2008-07-30 |
| EP1744456B1 (en) | 2013-05-22 |
| KR100655814B1 (ko) | 2006-12-13 |
| EP1744456A3 (en) | 2009-01-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |