1314733 P950166 22093twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的操作方法，且特別 疋有關於一種非揮發記憶體(n〇n_V〇latile mem〇ry)的重置 方法(reset method) ’其是利用双邊偏壓Q〇uble_^delias， DSB)-頻帶穿隧熱電洞但an(H〇_細d IunneUng职H〇le， BTBTHH)效應來進行的。 【先前技術】 士快閃記憶體之類的可電除可程式化非揮發記憶體在使 用時’-般包括將電子注入電荷儲存層的操作及除去電荷 儲存層中的電子的操作，後者之操作例如是將電子驅趕出 電荷儲存層，或是將電敝人電·存射與電子結合。 -此種，揮發s己憶體之抹除_程式化操作的常見模式有 二。其-是絲切有記憶胞的電荷儲存射的電子以進 2除，再將電子注人部分記⑽的電荷儲存層中以進行 化H是先將電子注人所有記憶胞的電荷儲存層 以’再除去部分記憶胞之電荷儲存層中的電子 胞進二式中，由於抹除是對所有的記憶 m 2 ί 抹除祕記憶胞會有過度抹_ 記仲，條麵射轉射的電子轉除的非揮發 子’主入法i%彳·^除者㈣’其在彡次雜/料化操作後 電荷儲存“會之後部分記憶胞的 電；、、:t λ、4· 1啕+正電何，而導致漏電的問題 1314733 P950166 22093twf.doc/n 別靠近源極150及汲極i6〇的兩個資料儲存區。 另外，以浮㈣為電荷儲存狀鱗魏憶胞的—例 是將110、120、130三層換成穿隧氧化層、複晶石夕浮置閑 及閘間介電層而得之記憶胞；以奈米晶粒層為電荷儲存層 之非揮發記憶胞的一例，則是將氮化矽層12〇換成内含許 多奈米矽晶粒的氧化矽層而得者。當電荷儲存層為奈米晶 粒層時，每一記憶胞亦可具有分別靠近源極區與汲極區的 二資料儲存區。 為同時說明高Vt儲存態之資料儲存區及過度抹除之 資料儲存區其各自在重置操作時發生的現象，圖丨例示之 記憶胞10具有分別靠近源極150及汲極160的兩個資料儲 存區，其中位在左邊者在重置前已被過度抹除，使該處之 氮化矽層120帶正電荷，而位在右邊者則在高％儲存態。 請參照圖1，此實施例之重置方法在控制閘14〇及基 底1〇〇上施加ον，並在源極區150及汲極區160上同時施 加高於0V的電壓Vs、Vd(=Vs)，此即所謂的「双邊偏壓」。 此VS、Vd之值足以產生頻帶穿隧熱電洞，通常為5V〜7V， 致使電子/電洞對產生於基底100中，其中電子會受左資料 儲存區之氮化矽層120中的正電荷吸引而進入其中，使左 資料儲存區的啟始電壓逐漸升高；電洞則會受右資料儲存 區之氮化矽層120中的負電荷吸引而進入其中，使右資料 儲存區的啟始電壓逐漸降低。經過一段時間之後，各資料 儲存區之氮化矽層120中的電荷量即可接近一平衡值，使 各資料儲存區具有相近的啟始電壓。 1314733 P950166 22093twf.doc/n △ ^上述原理可知，對兩資料儲存區的狀態並非過度抹 ，態匕向Vt儲存態的其他記憶胞(即過度抹除態/過度抹除 態、高Vt儲存態/高vt儲存態、正常抹除態/正常抹除態、 過度抹除態/正常抹除態及高vt儲存態/正常抹除態的記憶 胞）而言，其所有的資料儲存區皆可在上述重置操作進行一 段時間之後具有相近的啟始電壓。換句話說，上述各電壓 施加之時間須足以使各記憶胞所具有驗始電壓收敛至一 可容許範圍内。 此外，由上述原理可知，在一記憶胞僅一資料儲存區 的非揮發記憶體中，過度抹除態、高vt儲存態及正常抹除 態的記憶胞皆可以上述重置方法而具有相近的啟始電壓。 上述重置方法的一個實例請見圖2，其中非揮發記憶 體具有一虛擬接地陣列結構。在此實例中，所有與控制閘 耦接的字元線(！〇rd Line，WL)及基底皆施加0V，且所有 與源/没極區耦接的位元線幽^^，叫皆施加高於〇乂且 足以使頻帶穿隧熱電洞產生的Vl，例如是5V〜7v。此時各 記憶胞中所發生的現象如前所述。 接著請參照圖3、4A、4B，其繪示本發明第二實施例 之非揮發記憶體重置方法，其中圖3繪示閘電壓Vg隨時 間的變化，圖4A/B則繪示一例示之記憶胞的各部分上所 施加的電壓及閘電壓為正值/負值時所引發的現象。圖4A/ 4B所例示之記憶胞10與圖1所示者相同，亦具有分別靠 近源極150及没極160的兩個資料儲存區，其中位在左邊 者在重置前已被過度抹除，位在右邊者則在高％儲存態。 1314733 P950166 22093twf.doc/n 如圖3、4A、4B所示，此實施例是在基底loo上施加 0V ’在源極區150與汲極區160上施加高於0V的VS、Vd (=Vs)，並在各控制閘140上交替施加高於〇v的+乂2及低 於0V的-V2，其中V2例如是5V〜7V，且每一次施加+V2 的時間等於每一次施加-V2的時間。Vs、Vd之大小足以產1314733 P950166 22093twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a method of operating a semiconductor device, and particularly to a non-volatile memory (n〇n_V〇latile mem〇ry) The reset method (which is based on the bilateral bias voltage Q〇uble_^delias, DSB)-band tunneling thermoelectric holes but an (H〇_fine d IunneUng job H〇le, BTBTHH) effect of. [Prior Art] An electrically erasable and non-volatile memory such as a flash memory, when used, generally includes an operation of injecting electrons into a charge storage layer and an operation of removing electrons in the charge storage layer, the latter The operation is, for example, driving the electrons out of the charge storage layer, or combining the electrons, the emitters, and the electrons. - This type of volatilization s replied eraser _ stylized operation has two common modes. It is to cut off the electrons of the memory cell to store the electrons, and then divide the electrons into the charge storage layer of (10) to carry out the H. First, the electrons are injected into the charge storage layer of all the memory cells. 'Removing the electron cell in the charge storage layer of some memory cells, because the erase is for all memory m 2 ί erase the secret memory cells will have excessive wiping _ 仲 仲, stripe-emitting electrons The non-volatile sub-injection method of the non-volatile sub-injection method i% 彳 · ^ (4) 'the charge storage after the 杂 杂 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / + positive electricity, and the problem of leakage 1314733 P950166 22093twf.doc/n Close to the two data storage areas of the source 150 and the bungee i6〇. In addition, the floating (four) is the charge storage scale of the Weiyi cell. It is a memory cell obtained by replacing 110, 120, and 130 layers with a tunneling oxide layer, a double crystallized layer, and a dielectric layer of a gate; a non-volatile memory cell having a nanocrystalline layer as a charge storage layer. An example is to replace the tantalum nitride layer 12〇 with a layer of tantalum oxide containing many nano-nano grains. When the charge is stored When the layer is a nano-grain layer, each memory cell may also have two data storage areas respectively adjacent to the source region and the drain region. The data storage region and the over-erased data storage region for simultaneously explaining the high Vt storage state. The phenomenon that each of them occurs during the reset operation, the memory cell 10 illustrated in the figure has two data storage areas respectively close to the source 150 and the drain 160, wherein the left side is over-erased before resetting. The tantalum nitride layer 120 at this point is positively charged, while the one on the right side is in a high % storage state. Referring to FIG. 1, the reset method of this embodiment applies ον on the control gate 14〇 and the substrate 1〇〇. And a voltage Vs, Vd (=Vs) higher than 0V is simultaneously applied to the source region 150 and the drain region 160, which is called "bilateral bias". The values of VS and Vd are sufficient to generate a band tunneling thermowell, typically 5V~7V, resulting in an electron/hole pair being generated in the substrate 100, wherein the electrons are subject to a positive charge in the tantalum nitride layer 120 of the left data storage region. Attracting and entering, the starting voltage of the left data storage area is gradually increased; the hole is attracted by the negative charge in the tantalum nitride layer 120 of the right data storage area, and the right data storage area is started. The voltage gradually decreases. After a period of time, the amount of charge in the tantalum nitride layer 120 of each data storage area can be close to an equilibrium value, so that each data storage area has a similar starting voltage. 1314733 P950166 22093twf.doc/n △ ^ The above principle shows that the state of the two data storage areas is not excessively wiped, and other memory cells in the Vt storage state (ie, over-erased/over-wiped state, high-Vt storage state) / high vt storage state, normal erase state / normal erase state, over erased state / normal erase state and high vt storage state / normal erased memory cell), all data storage areas are available There is a similar starting voltage after the reset operation has been performed for a while. In other words, each of the above voltages must be applied for a time sufficient for each memory cell to have a threshold voltage that converges to an allowable range. In addition, according to the above principle, in a non-volatile memory in which only one data storage area of a memory cell is used, the memory cells of the over-erased state, the high-vt storage state, and the normal erased state may have similar reset methods. Start voltage. An example of the above reset method is shown in Figure 2, in which the non-volatile memory has a virtual ground array structure. In this example, all of the word lines (!〇rd Line, WL) and the substrate coupled to the control gate are applied with 0V, and all the bit lines coupled to the source/no-pole regions are applied. Vl higher than 〇乂 and sufficient to cause the frequency band to tunnel through the thermoelectric holes, for example, 5V to 7v. At this time, the phenomenon occurring in each memory cell is as described above. Referring to FIG. 3, FIG. 4A and FIG. 4B, FIG. 3 illustrates a non-volatile memory reset method according to a second embodiment of the present invention, wherein FIG. 3 illustrates a change of the gate voltage Vg with time, and FIG. 4A/B illustrates an example. A phenomenon caused when the voltage applied to each part of the memory cell and the gate voltage are positive/negative. The memory cell 10 illustrated in FIG. 4A/4B is the same as that shown in FIG. 1, and has two data storage areas respectively close to the source 150 and the dipole 160, wherein the left side is over-erased before resetting. The ones on the right are in the high % storage state. 1314733 P950166 22093twf.doc/n As shown in Figures 3, 4A, 4B, this embodiment applies 0V ' on the substrate loo' to apply VS, Vd (=Vs) above the 0V on the source region 150 and the drain region 160. And alternately apply +乂2 above 〇v and -V2 below 0V on each control gate 140, where V2 is, for example, 5V~7V, and the time of each application of +V2 is equal to each application of -V2 time. Vs, Vd are large enough to produce
生頻帶穿隧熱電洞，通常為5V〜7V ’致使電子/電洞對產 生於基底100中’其中電子會在每次於各控制閘上施 加+V2時注入各資料儲存區的氮化矽層12〇中，如圖4入所 示，且電洞會在每次於各控制閘140上施加_v2時注入各 資料儲存區的氮化石夕層120中，如圖4B所示。 由於左資料儲存區的氮化石夕層12〇具正電荷，故在其 電荷量趨=平衡狀態之前，每次施加+v2時注入的電子^ 會多於其前-次或後-次施加_V2收人的電洞數，致使 左資料儲存區的啟始電壓逐漸升高。另一方面，由於右資 料儲存區的電荷儲存層12G具負電荷，故在其電荷趨近平 衡狀態之前，每次施加·V2時〜的電酿會多於其前一 施加+V2時注入的電子數，致使右資料儲存區 =始ί壓逐漸降低。因此，經過—段時間後，各資料儲 夕層120即具有相近的電荷量，使各資料儲存 區具有相近的啟始電壓。 除離/古甘對兩貝枓儲存區的狀態並非過朗 除以同Vt儲存態的其他記憶胞 區皆可在上述重置方法進行一段;的貝刪 換句雜，上#電親加之_須足以使各記憶胞 11 1314733 P950166 22093twf.doc/n 所具有的啟始電壓收斂至一可容許範圍内。同樣地，在一 記憶胞一資料儲存區的非揮發記憶體中，所有記憶胞亦皆 可以上述重置方法而具有相近的啟始電壓。 凊再參照圖2’其亦蜂示本發明第二實施例之重置方 法用於虛擬接地陣列結構之非揮發記憶體的一個例子。在 此例中，基底施加ον ’所有與源/汲極區耦接的位元線(BL) 皆施加高於0V且足以使頻帶穿隧熱電洞產生的Vi，例如 是5V〜7V，且所有與閘極耦接的字元線(WL)皆同步交替施 加高於〇 v的+V2及低於〇 v的_ %，其中V2例如是5 v〜7 v， 其中母一次施加+V2的時間等於每一次施加的時間。此 時各記憶胞中所發生的現象如前所述。 接著請參照圖5，其繪示本發明第一實施例之非揮發 記憶體重置方法的一實驗例中，原為高啟始電壓之左/右位 元及原為低啟始電壓之左/右位元的啟始電壓隨時間的變 此實驗例中的左、右資料儲存區各自只儲存一位元的 資料，故以左、右位元稱之。基底及控制閘上所加電壓為 0V，且各源/汲極區上所加電壓為7V。 、如圖5所示，隨著重置操作的時間增加，重置前已被 過f抹除的低Vt儲存態的左、右位元及重置前為高％儲 存態的左、右位元的啟始電壓漸漸朝一特定電壓值收斂， 其稱為重置啟始電壓。雖然重置操作時間要很長才可以使 各位元的啟始電壓皆等於該重置啟始電壓，但在實用上， 各電壓施加之時間只要足以使各記憶胞所具有的啟始電壓 收斂至一可容許範圍内即可。 12 1314733 . P950166 22093twf.doc/n 圖6繪不本發明第二實施例之非揮發記憶體重置方法 的-實驗射，原為高啟始電壓之左/右位元及原為低啟始 電壓之右位元的啟始電壓隨時間的變化。此實驗例中的 左、右資料儲存區都只儲存-位元’故以左、右位元稱之。 基底上所加電麗為0V，各源/沒極區上所加電屋為5v，且 各控制閘上交替施加+7V及_7V，其中每次施加+7V或… 之時間長度為1毫秒。 、如圖6所示，隨著重置操作的時間增加，重置前已被 過度抹除的低Vt儲存態的左、右位元及重置前為高^儲 存態的左、右位元的啟始賴是則、幅振躺方式漸漸收 斂^-個範_。雖然此第二實施例之重置方法無法如第 、貝轭例之重置方法般使各位元的啟始電壓最終收斂至前 述重置啟始電壓’但卻有啟始電缝紐快的優點，而得 以節省重置操作的時間。 由於使用本發明之重置方法所能得到的啟始電壓分佈 範圍窄於使用習知重置方法所能得到者，所以後續在使用 該非揮發記Μ時，較不容緑生資料讀寫錯誤的問題。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限=本發明，任何熟習此祕者，在不麟本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖_ 1繪示本發明第一實施例之非揮發記憶體重置方法 中’例示之記憶胞的各部分上施加的電壓及其弓丨發的現象。 13 1314733 P950166 22093twf.doc/n ψ 圖2繪示本發明第一及第二實施例之非揮發記憶體重 置方法，其中非揮發記憶體是以電路簡圖來表示。 圖3繪示本發明第二實施例之非揮發記憶體重置方法 中，閘電壓Vg隨時間的變化。 圖4A/4B繪示本發明第二實施例之非揮發記憶體重置 方法中，一例示之記憶胞的各部分上所施加的電壓及閘電 壓為正值/負值時所引發的現象。 圖5繪示本發明第一實施例之非揮發記憶體重置方法 的一實驗例中，原為高啟始電壓之左/右位元及原為低啟始 電壓之左/右位元的啟始電壓隨時間的變化。 圖6繪示本發明第二實施例之非揮發記憶體重置方法 的一實驗例中，原為高啟始電壓之左/右位元及原為低啟始 電壓之左/右位元的啟始電壓隨時間的變化。 【主要元件符號說明】 10 :記憶胞 100 :基底 110、120、130 :底氧化層、氮化石夕層、頂氧化層 140 :控制閘 150、160 :源極區、没極區 BL、WL :位元線、字元線 V!、V2 :電壓值的代號 Vb :基底電壓The raw-band tunneling thermoelectric hole, usually 5V~7V 'causes an electron/hole pair to be generated in the substrate 100, where the electrons are injected into the nitride layer of each data storage area every time +V2 is applied to each control gate 12〇, as shown in FIG. 4, and the holes are injected into the nitride layer 120 of each data storage area each time _v2 is applied to each control gate 140, as shown in FIG. 4B. Since the nitride layer 12 of the left data storage area has a positive charge, before the charge amount becomes equilibrium, the electron injected by each time +v2 is applied will be more than its pre- or post-time application. The number of holes in the V2 collection causes the starting voltage of the left data storage area to gradually increase. On the other hand, since the charge storage layer 12G of the right data storage area has a negative charge, before the charge approaches the equilibrium state, the electric brewing of each time the application of V2 is more than the injection of the previous application of +V2. The number of electrons causes the right data storage area = the initial pressure to gradually decrease. Therefore, after a period of time, each data storage layer 120 has a similar amount of charge, so that each data storage area has a similar starting voltage. Detachment/Gugan's state of the two Beggar storage areas is not excessively divided by other memory cells of the same Vt storage state, which can be performed in the above reset method; the deletion of the sentence, the #电亲加_ It must be sufficient for the starting voltage of each memory cell 11 1314733 P950166 22093twf.doc/n to converge to an allowable range. Similarly, in a non-volatile memory of a memory cell-data storage area, all memory cells can also have similar starting voltages by the above reset method. Referring again to Figure 2', there is also shown an example of a non-volatile memory for a virtual ground array structure in the reset method of the second embodiment of the present invention. In this example, the substrate is applied ον 'all bit lines (BL) coupled to the source/drain regions are applied with a voltage higher than 0V and sufficient for the band to tunnel through the thermoelectric holes, for example 5V~7V, and all The word lines (WL) coupled to the gates are alternately applied with +V2 higher than 〇v and _% lower than 〇v, where V2 is, for example, 5 v~7 v, where the mother applies +V2 at a time Equal to the time of each application. At this time, the phenomenon occurring in each memory cell is as described above. Referring to FIG. 5, an experimental example of the non-volatile memory reset method according to the first embodiment of the present invention is shown as the left/right bit of the high start voltage and the left of the low start voltage. The start voltage of the right bit changes with time. The left and right data storage areas in the experimental example each store only one bit of data, so they are called left and right bits. The applied voltage on the substrate and the control gate is 0V, and the voltage applied to each source/drain region is 7V. As shown in FIG. 5, as the time of the reset operation increases, the left and right bits of the low Vt storage state that have been erased by f before the reset and the left and right bits of the high % storage state before the reset are reset. The starting voltage of the element gradually converges toward a specific voltage value, which is called a reset starting voltage. Although the reset operation time is long, the start voltage of each bit is equal to the reset start voltage, but practically, each voltage is applied for a time sufficient for the start voltage of each memory cell to converge to One can be within the allowable range. 12 1314733 . P950166 22093twf.doc/n FIG. 6 depicts a non-volatile memory reset method of the second embodiment of the present invention - the experimental shot, which is the left/right bit of the high start voltage and the original low start voltage. The starting voltage of the right bit changes with time. In the experimental example, the left and right data storage areas only store the -bits, so they are referred to as left and right bits. The power applied to the substrate is 0V, and the power supply house on each source/no-pole region is 5v, and +7V and _7V are alternately applied to each control gate, and the time length of each application of +7V or ... is 1 millisecond. . As shown in FIG. 6, as the time of the reset operation increases, the left and right bits of the low Vt storage state that have been over erased before resetting and the left and right bits of the high storage state before resetting are reset. The beginning of the reliance is that the swaying mode gradually converges ^- a __. Although the reset method of the second embodiment cannot make the starting voltage of each element finally converge to the aforementioned reset starting voltage as in the reset method of the first and the yoke example, the advantage of starting the electric seam is fast. And save time in reset operations. Since the starting voltage distribution range that can be obtained by using the reset method of the present invention is narrower than that obtained by using the conventional reset method, the subsequent use of the non-volatile memory is less likely to cause errors in reading and writing of green data. . Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any person skilled in the art may make some modifications and refinements within the scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a voltage applied to each portion of an exemplary memory cell and a phenomenon of bowing in the nonvolatile memory reset method according to the first embodiment of the present invention. 13 1314733 P950166 22093twf.doc/n FIG. 2 illustrates a non-volatile memory weight setting method according to the first and second embodiments of the present invention, wherein the non-volatile memory is represented by a circuit diagram. Fig. 3 is a diagram showing changes in the gate voltage Vg with time in the nonvolatile memory reset method of the second embodiment of the present invention. 4A/4B are diagrams showing a phenomenon in which the voltage applied to each portion of the memory cell and the gate voltage are positive/negative in the nonvolatile memory reset method according to the second embodiment of the present invention. FIG. 5 is a diagram showing an example of a method for resetting a non-volatile memory according to a first embodiment of the present invention. The left/right bit of the high start voltage and the left/right bit of the low start voltage are The starting voltage changes with time. 6 is a diagram showing an example of a non-volatile memory reset method according to a second embodiment of the present invention, in which the left/right bit of the high start voltage and the left/right bit of the low start voltage are turned on. The starting voltage changes with time. [Description of main component symbols] 10: Memory cell 100: Substrate 110, 120, 130: bottom oxide layer, nitride layer, top oxide layer 140: control gate 150, 160: source region, gate region BL, WL: Bit line, word line V!, V2: code value of voltage value Vb: base voltage
Vd、Vs :汲極電壓、源極電壓 Vg :閘電壓Vd, Vs: drain voltage, source voltage Vg: gate voltage