TWI313063B - - Google Patents

Description

1313063 No. 92107566_年月日日__ V. INSTRUCTION DESCRIPTION (1) Technical Field of the Invention The present invention relates to reducing the contact resistance of a thin film transistor gate and indium tin oxide, and the improvement of gate wiring. The method of impedance. i [Prior Art] The trend of conventional cathode ray tube displays is to increase the size, so that users can have higher and better visual effects. The development trend of liquid crystal displays is no exception, and various LCD monitor manufacturers are not trying their best to develop in large size. Due to the thin and light-saving characteristics of the liquid crystal display, the liquid crystal display has an inherent advantage over the cathode ray tube screen on a large-sized screen.

Especially in the cathode ray tube screen of more than 38 吋, it is too heavy and difficult to manufacture. Therefore, in the case of more than 38 吋 screen, it is necessary to use a non-cathode ray tube screen, and the liquid crystal screen is naturally a large-size screen. One of the choices. The largest LCD screen (LCD TV) has been released so far, with a size of 52 inches. However, a large-sized (20 吋 or higher) high-resolution liquid crystal firefly requires an R C delay time of shorter i. Traditionally, the metal material of the gate of a thin film transistor has

I ||g (A1), chromium (Cr), tungsten (W), tantalum (Ta), titanium (Τι), |锢 (Mo), and the like. Since aluminum has high electrical conductivity (ie, the resistance value R is low:), it is generally a single-layered imprint, or a double-layered metal composed of an inscription or alloy and other metals. The gate. In the case of the gate of a single-layer I aluminum, it is connected when it is removed from the vacuum deposition chamber to the next process.

Page 6 1313063 Case No. 92107566 Rev. 曰 V. Description of invention (2) Touching the atmosphere, causing oxides on the surface. This layer of oxide cannot be removed by the etchant, and the contact resistance is very high when it is connected to other metals (especially through the connection of indium tin oxide to drive the gate). Or, as shown in the first figure, the structure of the double-layer metal composed of the first metal layer 20 and the second metal layer 30 (for example, Ming or Ming alloy and other metals), due to different metals, There are different etch rate problems, and the i-house effect will occur after etching. That is, as shown in the first figure, the second metal layer 30 and the first metal layer 20 are on both sides of the contact surface, and the second metal layer 30 is slightly smaller than the first metal layer 20. Some of the etching residue tends to remain here, and it is difficult to clean and remove, which affects the subsequent process and the contact resistance of the gate and the electrical performance of the wiring impedance. If a gate of a thin film transistor is formed by a single layer of chromium or the like, the contact resistance with indium tin oxide is small, but the wiring resistance of other metals such as chromium is higher than that of aluminum, and the lower RC delay time cannot be achieved. .

I Therefore, how to reduce the contact resistance of the thin film transistor gate and other metals and the wiring resistance of the gate itself is a problem that must be solved when developing a large-size liquid crystal panel. SUMMARY OF THE INVENTION In view of the above-described background of the invention, in the prior art, a single layer of aluminum, aluminum, and other metals or alloys of a noble metal and other metals is used as a gate of a thin film transistor. There will be oxide or etch residue: the contact resistance and wiring resistance of the gate will be increased, or the thin film transistor gate formed by the metal such as chrome will be compared with the contact resistance of indium tin oxide. Aluminum is small, but the wiring resistance of other metals such as chrome is higher than aluminum, and there is no

Page 7 1313063 Case No. 92107566 Revised on the day of the month .........~~ ~~~~~- .......~~~ ' V. Invention description (3) Low RC delay time. The main object of the present invention is to provide a method for reducing the contact resistance of a thin film transistor, which utilizes a titanium metallization layer and a chromium layer i or a double layer metal structure of a bismuth aluminum layer and a chrome telluride layer to be treated by plasma. The method removes the etching residue or oxidation product of the surface, so that the formed film is electrically: the crystal gate structure has a low contact resistance with indium tin oxide. Another object of the present invention is to provide a method for reducing the contact resistance of a thin film transistor, wherein the etching rate of the material of the two-layer structure is similar, which makes it difficult for the e-etching to generate an eaves effect and affect the subsequent process or the electric power of the gate. Sex.

A further object of the present invention is to provide a method for reducing the contact resistance of a thin film transistor, which can effectively improve the RC delay time to improve the i reaction time of the liquid crystal panel. Another object of the present invention is to provide a method of reducing the contact resistance of a thin film transistor to achieve a shorter RC delay time for a large size panel.

I I In accordance with the above objects, the present invention provides a method of reducing the contact resistance of a thin film transistor. In a preferred embodiment of the invention, a method of reducing the contact resistance of a thin film transistor is disclosed, comprising forming a metal conductor: an electrical film on a substrate and performing a plasma surface treatment. The metal conductor: the electric film comprises a layer of A 1 Nd, formed on the substrate and a layer of Cr (Cr S i 1 ici de), formed in the layer : on the top layer to provide lower wiring resistance; and the plasma surface treatment system to treat the barrier layer and the chrome layer as barrier layer (a barrier 1 ayer)

Page 8 nn〇6i Case No. 92107566_年月日日____________________; V. Description of the invention (4) The surface of the titanium aluminum layer and the chromium layer to reduce the contact resistance of the metal conductive film. Therefore, compared to the conventional technique, a single layer of aluminum, Ming and other metals or aluminum alloys and other metals are used as a double layer metal, or as a gate of a thin film transistor, or other metal such as chromium. To form the gate of the thin film transistor, there is a high contact resistance or wiring impedance. The invention provides a method for reducing the contact resistance of a thin film transistor, in addition to avoiding the prior art

^ I I have problems, and at the same time achieve the advantages of the above object. j ! [Implementation] _

The embodiments of the present invention are described in detail below, but the present invention is only a preferred embodiment, and P is not intended to limit the present invention, which is subject to the scope of the following patents. i

II | i Further, in order to provide a clearer description and to more easily understand the present invention, the i parts in the illustration are not drawn according to their relative sizes, and some dimensions have been exaggerated compared to other related rule degrees; irrelevant The details are not completely drawn, and the simplicity of the β is shown. i! 1 ! The thin film transistor gate structure of a preferred embodiment of the present invention is as shown in the second figure. A first metal layer 20 is formed on a glass substrate 10, and a second metal layer 30 is formed on the first metal layer 20. Next, the first metal layer 20 and the second metal layer 30 are used as barrier layers (b a r r i e r 1 a y e r) to remove some oxides or residues on the surface, preferably by surface treatment of helium plasma. Generally, the first metal layer 20 is made of Shao or Ilu alloy, and the preferred material is aluminum telluride (A 1 Nd) to provide lower wiring resistance, but due to aluminum or -

Page 9 1313063 Case No. 92107566_Year of the month __ Amendment ____________ V. Description of the invention (5) When the aluminum alloy leaves the vacuum deposition chamber, it will contact the atmosphere and form an oxide that is difficult to remove, thus affecting the subsequent process or The value of the contact resistance connected to its metal layer in subsequent processes. Therefore, the second metal layer 30 can be formed on the first metal layer 20 in the same vacuum deposition chamber, so that the second metal layer 30 is formed in the first metal layer 20 without leaving the vacuum. Above the metal layer 20, it is possible to avoid the problem of electrical properties (for example, higher contact resistance |) when the aluminum or aluminum alloy surface first generates oxides and is connected to the metal layer of the other layer. The preferred material of the second metal layer 30 is chromium or chrome telluride, preferably having a thickness in the range of 5 - 30 nm, and more preferably in the range of 10 - 14 nm.

I then performs pattern transfer of the thin film transistor gate to define an etching pattern of the first metal layer 2 0 ® ί and the second metal layer 30. Since the etch rate of bismuth aluminum and chromium or aluminum bismuth and bismuth bismuth sulphide is equivalent to each other, the effect of the sinter can not occur on the subsequent I process after etching, but the shape of the complete chamfer. Therefore, it is possible to avoid the eaves effect of the two-layer structure due to the difference in etching rate in the prior art. The etched thin film transistor gate is moved into a chemical vapor deposition apparatus, and a helium gas layer and a chromium layer or a titanium layer and a chrome layer are used as obstacles by a helium plasma treatment method. The layer is surface-treated for the gate contact surface of the thin film transistor, and the residue and the oxidation product remaining after the etching are removed by the helium plasma 60. In this way, the contact impedance of the thin film transistor gate can be effectively reduced. i 丨The third figure shows the thin film transistor gate formed by the method of the present invention, in the thin i

Page 10 1313063 Case No. 92107566_年月日日__ V. Description of invention (6)

An insulating layer 40 is formed on the gate of the film transistor, and an opening is formed on the insulating layer 40. Indium tin oxide 50 is formed on the insulating layer 40 to cover the opening and penetrate the opening and the second metal layer. 30 0 electrical connection. According to the results of experiments by the inventors, the two-layer structure of the thin film transistor gate formed by the method of the present invention is double-layered with general aluminum/titanium nitride (A 1 N d / A 1 N d N ! i) Compared with the thin film transistor gate, it can effectively reduce the contact impedance of 60-8 0% left + right. Therefore, the thin film transistor gate formed by the method

The J i pole can provide a low RC delay time, especially for large-size (20-leaf or more) thin-film transistor liquid crystals (5) that require a shorter RC delay and delay time. |

In summary, the present invention discloses a method of reducing the contact resistance of a thin film transistor. According to the invention, it comprises forming a metal conductive film on a substrate and performing a plasma surface treatment. The metal conductive film comprises a titanium aluminum layer formed on the substrate, and a chromium layer or chrome telluride

An I i layer formed on the deuterated aluminum layer to provide a lower wiring resistance; and a plasma surface treatment using a deuterated aluminum layer and a chromium layer as a barrier layer to treat the antimony aluminum layer and the chromium layer Surface to reduce the contact resistance of the metal conductive film. Because of this, it can avoid the use of a single layer of Ilu, Ilu or Ming alloy and other metals in the prior art as a gate of a thin film transistor: or other metals such as chromium. To form a gate of a thin film transistor, there is a problem of higher contact resistance or wiring resistance, and a shorter RC delay.

Page 11 1313063 Case No. 92107566_Year Month Day _______ Charm ___________________ Simple illustration of the figure i [Simple description of the drawing]

BRIEF DESCRIPTION OF THE DRAWINGS In the prior art, a schematic diagram of a thin film transistor gate double layer metal structure composed of aluminum or an aluminum alloy and other metals is provided. The second figure is a preferred embodiment of the present invention, A thin film transistor gate double layer metal structure composed of an aluminum layer and a chromium or chrome telluride layer, which is schematically illustrated by a gas plasma treatment method; and a third diagram of a preferred embodiment of the present invention, A thin film transistor gate double-layer metal structure composed of an aluminum layer and a chromium or chrome telluride layer is electrically connected to indium tin oxide through an opening. [Main component symbol description] 10 Substrate 20 First metal layer 3 0 Second metal layer 4 0 Insulation layer 5 0 Indium tin oxide layer ! 60 plasma

Page 12

Claims (1)

T313063 Case No. 92107566 Revised frozen q屮年¥月1曰6, application patent scope 1. A method for reducing the contact resistance of a thin film transistor, comprising: forming a metal conductive film on a substrate, the formation of the metal conductive film The method comprises: forming an aluminum nitride (A 1 Nd) layer on the substrate; forming a chromium (Cr) layer on the layer of the mineralization layer; patterning the titanium aluminum layer and the chromium (Cr ) layer; A helium (He) gas beam surface treatment is performed, and the patterned natriment layer and the patterned chromium layer are treated as a barrier layer to treat the surface of the patterned aluminum telluride layer and the patterned chromium layer. 2. The method of reducing the contact resistance of a thin film transistor according to the first aspect of the patent application, wherein the substrate is a glass substrate. 3. The method for reducing the contact resistance of a thin film transistor according to claim 1, further comprising forming an insulating layer on the surface of the titanium aluminum layer and the chromium layer, the insulating layer having an opening in the contact Above the surface, a metal conductive layer is electrically connected to the metal conductive film through the opening. j |4. A method for reducing the contact resistance of a thin film transistor according to claim 3, wherein the metal conductive layer is made of indium tin oxide. 5. A method of reducing the contact resistance of a thin film transistor according to claim 1, wherein the titanium aluminum layer and the chromium layer are completed in the same deposition chamber. Page 13 Π 1 1061 Case No. 92107566_Yearly Revision 曰6. Patent Application Range 6. The method for reducing the contact resistance of a thin film transistor according to the first application of the patent scope, wherein the thickness of the chrome layer is 10 - 1 4 Nano. 7. The method of reducing the contact resistance of a thin film transistor according to the first aspect of the patent application, wherein the metal conductive film is a gate of a thin film transistor. 8. The method of claim 1, wherein the metal conductive film is chamfered. 9. A method of reducing contact impedance of a thin film transistor, comprising: Forming a metal conductive film on a substrate, the step of forming the metal conductive film comprises: forming a layer of aluminum telluride (A 1 N d) on the substrate; forming a chrome-like compound (C r S i a layer of 'icide' is located on the layer of the smelting layer; patterning the layer of bismuth aluminum and the layer of chrome telluride (Cr S 1 1 1 c 1 de); Performing a helium (He) gas plasma surface treatment, treating the patterned titaniumized aluminum layer i and the patterned chromium telluride layer with the patterned aluminum halide layer and the patterned chromium telluride layer as a barrier layer One of the contact surfaces. 0. A method for reducing the contact resistance i of a thin film transistor according to the scope of claim 9 wherein the substrate is a glass substrate. Page 14 1313063 Case No. 92107566_年月日日_ili_____________ VI. Patent Application Range 1 1. The method for reducing the contact resistance of a thin film transistor according to the scope of claim 9 further includes forming an insulating layer on the aluminum telluride. On the surface of the layer and the chrome telluride layer, the insulating layer has an opening over the contact surface, such that a metal conductive layer is electrically connected to the metal conductive film through the opening. 1 2 . The method of reducing the contact resistance of a thin film transistor according to claim 1 , wherein the metal conductive layer is made of indium tin oxide. 1 3. A method of reducing the contact resistance of a thin film transistor according to claim 9 wherein the aluminum halide layer and the chrome germanide layer are completed in the same deposition chamber. 1 4. The method of claim 9, wherein the chrome telluride layer has a thickness of from 10 to 14 nm. 1 5. The method of reducing the contact resistance of a thin film transistor according to claim 8 wherein the metal conductive film is a gate of a thin film transistor. Page 15 T313063 Case No. 92107566_Years and Months _ VI. Designation of representative drawings (1) The representative figure of this case is: the second figure (2), the symbol of the representative figure of this case is simple: 1 0 substrate 2 0 first metal Layer 3 0 second metal layer 5 0 indium tin oxide layer 60 plasma Page 4