!3113〇5 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種内歲時脈訊號多位階訊號發 及—種利用該方法驅動顯示面板之裝置，更具體^法 方法驅動顯示面板之裝置，其中在發送中 驅動襞置之時脈訊號。 關於-_料脈訊鮮位階訊號發送方法’係 、I 裡刊用該 示面板 内嵌一顯 【先前技術】 近來，除可攜式電子裝置（如筆記型電腦 ^通信裝置）日益普及之外，數位裝置及個人電腦=攜 規模亦持續增加。偶此類裝置與使用者之間=場 顯示裝置需具有重量輕及功率雜低 妾 通常使賴如LCD (液晶顯示器）、PDP (電漿奸面因此， ^ 有機電激發域之_ 器），而不採用習知CRT (陰極射線管）顯科。面‘ 如上所述，對於一般咖系統，需要用 時序控制器及驅動器積體電路(掃 ： 驅動積體電路)來驅動顯示面板。然而，在== 中，產生了大量有間=資料訊號之㈣ 磁波及射頻波在電子裝置中c形干擾係由電 磁干擾）或者叫射頻干擾）（下文中統稱為“腦”）。電 此外，目前求域幕及高解析度， 1311305 積 特別在冋解軒度面板之情況下，因為行線數為數百 2千條’所以用於驅動此等行線中每-行線之行驅動U …、路之輸人需要—高速資料發送技術。 如上所述，因為近來補充了 EMI之標準而更加‘ 速發送訊號之技術，故在面板内顯示器中普遍地使用^ Rsds (縮減擺動差動職發送）或最小等小訊: 動訊號發送方法來最終連接時序控彻與面板。、 "圖1 #、朗-f知RSDS (賴軸絲職發送 崎例之示意圖。而圖2係說明—f知最小LVDS = 差動訊號發送）實制之示意圖。RSDS及最小Lv加一勺 括-或多條資料訊號線，以滿足利用_與資料同步之二包 時脈訊號所需之頻寬。因為僅利用—時脈訊號，所以:離 提供該時脈訊號及該等資料訊號以匹配面板内部之〜^員 積體電路20及21之數目。即如圖丨、圖2 仃驅動[3113〇5 IX. Description of the invention: [Technical field of the invention] The present invention relates to a multi-level signal transmission of a year-old clock signal and a device for driving a display panel by the method, and more specifically driving the display by a method A device of a panel in which a clock signal of a device is driven during transmission. Regarding the -_ material pulse signal transmission method ', 'I, the magazine uses the display panel to embed a display. [Prior Art] Recently, in addition to the increasing popularity of portable electronic devices (such as notebook computers) , digital devices and personal computers = the scale of the number of carriers continues to increase. Even between such devices and users = the field display device needs to be light in weight and low in power, which is usually caused by LCD (Liquid Crystal Display), PDP (Electrical Electric Excitation Field, etc.) Instead of the conventional CRT (cathode ray tube). As described above, for a general coffee system, it is necessary to drive the display panel with a timing controller and a driver integrated circuit (scan: drive integrated circuit). However, in ==, a large number of (4) magnetic waves and radio frequency waves in the electronic device are generated by electromagnetic interference or radio frequency interference (hereinafter collectively referred to as "brain"). In addition, the current field and high resolution, 1311305 product is especially in the case of the Xuan Xuan panel, because the number of lines is hundreds of thousand ', so it is used to drive each line in these lines. Line drive U ..., the road to the need of people - high-speed data transmission technology. As mentioned above, because of the recent addition of the EMI standard and the technology of transmitting signals at a faster speed, it is common to use ^ Rsds (reduced swing differential transmission) or minimum telecommunications in the panel display: the signal transmission method The final connection timing is controlled with the panel. , " Figure 1 #, 朗-f know RSDS (Lai axis silk job sent a schematic diagram of the case, and Figure 2 is a description - f know the minimum LVDS = differential signal transmission) schematic diagram. The RSDS and the minimum Lv add a scoop of - or multiple data signal lines to meet the bandwidth required to utilize the two-package clock signal synchronized with the data. Since only the clock signal is used, the clock signal and the data signals are provided to match the number of the integrated circuit circuits 20 and 21 inside the panel. That is, as shown in Figure 丨, Figure 2 仃 drive
及最小LVDS均採用多點分支方法。 RSDS 然而’ RSDS及最小LVDS兩者所採用之多點八 係有缺失的，其原因在於：由於時脈訊號之大負刀、支方法 之增加及訊號品質之降低（例如因線路分支點、戴、 所引起的訊號失真）’而使最大工作速度愛到 抗失酉己 美國國家半導體公司最近宣佈了一稀 Λ制。 使用點劈| ^ 之面板内介面，即PPDS (點對點差動訊號笋 ' 、點方法 圖3所示之此種方法，將時脈訊號發送至^适）。板據如 22之每一積體電路，以解決該行驅動22 =驅動積體電路 時發生之問題。而且’此方法之特徵在於了用該時脈訊號 、在一時序控制 1311305 器與一單一行驅動積體電路22之間配置一獨立資料線，而 根據慣例將複數條資料線連接至複數個行驅動積體電路。 亦即，對於如圖3所示之pPDS，當使用一串聯方法時，將 從一 PPDS時序控制器12處配置一單一獨立資料線至該單 一行驅動積體電路22。 因此，與RSDS及最小LVDS所使用之習知多點分支 方法相比，減少了阻抗失配，故藉由減少訊號線總數而降 低了 EMI及製作成本。 然而，與習知RSDS相比，需要更高速度之時脈訊號， 而且分離之時脈線被分別連接至所有行驅動積體電路，因 此存在額外成本。此外’當用於取樣資料之時脈訊號與資 料訊號之間存在偏斜時，在㈣取_前能產生錯誤。 為了防止發生此種情況’需要用來修正該偏斜之分離電 路。因此，PPDS具有不同於習知RSDS及最小Lvds之問 題，而該等問題應該予以解決。 另外，如圖4所示，最近已提出了—種組態，其中行 驅動積體電路23以-種鍵形式接收時脈訊號。此種板離之 優點在於可減少由時脈社多點分支㈣起之阻抗失配以 及所產生之EMI。然而，此種組態亦存在問題，即由於行 驅動積體電路23間存在時脈延遲而會導致資料取樣失敗。 如上所述，面板内介面之最新趨勢聚焦於減少訊號線 Γ組件。另外，與訊號線數目之減少相較，面板 之工作速度以及解析度得以提高，因此需要― 板内介面，其可料在料發料財會發生之偏斜2 1311305 相對抖動等問題。 【發明内容】 方=發明，〜目的係提供内料脈訊號多位階訊號發送 控制考利用垓方法驅動顯示面板之裝置，其用於在一時序 送）_行驅動積體電路之間發送訊號（資料及時脈發 肩祥Λ中訊號線之數目* emi顯著減少，並福由一復 原時脈精確執彳卜詩取樣。 下面將插述本發明之其他目的及優點，並且藉由本發 日之實施例對其進行說明。另外，本發明之目的及優點^ 由申請專利_中_示之方法及其組合而予實施。a 根據本發明之第一態樣，其提供了一種内歲時脈訊號 多位階訊號發送方法，該方法用於—發送終端，以在一時 序控制器與一顯示面板驅動裝置之顯示驅動器積體電路之 間發送訊號，該方法包括以下㈣：將資料賴為電磨小 於一預定參考電壓之訊號；將時脈訊號轉換為電壓大於該 預定參考電壓之訊號；以及藉由將轉換後之時脈訊號内欲 於轉換後之資料訊號之間，將轉換後之時脈訊號及轉換後 之資料訊號多工化。 、 根據本發明之第二態樣，其提供了—種内敌時脈訊號 多位階訊號發送方法，該方法用於一接收終端中，以在一 時序控制器與一顯示面板驅動裝置之顯示驅動器積體電路 之間發送訊號，該方法包括：當所接收訊號之電壓大2一 參考電壓時，將所接收訊號復原為-時脈，而t所接收m 1311305 號之電壓小於該參考電壓時，將所接收訊號復原為一資料。 ' 根據本發明之弟二恝樣，其提供了一種内喪時脈訊號 .· 多位階訊號發送方法，該方法用於一發送終端中，以在一 日可序控制器與一顯示面板驅動裝置之顯示驅動器積體電路 之間I送sfL號，該方法包括以下步驟：將一資料轉換為電 壓大於一預定參考電壓之訊號；將一時脈轉換為電壓小於 該預疋參考電壓之讯號；以及藉由將轉換後之時脈訊號内 嵌於轉換後之資料訊號之間，將轉換後之時脈訊號與轉換 後之資料訊號多工化。 根據本發明之弟四恝樣，其提供了一種内喪時脈訊號 夕位階訊號發送方法，該方法用於一接收終端中，以在一 日守序控制器與一顯示面板驅動裝置之顯示驅動器積體電路 之間發送訊號，該方法包括：當所接收訊號之電壓大於一 參考電壓時，將所接收訊號復原為一資料，當所接收訊號 之電壓小於該參考電壓時，將所接收訊號復原為一時脈。 根據本發明之第五態樣，其提供了一種包括一時序控 制器、複數個行驅動積體電路及至少一列驅動積體電路之 驅動裝置，其中-差動對連接於該時序控制器與該複數個 行驅動積體電路之每一積體電路之間，用於將一資料訊號 及一時脈訊號從該時序控制器發送至該複數個行驅動積體 電路，並且其中將該時脈訊號内嵌於該資料訊號之間，以 具有不同於資料訊號之訊號幅度，且傳送該時脈訊鞔。 根據本發明之第六態樣，其提供了一種包括一時序抄 制器、複數個行驅動積體電路及至少一列驅動積體電路之 1311305 驅動裝置’其中一差動對連接於該時序控制器與該複數個 行驅動積體電路之至少兩積體電路之間，用於將一資料訊 號與一時脈訊號從該時序控制器發送到該等至少兩個行驅 動積體電路，且其中將該時脈訊號内嵌於該資料訊號之 間，以具有不同於該資料訊號之訊號幅度，且傳送該時脈 訊號。 【實施方式】 現將參照隨附圖式詳細說明本發明。用於「發明說明」 士「申請專利範圍」巾之術語及措詞不應限於普通含義或」 字面含義。所作的錢符合本發明之定義及概念，本發明 基於（諸）發明者可能定義之術語概念的原理，以最佳之 方弋説月八發明。因此，當已參考其較佳實施例示出並説 明本發明時，熟悉此技術者可理解各種不同之變化形式， 在不背離本發明隨㈣請專利範圍所限定之精神及範圍 時’均可實施本發明之細節。 、根據本發明，採用了—種習知之多位階訊號發送方 套新穎之編碼方法，其中一時脈訊號資訊内嵌 於該等資料訊號之間，取消或替代—分離之時脈訊號線， 因此解決了諸如由資料線及時脈線之多點分支所引起之阻 抗失配及所產生如E MI #之習知技術問題。 …另外，根據本發明，可利用多位階偵測方法很容易地 從内截於資料峨線中之時脈訊號中擷取時脈訊號組成， 而且該時脈訊餘分僅絲樣實際f料所需頻率的十分之 1311305 一。因此，由於該頻率係小頻率且可防止當資料訊號與時 脈訊號分離時產生之相對抖動或偏斜問題，以便執行高速 穩定之工作，所以在減少整個系統之EMI方面發揮了重要 之作用。 [第一實施例] 圖5係一說明根據本發明第一實施例之内嵌時脈面板 内顯示器結構之示意圖，並且為了便於理解，圖6係一說 明圖5在一時序控制器與行驅動積體電路之間發送時脈及 資料之結構示意圖。參照圖5及圖6，一顯示器包括一時 序控制器14、複數個行驅動積體電路24、複數個列驅動積 體電路30及顯示面板40。一用於顯示面板40之驅動裝置 包括時序控制器14、複數個行驅動積體電路24及複數個 列驅動積體電路30。 顯示面板40作為根據掃描訊號及資料訊號顯示一影 像之部分，並且可選自各種顯示面板，諸如LCD面板、PDP 面板及OELD面板。複數個列驅動積體電路30將掃描訊號 S1至Sn施加到顯示面板40，而且複數個行驅動積體電路 24將資料訊號D1至Dn施加到顯示面板40。時序控制器 14將DATA發送至複數個行驅動積體電路24,並且將時脈 CLK及_CLK_R及起始脈衝SP及SP_R施加到複數個行驅 動積體電路24及複數個列驅動積體電路30。從時序控制 器30發送至複數個行驅動積體電路24之DATA可僅包括 一將顯示在該面板40上之影像資料或該影像資料及一控 制訊號。 11 1311305 與習知技術相反的，根據本發明之第一實施例，僅— • 對差動對被用於將時脈C L K及資料訊號d AT A從時序控制 -器14發送至行驅動積體電路24。該時脈訊號CLK内嵌於 該資料訊號data之間，以便在時序控制器14處（即發送 終端上）具有不同之訊號幅度’並傳送該時脈訊號。該時 脈訊號CLK利用在行驅動積體電路24處（即接收終端上） 所接收之訊號幅度，而可與該資料訊號DATA區分。 圖7係一種多位階訊號發送範例之一示意圖，該多位 階訊號發送可被用於一如圖5中所示介於時序控制器與行 驅動積體電路間之介面。參考圖5至圖7，時序控制写14 將該資料轉換成電壓小於一預定參考電壓之一訊號，將一 時脈轉換成電壓大於該預定參考電壓之一訊號，並且將轉 換後之時脈訊號内嵌於該轉換後之資料訊號間，以便在多 工化後進行發送。另外，藉由此技術領域所習知的差動訊 號處理方法可在行驅動積體電路24 (即接收終端）上獲得 該資料訊號之值，而且可利用Vrefh和Vrefl區分時脈訊 號。亦即’當兩輸入訊號差之絕對值丨¥匕，？~%11，11|較小於 該參考訊號之幅度|Vrefh—Vrefl|時，該兩輸入訊號將作為 該資料訊號處理。因此，當Vin，p較大於Vin，n，該資料值 被设疋為1 ;而當Vin，p較小於Vin,n時，該資料值則被設 定為0。當兩輸入訊號差的絕對值較大於該參考訊號之幅 度(|Vm，p〜 Vin，n| > |Vrefh — Vrefl|)時，則該兩輸入訊號將被 識別為該時脈。 如圖所示，因為一實際内傲時脈之頻率低於資料之發 12 1311305 相=收_產生一與利用PLL(未示出)之 速度之時脈訊號，並且利用同樣之方法取樣該 統之EMI態樣中，最重要之因素係時脈訊號， 幅度係成正比於該時脈訊號之幅度與頻 ，該時脈之頻率可減少至習知_ 系、'克之1/10或測，因此顯著地減少了酿。 中復二時從如圖所示的該資料及該時脈訊號組態 Γ因：=含有資料之自然同步狀態方式復 ，復原時脈執行取樣於： 行該資料取樣。 及咖相比，可更精確地執 二且所，所示，當實際可能出現之訊號組合數目係 :7，戶“之訊號係兩資料訊號及一時 訊號差的絕對摩― 而且=1’丨時，將會無條件地產生該時脈訊號， 號同時發送—分離之控制訊號或-=像貧科。虽該符號係正時，其被識別為發送m 符號係負時，其被識別為發送0。 田β 圖8係另一種多位階訊號發送範例之—音 位階訊號發送可被用於—如圖5中所示介於時雜制匕 行驅動積體電路間之介面。 市 為電if、圖6及圊8,時序控制器14將該資料轉換 ===參考電壓之訊號’將時脈轉換為電壓小 於箱疋參考電塵之訊號’且將該轉換後之時脈内嵌於該 13 1311305 轉換後之資料訊號之間以多工化然後進行發送。另外，當 • 所接收之訊號電塵大於一參考電壓時，該行驅動積體電路 - 24 (即接收終端）將所接收之訊號復原為該資料，當所接 收之訊號電壓小於該參考電壓時’該行驅動積體電路24(即 接收終端）將所接收之訊號復原為談時脈。 如圖所示’與資料訊號不同的，因為時脈訊號不具有 諸如1及0之概念’故三位階已足以用於多位階之訊號發 送。亦即’當兩輸入訊號之差的絕對值|Vin，p —Vin,n|較大 於該參考訊號之幅度|Vrefh —Vrefl|時，該兩輸入訊號將被 識別為實料訊號’並且根據該資料訊號之符號，該資料將 被識別為1或0。相反地，即當兩輸入訊號之差的絕對值 | Vin，P — Vin，n|較小於該參考訊號之幅度丨Vrefli 一心, 時，則該兩輸入訊號將被識別為時脈訊號。因此，不同於 圖7中由於四位階之需求而需要MVx (△%指雜訊容限） 之電壓操作方法，圖8之方法可在2Δνχ之低電壓上作業， 此係因為三位階對於圖8之方法係足夠的。 、 圖9係再一種多位階訊號發送範例之-示意圖，該多 位階訊號料可被躲—如圖5巾所示介 行驅動積體電路間之介面。 料係在所示實例之情況下’雖然時脈訊號與資 ㈣-起讀送，但是因為對於每—資料 脈訊號，所以需要由DLT、Ρττ 个疋〜畀在日寸 復原電路。由DLL及二 對行驅動賴電路沒有㈣1 電流之增加 隹小LCD之行驅動積 14 1311305 體電路之情況下，可能會存右 子在問通。而且，當資料之私读 速度不是很高時，藉由料含* 田:付之切 〆 有每貝料之時脈而將時脈 復原電路配置為簡單電路係為有利的。 如圖9中所示之方法將解決此類問題。雖然圖9所示 方法與圖7及® 8在Μ階方_似，但是不同之處在於 時脈訊號係在-對應資料週期—半之期隨發送。當兩輸 入訊號之差的絕對值|Vm，p —Vin，n^大於該參考訊號之幅 度IV她—Vrefl丨時，會該兩輸入訊號將被識別為資料訊 號，而且根據資料訊號之符號將資料識別為丨或〇。相反 地，當兩輸入訊號之差的絕對值|Vin，p —Vin，n|較小於參考 讯號之幅度IVrefh —Vrefl|時，則兩輸出訊號將無條件地被 識別為時脈訊號。 如復原之資料及時脈訊號所示，該時脈訊號位於每一 資料過渡週期中間。該時脈復原電路之目的在於將該時脈 置於最理想取樣位置，即資料過渡週期之中間，顯然本發 明之號組態滿足此要求。亦即，當該時脈訊號之長度被 設定為與該資料長度相同時，將可平分該資料訊號之週 期，以便在該接收終端處，為每一該等資料復原時脈訊號。 透過此過程，可藉由一簡單云取樣電路復原所接收之資料 訊號。 、 根據如圖9所示之結構，僅當所接收資料超出一臨限 值時’才改變所触資料之符號。印僅當兩輸入訊號差值 之絕對值|Vin，p —Vin，n|較大於該參考訊號之幅度|Vrefh — Vrefl|時’才根據該資料之符號改變該值。 15 1311305 與此相反地，對於時脈可能存在兩種組態。第一，類 似於資料者’如果僅在當兩輸入訊號差值之絕對值|Vin，p Vin，n|較小於參考訊號之幅度| vrefj^vrefll的情況時才改 變極性’則在該時脈之上升邊緣及下降邊緣均可取樣該資 料。第二，與上述情況相反者，在當兩輸入訊號差值之絕 對值I Vin，p — Vin，n|較大於參考訊號之幅度I Vrefh - Vrefll的. 情況，以及當兩個輸入訊號差值之絕對值|Vin，p —Vin，n|較 小於參考訊號之幅度IVrefh — Vrefl|的情況時被視為該時脈 之過渡週期，則該資料係在如圖9所示之時脈訊號上升邊 緣處被取樣。 儘管如圖9所示主要描述了時脈訊號小於資料訊號之 情況’但是當該時脈訊號之幅度大於資料訊號之幅度時， 則可將該時脈訊號内嵌於該等資料訊號之每一訊號中，熟 悉此項技術者易於理解該技術。因此，省略了關於此技術 之詳細描述。 圖10係再一種多位階訊號發送範例之一示意圖，該多 位階訊號發送可被用於一如圖5中所示介於時序控制器與 行驅動積體電路間之介面。 參考圖10，時脈訊號之極性係遵循先前資料之極性。 即資料η-1與該時脈具有相同極性，並且增加該時脈之末 端位元，以另外產生與先前資料訊號（資料η-1)相同虛擬 資料之訊號。 藉由該虛擬資料可獲得足夠之上升時間及下降時間。 增加該虛擬資料以防止時脈在圖7之情況下根據先前資料 16 1311305 形式加速或延遲。因此’在此種情況下，減少了？丨起抖動 之可能性（產生原因在於資料.過渡與被視為時脈訊號之過 度間的偏斜率）’所以其對於在高速發送巾健穩定工作係 有利的。 亦即，雖然被用於產生該時脈訊號之零過位置係取決 於如圖7狀況中之先前資料的值，但在圖1()之情況中不產 生零式樣相關之抖動係為有利的。 [第二實施例] 圖11係-說明根據本發明第二實施例之内歲時派面 板内顯示器結構之示意圖，並且為了便於理解，圖12係一 僅說明圖11在-時序控制H與行驅動積體電路 時脈及資料之結構示意圖。 s x 、 相較第-實施例與第二實施例，第二實施例使用了點 對偶方案，而第一實施例則使用了點對點方案。因為除了 第二實施例使用了點對偶方案外，第二實施例係與第2與 同的’所以圖7至圖i。中所描述用於時序控制器: 動積體電路間之介面的多位階訊號發送 ::施例。然而’在第-實施例之情況下，將4= 連接至-行驅動積體電路；而在第二實施例之情況 差動對則被連接至兩行驅動積體電路2S。因此 每 施之情況下，經由差動對所發送之資料 ’實施例之兩倍。 t增加為弟 其中所描述之本發明顯示面板乃包含各種顯示面板， 么明内嵌時脈訊號之多位階訊號發送方法可被用於 17 1311305And the minimum LVDS uses a multi-point branching method. RSDS However, the multiple points and eight systems used in both RSDS and minimum LVDS are missing because of the large negative knives of the clock signal, the increase of the branching method, and the degradation of the signal quality (for example, due to the branch point of the line, wearing , the resulting signal distortion) 'and the maximum working speed to love to resist the loss of the United States National Semiconductor Corporation recently announced a thin system. Use the intra-panel interface of point 劈| ^, ie PPDS (point-to-point differential signal shooter ', point method, as shown in Figure 3, to send the clock signal to ^). The board is based on each of the integrated circuits of 22 to solve the problem that occurs when the row drive 22 = drives the integrated circuit. Moreover, the method is characterized in that an independent data line is arranged between the timing control 1311305 and a single row driving integrated circuit 22 by using the clock signal, and a plurality of data lines are connected to a plurality of lines according to a convention. Drive the integrated circuit. That is, for the pPDS shown in Fig. 3, when a series method is used, a single independent data line is arranged from a PPDS timing controller 12 to the one-line driving integrated circuit 22. Therefore, impedance mismatch is reduced compared to the conventional multipoint branching method used in RSDS and minimum LVDS, thereby reducing EMI and manufacturing costs by reducing the total number of signal lines. However, compared to the conventional RSDS, a higher speed clock signal is required, and the separated clock lines are respectively connected to all the row driving integrated circuits, so there is an additional cost. In addition, when there is a skew between the clock signal and the data signal used for sampling data, an error can be generated before (4) taking _. In order to prevent this from happening, a separate circuit for correcting the deflection is required. Therefore, PPDS has problems different from conventional RSDS and minimum Lvds, and such problems should be solved. Further, as shown in Fig. 4, a configuration has recently been proposed in which the row driving integrated circuit 23 receives the clock signal in the form of a key. The advantage of this type of delamination is that it reduces the impedance mismatch and the EMI generated by the multi-point branch (4) of the clock. However, this configuration also has a problem in that data sampling failure occurs due to a clock delay between the row driving integrated circuits 23. As mentioned above, the latest trend in the in-panel interface has focused on reducing the signal line components. In addition, compared with the reduction of the number of signal lines, the working speed and resolution of the panel are improved, so the "in-board interface" is required, which can be expected to be skewed in the material billing and accounting 2 1311305 relative jitter. [Description of the Invention] Fang = invention, ~ the purpose is to provide the internal material pulse signal multi-level signal transmission control test device using the method to drive the display panel, which is used to send signals between a time series send _ row drive integrated circuit ( The number of data in a timely manner, the number of the signal line * emi is significantly reduced, and the blessing is performed by a recovery clock. The other purposes and advantages of the present invention will be explained and implemented by this date. In addition, the objects and advantages of the present invention are implemented by the method of the patent application and the combination thereof. A according to the first aspect of the present invention, an internal clock signal is provided. A multi-level signal transmission method for transmitting a signal between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising the following (4): the data is determined to be less than an electric grinder a predetermined reference voltage signal; converting the clock signal into a signal having a voltage greater than the predetermined reference voltage; and using the converted clock signal to convert the signal Between the signal signals, the converted clock signal and the converted data signal are multiplexed. According to the second aspect of the present invention, the method for transmitting the multi-level signal of the internal enemy clock signal is provided. Used in a receiving terminal to transmit a signal between a timing controller and a display driver integrated circuit of a display panel driving device, the method comprising: receiving when the voltage of the received signal is greater than a reference voltage The signal is restored to the -clock, and when the voltage received by m 1311305 is less than the reference voltage, the received signal is restored to a data. ' According to the second aspect of the present invention, it provides a nucleus signal. The multi-level signal transmission method is used in a transmitting terminal to send an sfL number between the one-day order controller and the display driver integrated circuit of a display panel driving device, and the method comprises the following steps: Converting a data into a signal having a voltage greater than a predetermined reference voltage; converting a clock to a signal having a voltage less than the predetermined reference voltage; and by converting the converted clock signal Between the converted data signals, the converted clock signal and the converted data signal are multiplexed. According to the fourth embodiment of the present invention, the method provides a method for transmitting the internal time pulse signal The method is used in a receiving terminal to transmit a signal between a one-day sequence controller and a display driver integrated circuit of a display panel driving device, the method comprising: when the voltage of the received signal is greater than a reference voltage Recovering the received signal into a data, and restoring the received signal to a clock when the voltage of the received signal is less than the reference voltage. According to a fifth aspect of the present invention, there is provided a timing controller, a plurality of row driving integrated circuits and at least one driving device for driving the integrated circuits, wherein a differential pair is connected between the timing controller and each of the plurality of row driving integrated circuits for A data signal and a clock signal are sent from the timing controller to the plurality of row driving integrated circuits, and wherein the clock signal is embedded in the data signal , Having a different signal magnitude to the data signals, and transmits the clock information harness. According to a sixth aspect of the present invention, there is provided a 1311305 driving device comprising a timing manipulator, a plurality of row driving integrated circuits and at least one column of driving integrated circuits, wherein a differential pair is connected to the timing controller Between the at least two integrated circuits of the plurality of row driving integrated circuits, for transmitting a data signal and a clock signal from the timing controller to the at least two row driving integrated circuits, and wherein The clock signal is embedded between the data signals to have a signal amplitude different from the data signal, and the clock signal is transmitted. [Embodiment] The present invention will now be described in detail with reference to the accompanying drawings. The terminology and wording used in the "Invention Description" of the "Scope of Application" should not be limited to the ordinary meaning or "literal meaning". The money made is in accordance with the definitions and concepts of the present invention, and the present invention is based on the principle of the term concept that the inventors may define, and is invented by the best of the eight. Therefore, the present invention may be embodied and described with reference to the preferred embodiments thereof, and various modifications may be made without departing from the spirit and scope of the invention as defined by the scope of the invention. Details of the invention. According to the present invention, a novel multi-level signal transmitting method is used, in which a clock signal information is embedded between the data signals, and the clock signal line is cancelled or replaced, thereby solving the problem. Impedance mismatches caused by multiple branching of the data line and the timely pulse line and the prior art problems such as E MI #. In addition, according to the present invention, the multi-level detection method can be easily used to extract the clock signal from the clock signal in the data line, and the pulse remainder is only the actual sample material. The required frequency is very high, 1311305 one. Therefore, since the frequency is small in frequency and prevents relative jitter or skew generated when the data signal is separated from the clock signal, in order to perform high-speed stabilization, it plays an important role in reducing EMI of the entire system. [First Embodiment] FIG. 5 is a schematic view showing the structure of an in-line clock panel display according to a first embodiment of the present invention, and FIG. 6 is a diagram illustrating a timing controller and a row driver in FIG. A schematic diagram of the structure of the clock and data transmitted between the integrated circuits. Referring to Figures 5 and 6, a display includes a timing controller 14, a plurality of row drive integrated circuits 24, a plurality of column drive integrated circuits 30, and a display panel 40. A driving device for the display panel 40 includes a timing controller 14, a plurality of row driving integrated circuits 24, and a plurality of column driving integrated circuits 30. The display panel 40 serves as a portion for displaying an image based on the scanning signal and the data signal, and may be selected from various display panels such as an LCD panel, a PDP panel, and an OELD panel. The plurality of column driving integrated circuits 30 apply the scanning signals S1 to Sn to the display panel 40, and the plurality of row driving integrated circuits 24 apply the data signals D1 to Dn to the display panel 40. The timing controller 14 sends the DATA to the plurality of row drive integrated circuits 24, and applies the clocks CLK and _CLK_R and the start pulses SP and SP_R to the plurality of row drive integrated circuits 24 and the plurality of column drive integrated circuits. 30. The DATA transmitted from the timing controller 30 to the plurality of row driving integrated circuits 24 may include only one of the image data or the image data to be displayed on the panel 40 and a control signal. 11 1311305 In contrast to the prior art, according to the first embodiment of the present invention, only the pair of differential pairs are used to transmit the clock CLK and the data signal d AT A from the timing controller 14 to the row driving integrated body. Circuit 24. The clock signal CLK is embedded between the data signals data to have different signal amplitudes at the timing controller 14 (i.e., on the transmitting terminal) and to transmit the clock signals. The clock signal CLK can be distinguished from the data signal DATA by the amplitude of the signal received at the row driving integrated circuit 24 (i.e., at the receiving terminal). Figure 7 is a schematic diagram of a multi-level signal transmission example that can be used in an interface between a timing controller and a row driver integrated circuit as shown in Figure 5. Referring to FIG. 5 to FIG. 7, the timing control write 14 converts the data into a signal whose voltage is less than a predetermined reference voltage, and converts a clock into a signal whose voltage is greater than the predetermined reference voltage, and is converted into a clock signal. Embedded in the converted data signal for transmission after multiplexing. In addition, the value of the data signal can be obtained on the row driving integrated circuit 24 (i.e., the receiving terminal) by the differential signal processing method known in the art, and the clock signal can be distinguished by Vrefh and Vrefl. That is, when the absolute value of the difference between the two input signals is 丨¥匕,? When ~%11,11| is smaller than the amplitude of the reference signal |Vrefh_Vrefl|, the two input signals will be processed as the data signal. Therefore, when Vin,p is larger than Vin,n, the data value is set to 1; and when Vin,p is smaller than Vin,n, the data value is set to 0. When the absolute value of the difference between the two input signals is larger than the amplitude of the reference signal (|Vm, p~ Vin, n| > |Vrefh - Vrefl|), the two input signals will be recognized as the clock. As shown in the figure, because the frequency of an actual arrogant clock is lower than the data transmission 12 1311305 phase = _ generates a clock signal with the speed of the PLL (not shown), and uses the same method to sample the system In the EMI aspect, the most important factor is the clock signal, the amplitude is proportional to the amplitude and frequency of the clock signal, and the frequency of the clock can be reduced to 1/10 of the conventional _ system, 'gram, or measurement, Therefore, the brewing is significantly reduced. In the second and second time, the data and the clock signal configuration as shown in the figure are as follows: = The natural synchronization state mode of the data is included, and the recovery clock is sampled in: The data is sampled. Compared with the coffee, it can be more accurately executed. As shown, when the number of signal combinations that may actually appear is: 7, the "signal of the household is two data signals and the absolute difference of the one-time signal - and = 1" At the same time, the clock signal will be generated unconditionally, and the number is simultaneously sent-separated control signal or -= like poor. Although the symbol is positive, it is recognized as the transmission m symbol is negative, it is recognized as being sent. 0. Tian β Figure 8 is another example of multi-level signal transmission – the sound level signal transmission can be used – as shown in Figure 5, between the inter-machined driving integrated circuit interface. 6 and FIG. 8, the timing controller 14 converts the data to the === reference voltage signal 'converts the clock to a signal whose voltage is less than the reference voltage of the box' and embeds the converted clock in the signal 13 1311305 The converted data signals are multiplexed and then transmitted. In addition, when the received signal dust is greater than a reference voltage, the line drives the integrated circuit - 24 (ie, the receiving terminal) to receive The signal is restored to the data when the received signal voltage When the reference voltage is less than the reference voltage, the row drives the integrated circuit 24 (ie, the receiving terminal) to restore the received signal to the talk clock. As shown in the figure, 'the data signal is different because the clock signal does not have such as 1 and 0. The concept of 'three steps is enough for multi-level signal transmission. That is, when the absolute value of the difference between two input signals |Vin,p -Vin,n| is larger than the amplitude of the reference signal |Vrefh -Vrefl| The two input signals will be identified as the physical signal 'and the data will be identified as 1 or 0 according to the symbol of the data signal. Conversely, the absolute value of the difference between the two input signals | Vin, P - Vin , n| is smaller than the amplitude of the reference signal 丨Vrefli, when the two input signals will be recognized as the clock signal. Therefore, unlike the requirement of the four-order level in Figure 7, MVx is required (△% refers to the miscellaneous The voltage operation method of FIG. 8 can be operated at a low voltage of 2 Δν , because the three-order is sufficient for the method of FIG. 8. FIG. 9 is another schematic diagram of multi-level signal transmission. The multi-level signal material can be hidden As shown in Figure 5, the interface between the integrated circuit is driven. In the case of the example shown, 'the clock signal and the capital (4) are read and sent, but because it is for each data pulse, it needs to be DLT, Ρττ 疋 畀 畀 日 日 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Moreover, when the private reading speed of the data is not very high, it is advantageous to configure the clock recovery circuit as a simple circuit system by including the * field: it is necessary to cut the clock of each material. The method shown in the figure will solve such problems. Although the method shown in Figure 9 is similar to that of Figures 7 and 8 , the difference is that the clock signal is transmitted in the - corresponding data period - half period. . When the absolute value of the difference between the two input signals |Vm,p-Vin,n^ is greater than the amplitude IV of the reference signal, her-Vrefl丨, the two input signals will be recognized as data signals, and according to the symbol of the data signal The data is identified as 丨 or 〇. Conversely, when the absolute value of the difference between the two input signals |Vin,p -Vin,n| is smaller than the amplitude of the reference signal IVrefh -Vrefl|, the two output signals will be unconditionally recognized as the clock signal. As indicated by the recovered data and time signal, the clock signal is located in the middle of each data transition period. The purpose of the clock recovery circuit is to place the clock at the most ideal sampling position, i.e., in the middle of the data transition period, and it is apparent that the configuration of the present invention satisfies this requirement. That is, when the length of the clock signal is set to be the same as the length of the data, the period of the data signal can be equally divided to restore the clock signal for each of the data at the receiving terminal. Through this process, the received data signal can be recovered by a simple cloud sampling circuit. According to the structure shown in Fig. 9, the symbol of the touched data is changed only when the received data exceeds a threshold value. The print changes the value according to the sign of the data only when the absolute value |Vin,p -Vin,n| of the difference between the two input signals is greater than the amplitude |Vrefh - Vrefl| of the reference signal. 15 1311305 In contrast, there may be two configurations for the clock. First, similar to the data 'if the polarity is changed only when the absolute value of the two input signal values |Vin,p Vin,n| is smaller than the amplitude of the reference signal | vrefj^vrefll' The data can be sampled at both the rising and falling edges of the pulse. Second, contrary to the above, when the absolute value of the two input signal difference I Vin,p - Vin,n| is larger than the amplitude of the reference signal I Vrefh - Vrefll, and when the two input signals are different The absolute value |Vin,p -Vin,n| is smaller than the amplitude of the reference signal IVrefh - Vrefl| is regarded as the transition period of the clock, then the data is in the clock signal as shown in FIG. Sampled at the rising edge. Although the clock signal is smaller than the data signal as shown in FIG. 9 but when the amplitude of the clock signal is greater than the amplitude of the data signal, the clock signal can be embedded in each of the data signals. In the signal, those skilled in the art can easily understand the technology. Therefore, a detailed description about this technique is omitted. Figure 10 is a schematic diagram of still another example of multi-level signal transmission that can be used in an interface between a timing controller and a row driver integrated circuit as shown in Figure 5. Referring to Figure 10, the polarity of the clock signal follows the polarity of the previous data. That is, the data η-1 has the same polarity as the clock, and the terminal of the clock is increased to additionally generate the same virtual signal as the previous data signal (data η-1). With this virtual data, sufficient rise time and fall time can be obtained. The virtual data is added to prevent the clock from accelerating or delaying in the form of Figure 7 according to the previous data 16 1311305. So in this case, is it reduced? The possibility of picking up the jitter (caused by the data. The transition is considered to be the partial slope between the transitions of the clock signal) is therefore advantageous for the high speed transmission of the towel. That is, although the zero-over position used to generate the clock signal depends on the value of the previous data in the situation of FIG. 7, it is advantageous to not generate the zero-pattern related jitter in the case of FIG. 1(). . [Second Embodiment] Fig. 11 is a view showing the structure of a display in a panel according to a second embodiment of the present invention, and for ease of understanding, Fig. 12 is a view only showing the timing control H and line of Fig. 11 Schematic diagram of driving the integrated circuit clock and data. s x , compared to the first embodiment and the second embodiment, the second embodiment uses a point-to-point scheme, and the first embodiment uses a point-to-point scheme. Since the second embodiment is used in addition to the point-pairing scheme, the second embodiment is the same as the second and the same 'so that Figs. 7 to i. The multi-level signal transmission described in the timing controller for the interface between the moving body circuits is described in the following example. However, in the case of the first embodiment, 4 = is connected to the -row drive integrated circuit; and in the case of the second embodiment, the differential pair is connected to the two-row drive integrated circuit 2S. Therefore, in each case, the data transmitted by the differential pair is twice as large as the embodiment. The invention is characterized in that the display panel of the present invention comprises various display panels, and the multi-level signal transmission method of the built-in clock signal can be used for 17 1311305.
了序控制器與顯示軀動器積體電路（DDI)間，如.TFT-LCD 曰液晶顯示器）、S™_LCD、Ch'LCD、FLCD (鐵電液 日曰顯示5| ")、i 顯示器h咖。讀顯示面板）、GELD(有機電激發光 另^颂然可採用熟悉此項技術者所熟知之普通多位 測器/ @ Χμ&本發明之用於復原時脈及資料之多位階檢Between the sequence controller and the display body integrated circuit (DDI), such as .TFT-LCD 曰 liquid crystal display), STM_LCD, Ch'LCD, FLCD (ferroelectric liquid display 5| "), i Display h coffee. Read display panel), GELD (organic electro-optic light can also be used by ordinary multi-position detectors familiar to those skilled in the art / @ Χμ& The multi-level inspection of the present invention for restoring clock and data
率二且：日!脈頻率f之單位可與將被多工化之資料的頻 率=2母一該等將被多工化之資料各可包含該時脈頻 1號之頻率可係將被多卫化之資料頻率的_ = 根據時脈訊號之頻率f，可利用DLX或PLL 之頻率’或當每一資料包含一時脈訊號 pLL。、、R|fl號可被用於資料取樣而不必利用DLL或 二ί戶Γί ’根祕時脈訊號之多位階訊號發送方法 及利用本發明相同方法_顯示面板之 之實施例可被獲得;且與習知技術相= 減）線路數目’ U以改良麵特性。此外，不需要去偏斜 之步驟；而當經由復原時脈而獲得更精奴資料取樣時， ;且輯本發額決了訊號 【圖式簡單說明】 圖1係說明—習知RSDS(縮減擺動差動訊號發送）實 18 1311305 施例之示意圖。 圖2係說明一習知最小LVDS (低電壓差動訊號發送） 實施例之不,意圖。 圖3係說明一習知PPDS (點對點差動訊號發送）實施 例之示意圖。 圖4係説明一種用於從位在RSDS中之相鄰行驅動積 體電路處以串聯形式接收一時脈訊號之方法的示意圖；其 中，該行驅動電路之配置具有一鏈結構。 圖5係一說明根據本發明第一實施例之内嵌時脈面板 内顯示器結構之示意圖。 圖6係一為求便於理解而僅說明圖5在一時序控制器 與行驅動積體電路之間發送時脈及資料之結構示意圖。 圖7至圖10係說明圖5用於時序控制器與行驅動積體 電路之間的介面之多位階訊號發送方法範例之示意圖。 圖11係一說明根據本發明第二實施例之内嵌時脈面 板内顯示器結構之示意圖。 圖12係一為求便於理解而僅說明圖11在一時序控制 器與行驅動積體電路之間發送時脈及資料之結構示意圖。 【主要元件符號說明】 10:RSDS時序控制器 11 :最小LVDS時序控制器 12、13 : PPDS時序控制器 19 1311305 14、15 :用於内嵌時脈多位階訊號發送方法中之時序控 - 制器 . 20 : RSDS行驅動積體電路 21 :最小LVDS行驅動積體電路 22、23 : PPDS行驅動積體電路 24、25 :用於内嵌時脈多位階訊號發送方法中之行驅動 積體電路 30:列驅動積體電路 40 :驅動面板 20Rate two and: day! The frequency of the pulse frequency f can be the frequency of the data to be multiplexed = 2 mothers, the data that will be multiplexed, each of which can include the frequency of the clock frequency 1 can be _ = the frequency of the multi-defense data _ = according to the frequency f of the clock signal, the frequency of the DLX or PLL can be used 'or when each data contains a clock signal pLL. The R|fl number can be used for data sampling without using a DLL or a multi-level signal transmission method of the root clock signal and an embodiment using the same method of the present invention - a display panel can be obtained; And with the prior art = minus the number of lines 'U to improve the surface characteristics. In addition, there is no need to go to the step of skewing; and when the more refined slave data is sampled through the recovery clock, and the copy of the signal is decided [simplified description of the schema] Figure 1 is a description - conventional RSDS (reduced) Swing differential signal transmission) Real 18 1311305 Schematic diagram of the example. Figure 2 illustrates an example of a conventional minimum LVDS (Low Voltage Differential Signal Transmission) embodiment. Figure 3 is a schematic diagram showing a conventional PPDS (Peer-to-Peer Differential Signal Transmission) embodiment. Figure 4 is a diagram showing a method for receiving a clock signal in series from an adjacent row driving integrated circuit in the RSDS; wherein the row driving circuit is configured to have a chain structure. Fig. 5 is a view showing the structure of an in-line clock panel display according to a first embodiment of the present invention. FIG. 6 is a structural diagram showing the transmission of clock and data between a timing controller and a row driving integrated circuit in FIG. 5 for ease of understanding. 7 to 10 are diagrams showing an example of a multi-level signal transmission method for the interface between the timing controller and the row driving integrated circuit of Fig. 5. Fig. 11 is a view showing the structure of an in-line clock panel display according to a second embodiment of the present invention. FIG. 12 is a block diagram showing the structure of the clock and data transmitted between a timing controller and a row driving integrated circuit in FIG. 11 for ease of understanding. [Main component symbol description] 10: RSDS timing controller 11: Minimum LVDS timing controller 12, 13: PPDS timing controller 19 1311305 14, 15: Used for timing control in embedded clock multi-level signal transmission method 20: RSDS row driving integrated circuit 21: minimum LVDS row driving integrated circuit 22, 23: PPDS row driving integrated circuit 24, 25: for driving the driving complex in the embedded clock multi-level signal transmitting method Circuit 30: Column Drive Integrated Circuit 40: Drive Panel 20