1308338 14744twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本發明是有關於非易失性記憶體，特別是涉及提高氮 化物唯項圮憶體(nitride reacj-oniy mem〇ry，N〇RM)抹除一 致性和鑑別邊緣記憶胞(marginal mem〇ry ceU)的裝置和方 法。 【先前技術】 P过著對/肖費1;子產品需求的增加，如數位照相機、 MP3播放斋、膝上型電腦和個人數位助理（pDA)等，都 需要使用非易失性記憶體裝置存儲大量資料。 氮化物唯瀆記憶胞包括氧化物_氮化物_氧化物(ΟΝΟ) 閘極介電層（gate dielectric)和位於該ΟΝΟ閘極介電層之上 的控制閘極(controlling gate)。它允許ΟΝΟ閘極介電層的 氮化物層内兩個在空間上分隔的電荷分佈分別位於記憶胞 的源極和汲極節上。結果，0Ν0介電層能夠在這些節上每 個記憶胞中存儲兩位元的資訊。因此，氮化物唯讀記憶體 的2位元記憶胞至少因為其能夠減小記憶體陣列的尺和 降低非易失性記憶體裝置的成本而仍然具有吸引力。 氮化物唯讀記憶體單元可以使用“通道熱電子注 射（channel hot-electron injection)編程。在程式操作中， 取決於施加在源極、汲極和閘極節點的電壓，汲極失斷區 (pinch-off region)中的電子可以向ΟΝΟ氮化物介電層移動 從而對記憶胞編程。氮化物唯讀記憶胞可以透過‘‘能隙門 熱黾 /同;主入（band-to-band hot hole injection)被袜除 / I1* _ 1308338 14744twf.doc/g 除操作中，取決於施加的電壓，可通過能隙間穿峻 (band_to-band tunneling)在適當節（junction)的 ΟΝΟ 電介質 下生成電洞。如果在通道區(channel region)生成有強橫向 電場(lateral electric field)，這些電洞就能夠被注入ΟΝΟ電 介質。這些注入的電洞能夠與存儲的電子結合’從而為要 求的節之上的特定位元對記憶胞進行抹除。 抹除操作很大程度上依賴於在通道區内生成強橫向 電場。為了正確地執行抹除操作，必需在記憶胞的源極、 汲極和閘極節點上施加合適的電壓。圖丨和圖2是現有技 術中為了執行抹除操作被施加節點電壓的氮化物唯讀記憶 體單兀。參見圖1，可以使用能隙間熱電洞注射對氮化物 唯讀記憶胞執行單側抹除。例如，為了抹除位元丨，節點 1〇1接义來自負泵電路(negative pump circuit)的㈠負電 4郎點1 〇2接受來自正泵電路(positive pump circuit)的(十) 正電壓，節點1〇3接地。為了抹除位元2 ,節點1〇1接受 來自負泵電路的㈠負電壓，節點102接地，節點103接受 來自正泵電路的(+)正電壓。表丨列出了如上所詳述的圖i 中節點的電壓和連接。 表1 (現有的抹逆^作） 節點 抹除位元1 抹除位元2 -~~~—. 節點101 (-)負電壓 (-)負電壓 節點102 ~~——_ (+)正電壓 接地 節點103 ----__ 接地 (+)正電壓 ______________ 1308338 14744twf.doc/g 該現有技術的氮化物唯讀記憶胞的缺點是如果分別 施加在節點1〇2或103用來抹除位元1和位元2的(+)電壓 起過了 §己憶胞的擊穿電壓(punch_through voltage)，正栗電 路就會失效’導致抹除操作失敗。當位元線偏壓大於擊穿 電壓時就會發生這種情況。例如，當源極和汲極之間存在 很大的偏壓時，在通道區就可發生擊穿，導致電壓差下降。 電壓差下降會導致橫向電場強度不夠，從而對抹除操作產 生影響或導致沒有將位元抹除。 參見圖2，為了抹除位元丨，節點2〇1接受來自負泵 電路= (-)負電壓、節點202接受來在正泵電路的(+)正電 壓、即點203浮置。為了抹除位元2，節點2〇1接受來自 負泵電路的㈠負電壓、節點202浮置、節點2〇3接受來在 正泵電路的⑴正電壓。表2列出了如上所詳述的圖 點的電壓和連接。 表2 (現有的抹除操作） 節點 節點201 節點202 節點203 抹除位元1 (-)負電壓_ (+)正電壓 浮置 抹除位元2 (-)負電壓 浮置 (+)正電壓 202 術的氣化物唯讀記憶胞存在的缺點是節點 合$ _/、、了抹除位元1或位元2而處於浮置時，可能 i :::線的耦合或漏電流而被耦接到不確定的電壓標 準’ 操作的失敗。特別是電壓標準的不確定可= 1308338 14744twf.doc/g 會導致對全部記憶胞抹除的不一致。 逛有，現有技術的N0RM記憶體陣列中的部分記憶 胞^會發生邊緣缺陷(marginaIdefect)，如埋入沒極氧化 物，a源極·;及極漏電流等。這種邊緣缺陷可導致製造出 的氮化物唯讀記憶體陣列產生嚴㈣題，而在測試中對這 些缺陷進行鑑別是困_。如上所述，如果記憶胞的一側 接地，另一側接正泵電路，位元線偏壓可能會超過擊穿電 壓’導致泵f路失效。财，如果記憶胞的—側在抹除期 間浮置，該記憶胞就能被耦接到不確定的電壓，導致抹除 操作的不穩定。例如，抹除操作後臨界電壓(Vt)的分佈會 變得更廣。不確定電壓標準的變化可導致對全部記憶胞抹 除的不一致。 由此可見，有必要提供一種改進的非易失性I化物唯 讀記憶體元件和氮化物唯讀記憶胞操作測試方法以鑑別邊 緣缺陷。 【發明内容】 根據本發明的一個方面’是一種氮化物唯讀記憶體陣 列’其包括多個記憶胞和第一、第二位元線。所述第一、 第二位元線耦接到所述記憶胞的相對兩側。在抹除操作 中，記憶胞的一側接收一個正電壓並而另一侧耦接到一共 通節點或受限電流源(limited current source)。 根據本發明的又一個方面，是一種確定氮化物唯讀記 憶體陣列中的邊緣記憶胞的方法，該方法包括將所述記憶 體陣列内的記憶胞的位元預編程到一預定值。抹除所述記 1308338 14744tvvf；d〇c/g 界。及據抹除期間所述記憶胞的—— 所述記憶料财的邊緣記'_。 根據本發明的又一彳 θ & 胞，包括第一、筮 疋種氮化物唯讀記f咅 第二J 4二和第三節點。第-節點接受-負雷， 即點接受—正電壓或搞接到一 、=。 電，接到-共通節點，當第二節點^::接 弟:即點輕接到—共通節點，該共通節點 电昼 一個氮化物唯讀記憶胞的第三節點。‘'至少 胞，if第本發=又—/时面，是™種氮化物唯讀記_ ，括第―、第二和第三節點。第—節點接受—l ::即點接受一正電壓或输卜受限電流源。第三：: 正電壓或耦接到該受限電流源，當第二節轉= :::另第Γ郎點耦接到受限電流源’該受限電流源耦接 至夕另一個氮化物唯讀記憶胞的第三節點。 根據本發明的又—個方面，是—種氮化物唯讀記 車列二包括多個記憶胞、一負泵電路、—正泵電路以：二 共通節點。每個記憶胞都具有第—、第H節點。一 泵電路向所述記憶胞的第-節點提供負電壓。負 所述記憶胞的第二或第三節點提供正電壓。共通節 限電流源耦接到第二或第三節點，該第二或第三節點2又 到共通節點或受限電流源，而另一節點耦接到正接 路。 表電 根據本發明的又一個方面，是一種鑑別記憶胞 法。將包括有多個記憶胞塊的記憶體陣列編程。抹除記情 1308338 14744twf.doc/g 記憶胞。 圖3是-個為進行抹除操作具有能夠輕 的示例性節點電_氮化物唯讀記憶胞。例如，為=點 =[節點301接受來自負果電路的㈠負電壓、節= 接文來自正泵電路的(+)正電壓、節點3 點。為了抹除位元2,節點3〇1接受來自負^上通郎 電壓、節點302 _到共通節點、節點3〇3接負 點位元！和位元2 ^ 3G2f °上所_的圖3中抹除節 表3 2的302和303的電壓和連接關係。 3031308338 14744twf.doc/g IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a nonvolatile memory, and more particularly to an improvement of a nitride reacj-oniy mem〇ry (nitride reacj-oniy mem〇ry, N〇RM) Apparatus and method for erasing consistency and identifying marginal memory cells (marginal mem〇ry ceU). [Prior Art] P is over / Xiao Fei 1; the increase in demand for sub-products, such as digital cameras, MP3 playback, laptops and personal digital assistants (pDA), requires the use of non-volatile memory devices. Store a lot of data. The nitride-only memory cell includes an oxide-nitride-oxide (gate) gate dielectric and a control gate located above the gate dielectric layer. It allows two spatially separated charge distributions within the nitride layer of the gate dielectric layer to be located on the source and drain nodes of the memory cell, respectively. As a result, the 0 Ν 0 dielectric layer is capable of storing two bits of information in each of the memory cells. Therefore, the 2-bit memory cells of nitride read-only memory are still attractive at least because of their ability to reduce the size of the memory array and reduce the cost of non-volatile memory devices. The nitride read-only memory cell can be programmed using channel hot-electron injection. In program operation, depending on the voltage applied to the source, drain and gate nodes, the bucking break region ( The electrons in the pinch-off region can move toward the silicon nitride dielectric layer to program the memory cell. The nitride read-only memory cell can pass through the ''energy gap' heat/same; the main input (band-to-band hot) Hole injection) is removed by the socks / I1* _ 1308338 14744twf.doc/g In addition to the operation, depending on the applied voltage, electricity can be generated by the band_to-band tunneling in the appropriate junction dielectric. Holes. If a lateral electric field is generated in the channel region, these holes can be injected into the germanium dielectric. These injected holes can be combined with the stored electrons to make it above the required section. The specific bit erases the memory cell. The erase operation relies heavily on generating a strong lateral electric field in the channel region. In order to perform the erase operation correctly, it must be in the memory cell. Appropriate voltages are applied to the pole, drain and gate nodes. Figure 2 and Figure 2 are nitride read-only memory cells that are applied to the node voltage in order to perform the erase operation in the prior art. Referring to Figure 1, the energy gap can be used. The hot hole injection performs a one-sided erase on the nitride read-only memory cell. For example, in order to erase the bit 丨, the node 1〇1 is connected to the negative pump circuit (1) negative power 4 lang 1 〇 2 accept The (10) positive voltage from the positive pump circuit, node 1〇3 is grounded. To erase bit 2, node 1〇1 accepts the (a) negative voltage from the negative pump circuit, node 102 is grounded, node 103 accepts The (+) positive voltage from the positive pump circuit. The table lists the voltages and connections of the nodes in Figure i as detailed above. Table 1 (Existing Wiper Control) Node Erase Bit 1 Erasing Bits 2 -~~~-. Node 101 (-) Negative voltage (-) Negative voltage node 102 ~~——_ (+) Positive voltage ground node 103 ----__ Ground (+) Positive voltage ______________ 1308338 14744twf. Doc/g The disadvantage of this prior art nitride read-only memory cell is that if applied to node 1 respectively 2 or 103 used to erase 'lead (+) voltage breakdown voltage § played memory cell has the (punch_through voltage), Li n-1 circuit will fail bit 2 and bit erase operation failed. This occurs when the bit line bias is greater than the breakdown voltage. For example, when there is a large bias between the source and the drain, breakdown can occur in the channel region, resulting in a drop in voltage difference. A drop in the voltage difference can result in insufficient lateral electric field strength, which can have an effect on the erase operation or cause the bit to be erased. Referring to Figure 2, to erase the bit 丨, node 2〇1 accepts a negative voltage from the negative pump circuit = (-), node 202 accepts a (+) positive voltage at the positive pump circuit, i.e., point 203 floats. To erase bit 2, node 2〇1 accepts (a) a negative voltage from the negative pump circuit, node 202 floats, and node 2〇3 accepts a (1) positive voltage at the positive pump circuit. Table 2 lists the voltages and connections of the points detailed above. Table 2 (Existing erase operation) Node node 201 Node 202 Node 203 Erase bit 1 (-) Negative voltage _ (+) Positive voltage floating erase bit 2 (-) Negative voltage floating (+) positive The disadvantage of the vapor-only read-only memory cell of voltage 202 is that the node is $_/, and when the bit 1 or bit 2 is erased and is floating, the coupling or leakage current of the i:: line may be Coupling to an indeterminate voltage standard 'operation failure. In particular, the uncertainty of the voltage standard can be = 1308338 14744twf.doc/g will result in inconsistencies in the erasure of all memory cells. Some of the memory cells in the prior art N0RM memory arrays have marginal defects, such as buried polar oxides, a source, and polar leakage current. Such edge defects can lead to the production of nitride-only memory arrays that are subject to strict (4) problems, and it is difficult to identify these defects during testing. As described above, if one side of the memory cell is grounded and the other side is connected to the positive pump circuit, the bit line bias may exceed the breakdown voltage' causing the pump to fail. If the memory cell is floating during erasing, the memory cell can be coupled to an indeterminate voltage, resulting in instability of the erase operation. For example, the distribution of the threshold voltage (Vt) becomes wider after the erase operation. Uncertain variations in voltage standards can lead to inconsistencies in the erasure of all memory cells. Thus, it would be desirable to provide an improved non-volatile I-form read-only memory component and a nitride read-only memory cell operational test method to identify edge defects. SUMMARY OF THE INVENTION According to one aspect of the invention, a nitride read-only memory array includes a plurality of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cell. In the erase operation, one side of the memory cell receives a positive voltage and the other side is coupled to a common node or a limited current source. In accordance with still another aspect of the present invention, a method of determining an edge memory cell in a nitride read-only memory array, the method comprising preprogramming a bit of a memory cell within the memory array to a predetermined value. Erase the note 1308338 14744tvvf;d〇c/g bound. And according to the memory cell during the erase period - the edge of the memory is recorded as '_. Another 彳 θ & cell according to the present invention includes a first 筮 氮化 nitride read only f 咅 a second J 4 nd and a third node. The first node accepts - negative lightning, that is, accepts - positive voltage or engages with one, =. The power is connected to the common node, and when the second node is:: the partner: that is, the light is connected to the common node, and the common node is the third node of the nitride-reading memory cell. ‘'At least the cell, if the first hair=again-/the time is the TM nitride reading _, including the first, second and third nodes. The first node accepts -l:: a point accepts a positive voltage or a restricted current source. Third:: a positive voltage or coupled to the limited current source, when the second pitch = ::: another Γ point is coupled to the limited current source 'the limited current source is coupled to another nitrogen The third node of the read-only memory cell. According to still another aspect of the present invention, a nitride read-only train includes two memory cells, a negative pump circuit, and a positive pump circuit to: a common node. Each memory cell has a first and an Hth node. A pump circuit provides a negative voltage to the first node of the memory cell. Negative The second or third node of the memory cell provides a positive voltage. A common limiting current source is coupled to the second or third node, which in turn is to the common node or the restricted current source, and the other node is coupled to the positive interface. Table Electric According to still another aspect of the present invention, a method of identifying a memory cell. A memory array including a plurality of memory cells is programmed. Erase the quotation 1308338 14744twf.doc/g Memory cells. Figure 3 is an exemplary node-electron-nitride-only memory cell that can be lightly erased. For example, = point = [node 301 accepts (a) negative voltage from the negative fruit circuit, node = text (+) positive voltage from the positive pump circuit, node 3 points. In order to erase the bit 2, the node 3〇1 accepts the voltage from the negative voltage, the node 302_ to the common node, and the node 3〇3 to the negative bit! And the voltage and connection relationship of 302 and 303 in Table 3 of the erasing section in Figure 2 and the bit 2 ^ 3G2f °. 303
座避節 (+)正電壓 卽 節點301 節點302 節點303 參見表 3，τ一· 過程中，共通節在抹除位元1和位元2的 適當的值，比如〜個^供的電壓標準可以被維持在-個 仍然足夠低以便維憶胞擊穿的足夠高的值，但是 採用這種方式，將除位凡所需的強横向電場。 善記憶胞的抹1=地#3()3_到該共通節點可改 的示例性節點電受限電流源 位元I，節點40!接受 例如’為了抹除 負果電路的㈠負電覆、節點402 接受來自 流源的電流。為了抹除位元2，節 t來自受限電 路的㈠負電壓 '節點4G2接受來自 X來自負栗電 點403接受來自正泵電路的（+)正電Π =的電流、節 詳述的圖4中抹除位元Ησ位元 了如上所 壓和連接關係。 ρ ^ 402和403的電 表4 (利用電流源的抹險樺作） 402 節點402 節點403 ^表 4 , ^上!^壓— 標準能夠 泵電路 403的電壓標準就能料動態的並且 準相關。例如，如果對節…、他即點的電壓才 元線步進(stepping)，那户二 勺内置抹除操作使用了 { gJ那麼郎點403的電爆許唯外At々A、木 限電流源調節。位元線步 就― 在一次抹除後抹除校驗失敗，那種過程：如^ 壓標準重試一次扶广。、吾‘卩么就S加汲極側位兀線1 胞的節點402 4節；二，，為陣列中兩個或更多記必 的，那麼該設計mi通常是_到同—受限電源2 構就可提高陣财的記憶胞的抹除-至 1308338 14744twf.doc/g 性。 …圖：疋肊夠具有圖3和圖4中所示的記憶胞的氮化物 ，讀記憶陣列。例如’記憶體陣列中的多個記憶胞如 月b夠參照上述的記憶胞。這些記憶胞5〇3按照“η”行排 列，能夠在每個記憶胞的源極節和汲極節上儲存兩位元資 5fl。在5亥例中’記憶胞第一行的閘極節點與字元線饥〇 耦接，第n行記憶胞的閘極節點與第η行字元線WLn耦 接。記憶體陣列500可以採用任意數量的記憶胞和任音 的記憶胞。 ~ ^記憶體陣列500還包括一虛擬接地陣列5〇2和—放電 系統501。在本例中，虛擬接地陣列5〇2輸出多個金屬位 元線，例如位元線MBL0到MBL3，其分別在具有串列排 列的選擇輸入（SEL0、SEL1)和（SEL2、SEL3)的選擇 電晶體之間的節點處耦接，以便選擇性地提供電壓和/或電 流。用以控制耦接到MBL的選擇電晶體使其閘極節點耦 接到對應的選擇輸入（例如：SEL0、SEU、SEL2和SEL3 )， • 這些選擇輸入有選擇地導通與其對應的電晶體。在本例 中’選擇電晶體耦接到對應的位元線BL0至BL7。取決於 哪個選擇電晶體是導通的，位元線能夠被耦接到共通節點 或通過放電系統501内的金屬位元線（MBL)耦接到受限 電流源，參見圖6所示並參閱下面的詳細說明。 例如，如果選擇輸入SEL0導通，位元線BL0與能夠 被耦合到共通節點或放電系統501内受限電流源的金屬位 元線MBL0耦合。同樣，如果選擇輸入SEL1導通，位元 13 1308338 14744twf.doc/g 線BL2與能夠_合到共通節點或受限電流源的金屬位元 線MBL0麵合。採用這種方式，位元線Bl〇和犯 夠被耦合到共通節點或受限電流源。另一些字元線也可以 採取與位7L線BLG# BU相同的方式通過金屬位元線 MBL1到MBL3被麵合到共通節點或放電系統5〇1内 限電流源 這樣’選擇輸入就允許對記憶胞某些節_接到丘通 # _點或受限電流源的控制。特別是，偶數位元連接線了例 如’ BL0、BL2、BL4和BL6，與耦接到選擇輸入SEL〇和 SEL1的電晶體節聽接。奇數位元連接線，例如，犯、 BL3、BL5和BL7 ’與耦接到選擇輸入狐2和狐3的電 晶體節點搞接。採用上述方式，位元連接線組與其他位元 連接線組配對。例如，偶數位元連接線BL〇和Bl2與奇 數位連接BU和BL3配對，以便至少控制四列中㈣個 記憶胞的抹除。 81 6是圖5的放電系統的較為詳細的示意圖。放電系 統包括節點601和602和多個放電或下拉電晶體 f DISCH η，耦合到對應的金屬位元線MBL〇至MBLn。 f點601和602能夠作為共通節點或電流源或連接到共通 節點的電流源。在本例中，節點601與放電電晶體DISCH 〇、DISCH2和DISCH n-1耦接並且節點6〇2耦接到放電電 晶體msCH卜mSCH n-2和DISCH n。當放電電晶體導 通時，放電系統501可連接金屬位元線mbl到共通節點 或作為受限電流源。 〃 ' 14 1308338 14744twf.d〇c/g 在一個實例中’節點601和602可以是共通節點或是 ，連接到共通節點，例如浮置接地或正電壓源。如果共通 即點是正電壓源，那麼來自此正電壓源的電壓標準應該被 設定為即足夠高以阻止擊穿又足夠低以維持正確抹除所需 要的杈向電場。如果節點601和602是共通節點並且某個 特定的放電電晶體處於導通狀態，那麼連接於放電電晶體 的對應金屬線就會被耦接到共通節點。如果放電系統5〇1 φ 作為叉限電流源，那麼節點601或602可以是電流源或連 接到電流源。當放電電晶體導通時，會由作為電流源或連 接到電流源的對應節點601或602放電，從而提供受限電 流源。Block avoidance section (+) positive voltage 卽 node 301 node 302 node 303 Referring to Table 3, in the process of τ··, the common section erases the appropriate values of bit 1 and bit 2, such as the voltage standard of ~ It can be maintained at a sufficiently high value that is still low enough to break the cell, but in this way, the strong transverse electric field required will be removed. The memory of the good memory 1 = ground #3 () 3_ to the exemplary node can be modified by the exemplary node electrically limited current source bit I, node 40! accepts, for example, in order to erase the (a) negative power of the negative fruit circuit, Node 402 accepts current from the source. In order to erase the bit 2, the section t from the limited circuit (a) the negative voltage 'node 4G2 accepts the current from X from the negative pump point 403 to receive the (+) positive Π = from the positive pump circuit, a detailed diagram of the section In 4, the bit Η σ bit is erased and the relationship is as described above. Table 4 of ρ ^ 402 and 403 (using the current source of the harmed birch) 402 Node 402 Node 403 ^ Table 4, ^Up!^Pressure - Standard ability The voltage standard of the pump circuit 403 can be dynamic and quasi-correlated. For example, if the voltage is stepped on the section..., the voltage of the point, the second scooping erase operation of the household uses { gJ then Lang point 403 of the electric explosion Xu Wei outside At々A, wood limit current Source adjustment. The bit line step is to erase the verification failure after one erasure, and the process: such as ^ pressure standard retry once. I, 卩 就 就 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S 2 The structure can improve the memory of the memory cells - to 1308338 14744twf.doc / g sex. ...Fig.: A nitride having a memory cell as shown in Figs. 3 and 4, a read memory array. For example, a plurality of memory cells in the memory array, such as the month b, are sufficient to refer to the memory cells described above. These memory cells are arranged in "n" rows, and can store two yuan 5fl on the source and the dipole nodes of each memory cell. In the case of 5 hai, the gate node of the first row of the memory cell is coupled to the word line hunger, and the gate node of the nth row of memory cells is coupled to the η row of word line WLn. The memory array 500 can employ any number of memory cells and any memory cells. The memory array 500 also includes a virtual ground array 5〇2 and a discharge system 501. In this example, the virtual ground array 5〇2 outputs a plurality of metal bit lines, such as bit lines MBL0 to MBL3, which are selected in a series of select inputs (SEL0, SEL1) and (SEL2, SEL3), respectively. The nodes between the transistors are coupled to selectively provide voltage and/or current. The select transistor coupled to the MBL is coupled to its gate node to a corresponding select input (e.g., SEL0, SEU, SEL2, and SEL3), • These select inputs selectively conduct their corresponding transistors. In this example, the 'selective transistor' is coupled to the corresponding bit line BL0 to BL7. Depending on which selection transistor is conductive, the bit line can be coupled to the common node or coupled to the limited current source through a metal bit line (MBL) within the discharge system 501, see Figure 6 and see below. Detailed description. For example, if input SEL0 is selected to be turned on, bit line BL0 is coupled to metal bit line MBL0 that can be coupled to a common node or a limited current source within discharge system 501. Similarly, if input SEL1 is selected to be turned on, bit 13 1308338 14744twf.doc/g line BL2 is coincident with metal bit line MBL0 that can be coupled to a common node or a limited current source. In this manner, the bit line B1〇 and the assertion are coupled to a common node or a limited current source. Other word lines can also be taken in the same way as the bit 7L line BLG# BU through the metal bit lines MBL1 to MBL3 to the common node or the discharge system 5〇1 inner current source so that the 'select input allows the memory Some sections of the cell are connected to the control of Qiutong #_point or limited current source. In particular, even bit connections such as 'BL0, BL2, BL4, and BL6 are audible to the transistor sections coupled to select inputs SEL and SEL1. The odd bit connections, e.g., BL3, BL5, and BL7', are coupled to the transistor nodes coupled to select input fox 2 and fox 3. In the above manner, the bit connection group is paired with other bit connection groups. For example, the even bit connections BL 〇 and B 2 are paired with the odd bit connections BU and BL 3 to control at least the erasure of the (four) memory cells in the four columns. 81 6 is a more detailed schematic diagram of the discharge system of FIG. The discharge system includes nodes 601 and 602 and a plurality of discharge or pull-down transistors f DISCH η coupled to corresponding metal bit lines MBL〇 to MBLn. Point f 601 and 602 can act as a common node or current source or as a current source connected to a common node. In this example, node 601 is coupled to discharge transistors DISCH 〇, DISCH2, and DISCH n-1 and node 6〇2 is coupled to discharge transistors msCH, mSCH n-2 and DISCH n . When the discharge transistor is turned on, the discharge system 501 can connect the metal bit line mbl to the common node or as a limited current source. 〃 ' 14 1308338 14744twf.d〇c/g In one example 'nodes 601 and 602 may be common nodes or connected to a common node, such as a floating ground or positive voltage source. If the common point is a positive voltage source, then the voltage standard from this positive voltage source should be set to be high enough to prevent the breakdown and low enough to maintain the desired slanting electric field. If nodes 601 and 602 are common nodes and a particular discharge transistor is in an on state, the corresponding metal line connected to the discharge transistor is coupled to the common node. If the discharge system 5〇1 φ is the source of the crossover current, then node 601 or 602 can be a current source or connected to a current source. When the discharge transistor is turned on, it is discharged by a corresponding node 601 or 602 that is a current source or is connected to a current source, thereby providing a limited current source.
下面結合圖5和圖6詳細說明記憶胞的抹除操作。泉 見® 5 ’如果在抹除操作中於記憶胞5〇3的侧向施加(+)正 電壓’那麼該側就會戴止對應的放電電晶體並且記憶胞的 相對一側就會耦接到如圖6所示放電系統5〇1内的共 點或受限電流源。 、P _ 例如’在圖5中’要抹除氛化物唯讀記憶胞5〇3的偶 數位元（毗鄰偶數位元線BL0、BL2、BL4、BL6等）， 利用抹除汲極側偏壓的Y_pass閘極和γ_解碼器（或列解 碼器），偶數金屬位元線(MBL0、MBL2等）可被耦接到正 電壓源。奇數金屬位元線(MBL1、MBL3等）可通過相對應 的放電電晶體被耦接到與共通節點或放電系統5〇l中的 流源連接的節點602。為了抹除氮化物唯讀記憶胞的奇數 位元（毗鄰奇數位元線BU、BL3、BL5、BL7等） 15 1308338 14744twf.doc/g 用抹除汲極側偏壓的Y_pass閘極和γ_解碼器（或列解碼 器），奇數金屬位元線(MBL1、MBL3等）可被耦接到正電 壓源。偶數金屬位元線(MBL〇、MBL2等）可通過相對應的 放電電晶體被耦接到與共通節點或電流源連接的節點 601 〇 下面的表5所示為在用戶模式和測試模式下示例性的 抹除圖5所示記憶體陣列5〇〇中的位元所用的電壓值。 表5 測試模式 用戶模式The erasing operation of the memory cell will be described in detail below with reference to FIGS. 5 and 6.泉见® 5 'If a (+) positive voltage is applied laterally to the memory cell 5〇3 during the erase operation, then the corresponding discharge transistor is worn on the side and the opposite side of the memory cell is coupled To a common point or limited current source in the discharge system 5〇1 as shown in FIG. , P _ For example, 'in Figure 5', the even-numbered bits of the memory-only memory cell 5〇3 are to be erased (adjacent to the even-numbered bit lines BL0, BL2, BL4, BL6, etc.), and the drain side bias is erased. The Y_pass gate and γ_decoder (or column decoder), even metal bit lines (MBL0, MBL2, etc.) can be coupled to a positive voltage source. The odd metal bit lines (MBL1, MBL3, etc.) may be coupled to a node 602 connected to a common source or a current source in the discharge system 5〇1 through a corresponding discharge transistor. To erase the odd-numbered bits of the nitride-reading memory cell (adjacent to the odd-numbered bit lines BU, BL3, BL5, BL7, etc.) 15 1308338 14744twf.doc/g Use the Y_pass gate and γ_ to erase the drain side bias A decoder (or column decoder), odd metal bit lines (MBL1, MBL3, etc.) can be coupled to a positive voltage source. The even metal bit lines (MBL〇, MBL2, etc.) can be coupled to the node 601 connected to the common node or current source through the corresponding discharge transistor. Table 5 below shows the example in user mode and test mode. The voltage values used for the bits in the memory array 5A shown in FIG. 5 are erased. Table 5 Test mode User mode
WL MBL 偶數 VG(-3V) VG(-3V) 奇數位元WL MBL even VG(-3V) VG(-3V) odd bit
VD(4-8V) VS(501) VS(501) YD(^8V^ VG(-3V) VD(4-8V) VS(501) VG(-3V)_ VS(501) VD(4-8V)VD(4-8V) VS(501) VS(501) YD(^8V^ VG(-3V) VD(4-8V) VS(501) VG(-3V)_ VS(501) VD(4-8V)
BL偶$ BL奇數 參見圖 5-- 沒極節點輕接到正泵電路並且記二記，503在 到共通節點或放電系統5G1 p二 ；原極_點轉指 入SEL0至SEL3都打開）。流源（例如：選擇輕 _接-個共通節點，被抹除；=二= 1308338 14744twf.doc/g 體陣列中可得到的擬記憶胞(dummy cell)或後備記憶胞取 代缺陷或邊緣記憶胞，如通過重寫擬記憶胞或後備記憶胞 使其成為記憶體陣列中的組成部分。因此可實現陣列的操 作完整性(integrity)或一致性(unif〇rmity)。 參見圖8，為示例性的臨界電壓（ντ)分佈，圖中顯 示出邊緣记憶胞的vt分佈偏離非邊緣記憶胞的分佈。Εγ 代表抹除校驗WL電壓、RD代表讀WL電壓、ρν代表編 程校驗WL電壓。 ' 圖9是鑑別執行缺陷抹除操作的邊緣記憶胞的流程 圖。最初，整個記憶體陣列被預編程為“ 〇”（步驟9〇2)。 接著’整個_被抹除“Ν，’次，例如，通過注入電洞。 如圖8所示1 VT分佈檢查記憶塊，這樣就從非難抹除 位元中鑑別出難抹除位元。 ' 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精 和範圍内’當可作些許之更動與㈣，因此本發明之 範圍當視後附之申請專利範圍所界定者為準。 ° 【圖式簡單說明】 圖1是現有技術的抹除操作中的氮化物唯讀記憶胞。 圖2是另-現有技術的抹除操作中的氣化物唯讀記憶 圖3是-個具有能_接到共通節點的示例性節 壓的氮化物唯讀記憶胞。 ‘電 圖4是-個具有能夠麵接到受限電流源的示例性節點 1308338 l4744twf.doc/g 電壓的氮化物唯讀記憶胞。 ®5是-個具有虛擬接地陣列和放電系統的氣化物唯 讀記憶體陣列。 圖6是圖5的放電系統的較為詳細的示意圖。 圖7是鏗別執行缺陷抹除操作的邊緣記憶胞的一個流 程圖。 圖8是鑑別出邊緣記憶胞所使用的電壓分佈示意圖。 圖9是鑑職行缺陷抹轉作的邊緣記憶胞的流程 P圖。 【主要元件符號說明】 101、102、103、201、2G2、203、301、302、303、 4(Π、402、403 :節點 500 :記憶陣列 501 :放電系統 502 :虛擬接地陣列 503 :記憶胞 ► MBL0〜MBL3 :金屬位元線 WL0〜WLn :字元線 BL0〜BL6 :位元線 SEL0〜SEL3 :選擇輪入 DISCH0〜DISCHn:電晶體 19BL even $BL odd number See Figure 5-- The no-pole node is lightly connected to the positive pump circuit and remembers two, 503 is at the common node or the discharge system 5G1 p2; the original pole _ point is turned into SEL0 to SEL3 are turned on). Stream source (for example: select light_connected-one common node, erased; =2 = 1308338 14744twf.doc/g available dummy cells or backup memory cell substitution defects or edge memory cells For example, by rewriting the pseudo memory cell or the backup memory cell, it becomes an integral part of the memory array. Therefore, the operational integrity or uniformity of the array can be achieved. See FIG. 8 for exemplary The critical voltage (ντ) distribution shows the distribution of the vt distribution of the edge memory cells away from the non-edge memory cells. Εγ represents the erase verify WL voltage, RD represents the read WL voltage, and ρν represents the program verify WL voltage. Figure 9 is a flow chart for identifying edge memory cells that perform a defect erase operation. Initially, the entire memory array is preprogrammed as "〇" (step 9〇2). Then 'whole_ is erased, 'Ν,' times For example, by injecting a hole. The memory block is inspected by a 1 VT distribution as shown in Fig. 8, thus identifying a hard-to-erase bit from the non-difficult erasing bit. 'Although the invention has been disclosed above in the preferred embodiment, However, it is not intended to limit this issue. It is to be understood that the scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a nitride read-only memory cell in a prior art erase operation. Figure 2 is a vapor-only read memory in another prior art erase operation. Figure 3 is a An exemplary throttled nitride read-only memory cell of the common node. Electrode 4 is a nitride read-only memory cell having an exemplary node 1308338 l4744twf.doc/g voltage that can be interfaced to a limited current source. ® 5 is a vapor-only read-only memory array with a virtual ground array and discharge system. Figure 6 is a more detailed schematic of the discharge system of Figure 5. Figure 7 is an edge memory cell that performs a defect erase operation Fig. 8 is a schematic diagram showing the voltage distribution used for identifying the edge memory cells. Fig. 9 is a flow diagram P of the edge memory cells of the foreword defect erasing. [Main component symbol description] 101, 102, 103, 201, 2G2, 203, 301 , 302, 303, 4 (Π, 402, 403: node 500: memory array 501: discharge system 502: virtual ground array 503: memory cell ► MBL0 to MBL3: metal bit line WL0 to WLn: word line BL0 to BL6 : Bit line SEL0 to SEL3: Select round-in DISCH0 to DISCHn: transistor 19